WO2008093579A1 - 積層体、基板の製造方法、基板および半導体装置 - Google Patents

積層体、基板の製造方法、基板および半導体装置 Download PDF

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Publication number
WO2008093579A1
WO2008093579A1 PCT/JP2008/050889 JP2008050889W WO2008093579A1 WO 2008093579 A1 WO2008093579 A1 WO 2008093579A1 JP 2008050889 W JP2008050889 W JP 2008050889W WO 2008093579 A1 WO2008093579 A1 WO 2008093579A1
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WO
WIPO (PCT)
Prior art keywords
substrate
multilayer body
semiconductor device
resin layer
producing
Prior art date
Application number
PCT/JP2008/050889
Other languages
English (en)
French (fr)
Inventor
Junpei Morimoto
Kenichi Kaneda
Original Assignee
Sumitomo Bakelite Company Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Company Limited filed Critical Sumitomo Bakelite Company Limited
Priority to US12/523,391 priority Critical patent/US8455765B2/en
Priority to JP2008556063A priority patent/JPWO2008093579A1/ja
Priority to KR1020097014646A priority patent/KR101103451B1/ko
Priority to CN2008800024672A priority patent/CN101584259B/zh
Publication of WO2008093579A1 publication Critical patent/WO2008093579A1/ja

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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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    • B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H05K1/02—Details
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    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249924—Noninterengaged fiber-containing paper-free web or sheet which is not of specified porosity
    • Y10T428/24994—Fiber embedded in or on the surface of a polymeric matrix
    • Y10T428/24995—Two or more layers
    • Y10T428/249951—Including a free metal or alloy constituent

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Textile Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

　本発明の積層体（１０）は、繊維基材で構成されるコア部（１）を内蔵する樹脂層（２）と、前記樹脂層の片面に接合される金属層（３）とを有する積層体であって、前記繊維基材の厚さが２５μｍ以下であり、前記金属層が前記樹脂層に形成されるビアホールに対応する開口部（３１）を有する。また、本発明の基板の製造方法は、上記に記載の積層体にレーザー（９）照射して前記樹脂層にビアホール（２３）を形成する工程と、前記ビアホール形成後に、前記積層体から前記金属層を除去する工程と、を有する。また、本発明の基板（１００）は、上記に記載の製造方法で得られる。また、本発明の半導体装置（１２）は、上記に記載の基板に、半導体素子（１２１）を搭載してなる。
PCT/JP2008/050889 2007-01-29 2008-01-23 積層体、基板の製造方法、基板および半導体装置 WO2008093579A1 (ja)

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US12/523,391 US8455765B2 (en) 2007-01-29 2008-01-23 Laminated body, method of manufacturing substrate, substrate, and semiconductor device
JP2008556063A JPWO2008093579A1 (ja) 2007-01-29 2008-01-23 積層体、基板の製造方法、基板および半導体装置
KR1020097014646A KR101103451B1 (ko) 2007-01-29 2008-01-23 적층체, 기판의 제조 방법, 기판 및 반도체 장치
CN2008800024672A CN101584259B (zh) 2007-01-29 2008-01-23 层叠体、基板的制造方法、基板及半导体装置

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KR101103451B1 (ko) 2012-01-09
US20100044081A1 (en) 2010-02-25
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JPWO2008093579A1 (ja) 2010-05-20
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CN102176808B (zh) 2014-04-09

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