DE69333548D1 - Halbleiterspeicheranordnung - Google Patents
HalbleiterspeicheranordnungInfo
- Publication number
- DE69333548D1 DE69333548D1 DE69333548T DE69333548T DE69333548D1 DE 69333548 D1 DE69333548 D1 DE 69333548D1 DE 69333548 T DE69333548 T DE 69333548T DE 69333548 T DE69333548 T DE 69333548T DE 69333548 D1 DE69333548 D1 DE 69333548D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- memory device
- operations
- rewrite operations
- internal algorithm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/107—Programming all cells in an array, sector or block to the same state prior to flash erasing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3472—Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/802—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by encoding redundancy signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
- G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/067—Single-ended amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32428492 | 1992-12-03 | ||
JP32428492A JP3347374B2 (ja) | 1992-12-03 | 1992-12-03 | デコーダ回路及び半導体記憶装置 |
JP34948192A JP3159816B2 (ja) | 1992-12-28 | 1992-12-28 | 不揮発性半導体記憶装置 |
JP34948192 | 1992-12-28 | ||
JP30493 | 1993-01-05 | ||
JP00030493A JP3392165B2 (ja) | 1993-01-05 | 1993-01-05 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69333548D1 true DE69333548D1 (de) | 2004-07-15 |
DE69333548T2 DE69333548T2 (de) | 2004-09-30 |
Family
ID=27274405
Family Applications (8)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69333631T Expired - Fee Related DE69333631T2 (de) | 1992-12-03 | 1993-06-25 | Halbleiterspeicheranordnung |
DE69333548T Expired - Fee Related DE69333548T2 (de) | 1992-12-03 | 1993-06-25 | Halbleiterspeicheranordnung |
DE69331090T Expired - Fee Related DE69331090T2 (de) | 1992-12-03 | 1993-06-25 | Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften |
DE69333263T Expired - Fee Related DE69333263T2 (de) | 1992-12-03 | 1993-06-25 | Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften |
DE69333549T Expired - Fee Related DE69333549T2 (de) | 1992-12-03 | 1993-06-25 | Halbleiterspeicheranordnung |
DE69333557T Expired - Fee Related DE69333557T2 (de) | 1992-12-03 | 1993-06-25 | Halbleiterspeicheranordnung |
DE69333606T Expired - Fee Related DE69333606T2 (de) | 1992-12-03 | 1993-06-25 | Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften |
DE69333373T Expired - Fee Related DE69333373T2 (de) | 1992-12-03 | 1993-06-25 | Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69333631T Expired - Fee Related DE69333631T2 (de) | 1992-12-03 | 1993-06-25 | Halbleiterspeicheranordnung |
Family Applications After (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69331090T Expired - Fee Related DE69331090T2 (de) | 1992-12-03 | 1993-06-25 | Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften |
DE69333263T Expired - Fee Related DE69333263T2 (de) | 1992-12-03 | 1993-06-25 | Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften |
DE69333549T Expired - Fee Related DE69333549T2 (de) | 1992-12-03 | 1993-06-25 | Halbleiterspeicheranordnung |
DE69333557T Expired - Fee Related DE69333557T2 (de) | 1992-12-03 | 1993-06-25 | Halbleiterspeicheranordnung |
DE69333606T Expired - Fee Related DE69333606T2 (de) | 1992-12-03 | 1993-06-25 | Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften |
DE69333373T Expired - Fee Related DE69333373T2 (de) | 1992-12-03 | 1993-06-25 | Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften |
Country Status (4)
Country | Link |
---|---|
US (10) | US5452251A (de) |
EP (9) | EP1158532B1 (de) |
KR (1) | KR960007638B1 (de) |
DE (8) | DE69333631T2 (de) |
Families Citing this family (103)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69426818T2 (de) * | 1994-06-10 | 2001-10-18 | Stmicroelectronics S.R.L., Agrate Brianza | Fehlertolerantes Speichergerät, insbesondere des Typs "flash EEPROM" |
EP1176602B1 (de) * | 1994-09-13 | 2004-03-03 | Macronix International Co., Ltd. | Flash EPROM integrierte Schaltungsarchitektur |
JPH08102198A (ja) * | 1994-09-30 | 1996-04-16 | Nec Corp | 電気的書換え可能な不揮発性半導体記憶装置の初期化方 法 |
JP3263259B2 (ja) * | 1994-10-04 | 2002-03-04 | 株式会社東芝 | 半導体記憶装置 |
US5765002A (en) * | 1995-03-13 | 1998-06-09 | Intel Corporation | Method and apparatus for minimizing power consumption in a microprocessor controlled storage device |
US5751629A (en) | 1995-04-25 | 1998-05-12 | Irori | Remotely programmable matrices with memories |
US6416714B1 (en) | 1995-04-25 | 2002-07-09 | Discovery Partners International, Inc. | Remotely programmable matrices with memories |
US6329139B1 (en) | 1995-04-25 | 2001-12-11 | Discovery Partners International | Automated sorting system for matrices with memory |
US5874214A (en) | 1995-04-25 | 1999-02-23 | Irori | Remotely programmable matrices with memories |
US6331273B1 (en) | 1995-04-25 | 2001-12-18 | Discovery Partners International | Remotely programmable matrices with memories |
US6017496A (en) | 1995-06-07 | 2000-01-25 | Irori | Matrices with memories and uses thereof |
EP0741387B1 (de) * | 1995-05-05 | 2000-01-12 | STMicroelectronics S.r.l. | Nichtflüchtige Speicheranordnung mit Sektoren, deren Grösse und Anzahl bestimmbar sind |
JP3710002B2 (ja) * | 1995-08-23 | 2005-10-26 | 株式会社日立製作所 | 半導体記憶装置 |
FR2760544A1 (fr) * | 1997-03-04 | 1998-09-11 | Vernet Sa | Thermostat a montage rapide |
DE19708962C2 (de) * | 1997-03-05 | 1999-06-24 | Siemens Ag | Halbleiterdatenspeicher mit einer Redundanzschaltung |
JP3214395B2 (ja) * | 1997-05-20 | 2001-10-02 | 日本電気株式会社 | 不揮発性半導体記憶装置 |
US6046945A (en) * | 1997-07-11 | 2000-04-04 | Integrated Silicon Solution, Inc. | DRAM repair apparatus and method |
JP3237699B2 (ja) * | 1997-08-11 | 2001-12-10 | 日本電気株式会社 | 半導体記憶装置 |
US6114903A (en) * | 1998-01-14 | 2000-09-05 | Lsi Logic Corporation | Layout architecture for core I/O buffer |
JPH11339493A (ja) | 1998-05-27 | 1999-12-10 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
US6910152B2 (en) * | 1998-08-28 | 2005-06-21 | Micron Technology, Inc. | Device and method for repairing a semiconductor memory |
US6199177B1 (en) * | 1998-08-28 | 2001-03-06 | Micron Technology, Inc. | Device and method for repairing a semiconductor memory |
US6452845B1 (en) * | 1999-01-07 | 2002-09-17 | Micron Technology, Inc. | Apparatus for testing redundant elements in a packaged semiconductor memory device |
JP4446505B2 (ja) * | 1999-01-19 | 2010-04-07 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US6552947B2 (en) * | 1999-04-05 | 2003-04-22 | Madrone Solutions, Inc. | Memory tile for use in a tiled memory |
US6249475B1 (en) * | 1999-04-05 | 2001-06-19 | Madrone Solutions, Inc. | Method for designing a tiled memory |
US6219286B1 (en) * | 1999-06-04 | 2001-04-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory having reduced time for writing defective information |
DE10029835C1 (de) * | 2000-06-16 | 2001-10-25 | Infineon Technologies Ag | Integrierte Schaltung mit Testbetrieb und Testanordnung zum Testen einer integrierten Schaltung |
US6426910B1 (en) | 2000-08-30 | 2002-07-30 | Micron Technology, Inc. | Enhanced fuse configurations for low-voltage flash memories |
JP4667594B2 (ja) * | 2000-12-25 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
JP3875570B2 (ja) * | 2001-02-20 | 2007-01-31 | 株式会社東芝 | 半導体記憶装置のデータ書き込み方法及び半導体記憶装置 |
KR100439045B1 (ko) * | 2001-06-29 | 2004-07-05 | 주식회사 하이닉스반도체 | 워드 라인 전압 클램핑 회로 |
KR100390957B1 (ko) * | 2001-06-29 | 2003-07-12 | 주식회사 하이닉스반도체 | 플래쉬 메모리 장치 |
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1995
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1999
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2001
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2002
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