DE69426818T2 - Fehlertolerantes Speichergerät, insbesondere des Typs "flash EEPROM" - Google Patents

Fehlertolerantes Speichergerät, insbesondere des Typs "flash EEPROM"

Info

Publication number
DE69426818T2
DE69426818T2 DE69426818T DE69426818T DE69426818T2 DE 69426818 T2 DE69426818 T2 DE 69426818T2 DE 69426818 T DE69426818 T DE 69426818T DE 69426818 T DE69426818 T DE 69426818T DE 69426818 T2 DE69426818 T2 DE 69426818T2
Authority
DE
Germany
Prior art keywords
fault
storage device
type
flash eeprom
tolerant storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69426818T
Other languages
English (en)
Other versions
DE69426818D1 (de
Inventor
Giovanni Campardo
Emilio Camerlenghi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69426818D1 publication Critical patent/DE69426818D1/de
Publication of DE69426818T2 publication Critical patent/DE69426818T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current
DE69426818T 1994-06-10 1994-06-10 Fehlertolerantes Speichergerät, insbesondere des Typs "flash EEPROM" Expired - Fee Related DE69426818T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830283A EP0686979B1 (de) 1994-06-10 1994-06-10 Fehlertolerantes Speichergerät, insbesondere des Typs "flash EEPROM"

Publications (2)

Publication Number Publication Date
DE69426818D1 DE69426818D1 (de) 2001-04-12
DE69426818T2 true DE69426818T2 (de) 2001-10-18

Family

ID=8218466

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69426818T Expired - Fee Related DE69426818T2 (de) 1994-06-10 1994-06-10 Fehlertolerantes Speichergerät, insbesondere des Typs "flash EEPROM"

Country Status (4)

Country Link
US (1) US5682349A (de)
EP (1) EP0686979B1 (de)
JP (1) JP3725581B2 (de)
DE (1) DE69426818T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9614551D0 (en) 1996-07-11 1996-09-04 Memory Corp Plc Memory system
US6532556B1 (en) 2000-01-27 2003-03-11 Multi Level Memory Technology Data management for multi-bit-per-cell memories
US6314023B1 (en) * 2000-06-15 2001-11-06 Motorola, Inc. Non-volatile programming elements for redundancy and identification in an integrated circuit
US6466476B1 (en) 2001-01-18 2002-10-15 Multi Level Memory Technology Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell
EP1357559B1 (de) * 2002-04-26 2006-06-14 STMicroelectronics S.r.l. Selbstreparatur-Methode für nicht flüchtige Speicher mit einer Architektur zur Fehlervermeidung sowie nicht flüchtiger Speicher
EP1365419B1 (de) 2002-05-21 2008-12-31 STMicroelectronics S.r.l. Selbstreparaturverfahren für nichtflüchtige Speicheranordnung mit Lösch-/Programmierfehlerdetektion, und nichtflüchtige Speicheranordnung dafür
US6839275B2 (en) * 2003-06-04 2005-01-04 Hewlett-Packard Development Company, L.P. Memory system having control circuit configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells
US7046555B2 (en) * 2003-09-17 2006-05-16 Sandisk Corporation Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
US7177189B2 (en) * 2004-03-01 2007-02-13 Intel Corporation Memory defect detection and self-repair technique
JP2006294144A (ja) * 2005-04-12 2006-10-26 Toshiba Corp 不揮発性半導体記憶装置
EP1947539A4 (de) * 2005-09-27 2011-05-18 Advantest Corp Steuerverfahren und steuersystem
US7545679B1 (en) * 2007-12-28 2009-06-09 Freescale Semiconductor, Inc. Electrical erasable programmable memory transconductance testing

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0198935A1 (de) * 1985-04-23 1986-10-29 Deutsche ITT Industries GmbH Elektrisch umprogrammierbarer Halbleiterspeicher mit Redundanz
JPS62114200A (ja) * 1985-11-13 1987-05-25 Mitsubishi Electric Corp 半導体メモリ装置
EP0403822B1 (de) * 1989-06-19 1994-10-12 Texas Instruments Incorporated Schaltung und Verfahren zur Vorbereitung gelöschter EEPROMS vor der Programmierung
US5233559A (en) * 1991-02-11 1993-08-03 Intel Corporation Row redundancy for flash memories
KR960002006B1 (ko) * 1991-03-12 1996-02-09 가부시끼가이샤 도시바 2개의 기준 레벨을 사용하는 기록 검증 제어기를 갖는 전기적으로 소거 가능하고 프로그램 가능한 불휘발성 메모리 장치
JP3080743B2 (ja) * 1991-12-27 2000-08-28 日本電気株式会社 不揮発性半導体記憶装置
KR960002777B1 (ko) * 1992-07-13 1996-02-26 삼성전자주식회사 반도체 메모리 장치의 로우 리던던시 장치
FR2694404B1 (fr) * 1992-07-31 1994-09-09 Sgs Thomson Microelectronics Procédé de mesure des tensions de seuil des cellules d'une mémoire intégrée.
US5428621A (en) * 1992-09-21 1995-06-27 Sundisk Corporation Latent defect handling in EEPROM devices
US5452251A (en) * 1992-12-03 1995-09-19 Fujitsu Limited Semiconductor memory device for selecting and deselecting blocks of word lines
JP3212421B2 (ja) * 1993-09-20 2001-09-25 富士通株式会社 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
JP3725581B2 (ja) 2005-12-14
US5682349A (en) 1997-10-28
EP0686979B1 (de) 2001-03-07
DE69426818D1 (de) 2001-04-12
JPH0883500A (ja) 1996-03-26
EP0686979A1 (de) 1995-12-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee