WO2022007268A1 - 线路板及其制作方法 - Google Patents

线路板及其制作方法 Download PDF

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Publication number
WO2022007268A1
WO2022007268A1 PCT/CN2020/127009 CN2020127009W WO2022007268A1 WO 2022007268 A1 WO2022007268 A1 WO 2022007268A1 CN 2020127009 W CN2020127009 W CN 2020127009W WO 2022007268 A1 WO2022007268 A1 WO 2022007268A1
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WIPO (PCT)
Prior art keywords
chip
layer
connection terminal
power signal
signal layer
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PCT/CN2020/127009
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English (en)
French (fr)
Inventor
黄立湘
王泽东
缪桦
Original Assignee
深南电路股份有限公司
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Application filed by 深南电路股份有限公司 filed Critical 深南电路股份有限公司
Priority to EP20825133.0A priority Critical patent/EP4181636A4/en
Priority to US17/134,488 priority patent/US11317503B2/en
Publication of WO2022007268A1 publication Critical patent/WO2022007268A1/zh

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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/08—Magnetic details
    • H05K2201/083—Magnetic materials
    • H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present application relates to the technical field of chip embedding, and in particular, to a circuit board and a manufacturing method thereof.
  • Today's electronic packaging not only needs to provide chip protection, but also needs to meet the increasing performance, reliability, heat dissipation, power distribution and other requirements at a certain cost.
  • the existing circuit boards are not highly integrated in the manufacturing process, and the power consumption and cost are relatively high.
  • the present application mainly provides a circuit board and a manufacturing method thereof, so as to realize the thinning and miniaturization of the circuit board.
  • a technical solution provided by the present application is to provide a circuit board, comprising: a core board, and a groove body is formed, and the groove body includes a plurality of first sub-groove bodies and a plurality of A second sub-slot body below the sub-slot body and corresponding to the position of the first sub-slot body; a chip assembly disposed in the slot body; the chip assembly including a plurality of chips located in the first sub-slot body The first chip and a plurality of second chips located in the second sub-slot body; wherein, each of the first chips and the second chips corresponding to their positions are connected in series to form a plurality of chip groups; the plurality of The chip sets are connected in parallel with each other, and one end of the plurality of chip sets is connected to the first power signal layer, and the other end is connected to the ground wire layer.
  • the circuit board further includes: a first circuit layer, disposed on one side of the core board; a second circuit layer, disposed on a side of the core board away from the first circuit layer; a first insulating layer , arranged between the core board and the first circuit layer; a second insulating layer, arranged between the core board and the second circuit layer; wherein, the first circuit layer includes the first circuit layer a power signal layer and a control signal layer; the second circuit layer includes the ground layer and the second power signal layer.
  • the circuit board further includes: a first power signal layer, arranged on one side of the core board; a second power signal layer, arranged on a side of the core board away from the first power signal layer; an insulating layer, disposed between the core board and the first power signal layer; a second insulating layer, disposed between the core board and the second power signal layer; located between the first power signal layer
  • the control signal layer on the side of the layer far away from the core board; the ground wire layer on the side of the second power signal layer away from the core board; the ground layer on the side of the first power signal layer and the control signal layer a third insulating layer between the second power signal layer and the ground layer; and a fourth insulating layer between the second power signal layer and the ground layer.
  • each of the first chip and the second chip includes: a second connection terminal and a third connection terminal close to one side of the first circuit layer, and a first connection close to the second circuit layer terminal; wherein, the first connection terminal of the first chip is coupled to the second connection terminal of the second chip corresponding to its position; the second connection terminal of the first chip is coupled to the first power supply signal layer, the third connection terminal of the first chip is coupled to the control signal layer, the third connection terminal of the second chip is coupled to the control signal layer, and the first connection terminal of the second chip is connected to the control signal layer the ground layer.
  • the second insulating layer has a first conductive hole at a position corresponding to the first connection terminal of the first chip, so as to connect the second power signal layer with the first connection terminal of the first chip;
  • the first insulating layer has a second conductive hole at a position corresponding to the second connection terminal of the second chip, so as to connect the first power signal layer with the second connection terminal of the second chip;
  • the first insulating layer has a fourth conductive hole at the position corresponding to the third connection terminal of the first chip and the second chip, so as to connect the third connection terminal of the first chip and the second chip with a fourth conductive hole.
  • the connection terminal is connected to the control signal layer; or the first insulating layer and the third insulating layer have fourth conductive holes at positions corresponding to the third connection terminals of the first chip and the second chip, The third connection terminals of the first chip and the second chip are connected to the control signal layer.
  • the first insulating layer has a fifth conductive hole at a position corresponding to the second connection terminal of the first chip, so as to connect the second connection terminal of the first chip with the first power supply
  • the signal layer is connected
  • the second insulating layer has a sixth conductive hole at the position corresponding to the first connection terminal of the second chip, so as to connect the first connection terminal of the second chip with the ground
  • the wire layer is electrically connected
  • the first insulating layer has a fifth conductive hole at the position corresponding to the second connection terminal of the first chip, so as to connect the second connection terminal of each of the first chips to the second connection terminal of the first chip the first power signal layer is connected
  • the second insulating layer and the fourth insulating layer have sixth conductive holes at the positions corresponding to the first connection terminals of the second chip to connect each of the first The second connection terminals of the two chips are electrically connected to the ground layer.
  • another technical solution provided by the present application is to provide a method for manufacturing a circuit board, including: providing a core board; and opening a groove body on the core board, and the groove body includes a plurality of first a sub-slot body and a plurality of second sub-slot bodies located under the first sub-slot body and corresponding to the positions of the first sub-slot body; a chip assembly is placed in the slot body, and the chip assembly includes a plurality of A first chip located in the first sub-slot body and a plurality of second chips located in the second sub-slot body, wherein each of the first chips and the second chips corresponding to their positions are formed in series A plurality of chip groups; the plurality of chip groups are connected in parallel with each other, and one end of the plurality of chip groups is connected to the first power signal layer, and the other end is connected to the ground wire layer.
  • the chip assembly is placed in the groove body, and the chip assembly includes a plurality of first chips located in the first sub-groove body and a plurality of second chips located in the second sub-groove body wherein, each of the first chips and the second chips corresponding to their positions are connected in series to form a plurality of chip groups; the plurality of chip groups are connected in parallel with each other, and one end of the plurality of chip groups is connected to the first power signal layer,
  • the step of connecting the other end to the ground wire layer includes: arranging a first circuit board on one side of the core board, and arranging a second circuit layer on a side of the core board away from the first circuit layer; wherein, the The first circuit layer includes a first power signal layer and a control signal layer, the second circuit layer includes a ground layer and a second power signal layer; a first circuit layer is arranged between the core board and the first circuit layer an insulating layer, and a second insulating layer is arranged between the core board and the second circuit layer; or a
  • a second power signal layer is arranged on one side of a power signal layer; a first insulating layer is arranged between the core board and the first power signal layer, and a first insulating layer is arranged between the core board and the second power signal layer A second insulating layer is arranged between; a control signal layer is arranged on the side of the first power signal layer away from the core board, and a ground wire layer is arranged on the side of the second power signal layer away from the core board; A third insulating layer is provided between the first power signal layer and the control signal layer, and a fourth insulating layer is provided between the second power signal layer and the ground layer.
  • the method further includes: arranging a first conductive hole at a position of the second insulating layer corresponding to the first connection terminal of the first chip; A second conductive hole is provided at the position of the two connection terminals, and a third conductive hole is provided between the first chip and the second chip, penetrating the core board, the first insulating layer and the second insulating layer a conductive hole to connect the first connection terminal of the first chip with the second connection terminal of the second chip; provided at the position of the first insulating layer corresponding to the second connection terminal of the first chip a fifth conductive hole to connect the second connection terminal of the first chip with the first power signal layer; at the position of the second insulating layer corresponding to the first connection terminal of the second chip A sixth conductive hole is provided to connect the first connection terminal of the second chip with the ground wire layer; the first insulating layer corresponds to the first chip and the third chip of the second chip A fourth conductive hole is provided at the position of the connection terminal, so as to connect the third connection terminal of the first
  • the circuit board provided by the present application includes a core board, and a groove body is formed on the core plate. and a second sub-slot body corresponding to the position of the first sub-slot body; the chip assembly is arranged in the slot body; the chip assembly includes a plurality of first chips located in the first sub-slot body and a plurality of first chips located in the second sub-slot body The second chip; wherein, each first chip and its corresponding second chip are connected in series to form a plurality of chip groups; the plurality of chip groups are connected in parallel with each other, and one end of the plurality of chip groups is connected to the first power signal layer, and the other end is connected to the ground line layer.
  • the chip is embedded in the circuit board and combined with the circuit board, so as to realize the thinning and miniaturization of the circuit board.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a circuit board of the present application.
  • Fig. 2 is the structural schematic diagram of the groove body of the circuit board of the present application.
  • FIG. 3 is a schematic structural diagram of a second embodiment of the circuit board of the present application.
  • FIG. 4 is a schematic flowchart of the first embodiment of the manufacturing method of the circuit board of the present application.
  • FIG. 5 is a schematic flowchart of a second embodiment of the method for manufacturing a circuit board of the present application.
  • FIG. 6 is a schematic flowchart of a third embodiment of a method for manufacturing a circuit board of the present application.
  • FIG. 7 is a schematic flow chart of a fourth embodiment of the manufacturing method of the circuit board of the present application.
  • FIG. 1 is a schematic structural diagram of a circuit board according to a first embodiment of the present application. It includes: a core board 11 and a chip assembly 12 ; a groove body is formed on the core board 11 , please refer to FIG. Sub-tank body 112 .
  • the first sub-slot body 111 and the second sub-slot body 112 are arranged in an array, and the second sub-slot body 112 is located below the first sub-slot body 111 and is one-to-one with the first sub-slot body 111 correspond.
  • the chip assembly 12 includes a first chip 121 located in the first sub-slot body 111 and a second chip 122 located in the second sub-slot body 112 . This embodiment is described by taking three first chips 121 and three second chips 122 as an example.
  • the schematic structural diagram shown in FIG. 1 is a side view of the circuit board.
  • one first chip 121 is correspondingly placed in one first sub-slot body 111
  • one second chip 122 is placed in one second sub-slot body 113 correspondingly.
  • multiple chips may also be placed in one slot, and in this embodiment, one slot is used to place one chip as an example for description.
  • the circuit board shown in FIG. 1 further includes a first circuit layer 15 and a second circuit layer 14.
  • the first circuit layer 15 and the second circuit layer 14 are respectively disposed on both sides of the core board 11, and pass through the first insulating layer 17 and the second circuit layer 14 respectively.
  • the second insulating layer 16 is connected to the core board 11 .
  • the first insulating layer 17 is provided between the core board 11 and the first circuit layer 15 for connecting the core board 11 and the first circuit layer 15 ;
  • the second insulating layer 16 is provided between the core board 11 and the second circuit layer 15 .
  • Between the layers 14 it is used to connect the core board 11 and the second circuit layer 14 .
  • the material of the core board 11 is a copper clad laminate
  • the copper clad laminate is a basic material for making a circuit board, including a base material board and a copper foil covering the base material.
  • the base material board is made of paper substrate, glass fiber Fabric substrates, synthetic fiber fabric substrates, non-woven substrates, composite substrates and other materials are impregnated with resin to form a bonding sheet, which is made of a combination of multiple bonding sheets, and is coated on one or both sides of the prepared substrate board.
  • the copper foil is then cured by hot pressing to form a copper clad laminate.
  • the first insulating layer 17 and the second insulating layer 16 are prepregs, which are used as interlayer bonding layers during lamination.
  • the prepregs are mainly composed of resin and reinforcing materials.
  • Glass fiber cloth is used as a reinforcing material, impregnated with resin glue, and then pre-baked into thin sheets by heat treatment. It will soften under heating and pressure, solidify after cooling, and has viscosity. Adjacent layers are glued together.
  • the first chip 121 located in the first sub-slot body 111 and the second chip 122 located in the second sub-slot body 112 are connected in series with each other to form multiple chip sets, and the multiple chip sets are connected in parallel , that is, one end of the plurality of chipsets is connected to the first power signal layer, and the other end is connected to the ground layer.
  • the first chip 121 and the second chip 122 each include a first connection terminal, a second connection terminal and a third connection terminal.
  • the second connection terminal and the third connection terminal are located on the side close to the first circuit layer
  • the first connection terminal is located on the side close to the second circuit layer.
  • the first circuit layer 15 in the circuit board in this embodiment includes a first power signal layer 151 and a control signal layer 152 that are not connected to each other; the second circuit layer 14 includes a second power source that is not connected to each other Signal layer 141 and ground layer 142 .
  • the second insulating layer A first conductive hole 181 is provided at a position corresponding to the first connection terminal of the first chip 121 to connect the second power signal layer 141 with the first connection terminal of the first chip 121 .
  • the first insulating layer 17 has a second conductive hole 182 at a position corresponding to the second connection terminal of the second chip 122 to connect the first power signal layer 151 to the second connection terminal of the second chip 122 .
  • first insulating layer 17 and the second insulating layer 16 to connect the first power signal layer 151 and the second power signal layer 141 connection, and then connect the first connection terminal of the first chip 121 to the second connection terminal of the second chip 122 to connect the first chip 121 and the second chip 122 in series.
  • the second connection terminals of each of the first chips 121 are connected to each other, and the first connection terminals of each of the second chips 122 are connected to each other.
  • the first insulating layer 17 has fifth conductive holes 185 at positions corresponding to the second connection terminals of the first chip 121 to connect each first chip 121 to each other.
  • the second connection terminal of a chip 121 is connected to the first power signal layer 151 ; the second connection terminal of the first chip 121 is connected in parallel through the first power signal layer 151 .
  • the second insulating layer 16 has sixth conductive holes 186 at positions corresponding to the first connection terminals of the second chips 122 to connect each second chip 122 to each other.
  • the first connection terminal of the second chip 122 is connected to the ground wire layer 142 ; the first connection terminal of the second chip 122 is connected in parallel through the ground wire layer 142 .
  • the first insulating layer 17 has fourth conductive holes 184 at positions corresponding to the third connection terminals of the first chip 121 and the second chip 122, and the fourth conductive holes 184 are used to connect the first chip 121 and the third connection terminals of the second chip 122 are connected to the control signal layer 152 .
  • a plurality of first chips 121 and second chips 122 are embedded in the circuit board, and the first chips 121 and the corresponding second chips 122 are connected in series to form a chip set, so that the chip set is connected in series.
  • the embedded circuit board can be made thinner and smaller, and the purpose of short signal transmission distance and reduced signal loss can be achieved.
  • FIG. 3 is a schematic structural diagram of a second embodiment of the circuit board of the present application. It includes: a core board 21 and a chip assembly 22 ; the core board 21 is provided with a slot body, please refer to FIG. 2 , the slot body includes a plurality of first sub-slot bodies 111 arranged in rows, and a plurality of a second sub-tank 112 .
  • the chip assembly 22 includes a first chip 221 located in the first sub-slot body 111 and a second chip 222 located in the second sub-slot body 112 . This embodiment is described by taking three first chips 221 and three second chips 222 as an example.
  • the schematic structural diagram of the circuit board shown in FIG. 3 is a side view of the circuit board.
  • the circuit board shown in FIG. 3 further includes a first power signal layer 251 and a second power signal layer 241.
  • the first power signal layer 251 and the second power signal layer 241 are respectively disposed on both sides of the core board 21, and pass through the first power signal layer 251 and the second power signal layer 241 respectively.
  • the insulating layer 271 and the second insulating layer 261 are connected to the core board 21 .
  • the first insulating layer 271 is disposed between the core board 21 and the first power signal layer 251 for connecting the core board 21 and the first power signal layer 251;
  • the second insulating layer 261 is disposed between the core board 21 and the first power signal layer 251; Between the two power signal layers 241 is used to connect the core board 21 with the second power signal layer 241 .
  • the circuit board shown in this embodiment further includes a third insulating layer 272 , a fourth insulating layer 262 , a control signal layer 252 and a ground wire layer 242 .
  • the control signal layer 252 is located on the side of the first power signal layer 251 away from the core board 21
  • the ground layer 242 is located on the side of the second power signal layer 241 away from the core board 21 .
  • the third insulating layer 272 is located between the first power signal layer 251 and the control signal layer 252 for bonding the first power signal layer 251 and the control signal layer 252.
  • the fourth insulating layer 262 is located between the second power signal layer 241 and the control signal layer 252. Between the ground wire layers 242 , the second power signal layer 241 and the ground wire layer 242 are bonded together.
  • the first chip 221 and the second chip 222 each include a first connection terminal, a second connection terminal and a third connection terminal.
  • the first connection terminal of the first chip 221 is connected to the second connection terminal of the second chip 222 corresponding to its position.
  • each chip set is connected in parallel with each other, one end of the chip set is connected to the first power signal layer 251 , and the other end is connected to the ground wire layer 242 .
  • the second connection terminal of the first chip 221 is connected to the first power signal layer 251
  • the first connection terminal of the second chip 222 is connected to the ground wire layer 242 .
  • the second insulating layer 261 has a first conductive hole 281 at a position corresponding to the first connection terminal of the first chip 221 to connect the second power signal layer 241 to the first connection terminal of the first chip 221 .
  • the first insulating layer 271 has a second conductive hole 282 at a position corresponding to the second connection terminal of the second chip 222 to connect the first power signal layer 251 to the second connection terminal of the second chip 222 .
  • a third conductive hole 183 is formed between the first chip 221 and the second chip 222 through the core board 21 , the first insulating layer 271 and the second insulating layer 261 to connect the first power signal layer 251 and the second power signal layer 241 and then connect the first connection terminal of the first chip 221 and the second connection terminal of the second chip 222 to connect the first chip 221 and the second chip 222 in series.
  • the second connection terminals of each first chip 221 are connected to each other and to the first power signal layer 251 , and the first connection terminals of each second chip 222 are connected to each other.
  • the terminals are connected to each other and to the ground plane 242 .
  • the first insulating layer 271 has a fifth conductive hole 285 at the position corresponding to the second connection terminal of the first chip 221 to connect each first chip 221 to each other.
  • the second connection terminal of a chip 221 is connected to the first power signal layer 251 ; the second connection terminal of the first chip 221 is connected in parallel through the first power signal layer 251 .
  • the first connection terminals of each of the second chips 222 are connected to each other.
  • the second insulating layer 261 has sixth conductive holes 286 at positions corresponding to the first connection terminals of the second chip 222 to connect each second chip 222 to each other.
  • the first connection terminals of the two chips 222 are connected to the ground wire layer 242 ; the first connection terminals of the second chip 222 are connected in parallel through the ground wire layer 242 .
  • the positions of the first insulating layer 271 and the third insulating layer 272 corresponding to the third connection terminals of the first chip 221 and the second chip 222 have fourth conductive holes 284 , and the fourth conductive holes 284
  • the third connection terminals of the first chip 221 and the second chip 222 are used to connect the control signal layer 252 .
  • a plurality of first chips 221 and second chips 222 are embedded in the circuit board, and the first chips 221 and the corresponding second chips 222 are connected in series to form a chip set.
  • the groups are connected in parallel with each other, so as to realize the thinning and miniaturization of the embedded circuit board, and can achieve the purpose of short signal transmission distance and reducing signal loss.
  • FIG. 4 is a schematic flowchart of the first embodiment of the manufacturing method of the circuit board of the present application. Including: Step S41 : providing a core board.
  • the material of the core board is a copper clad laminate
  • the copper clad laminate is a basic material for making circuit boards, including a base material board and a copper foil covering the base material
  • the base material board is made of paper substrate, glass fiber cloth Substrates, synthetic fiber cloth substrates, non-woven substrates, composite substrates and other materials are impregnated with resin to form a bonding sheet, which is made by combining multiple bonding sheets, and is covered on one or both sides of the prepared base material.
  • the copper foil is then cured by hot pressing to form a copper clad laminate.
  • Step S42 opening a groove body on the core board, the groove body includes a plurality of first sub-groove bodies and a plurality of first sub-groove bodies located under the first sub-groove body and corresponding to the positions of the first sub-groove bodies. Two sub-tank.
  • the slot body includes a first sub-slot body and a second sub-slot body located below the first sub-slot body, and the first sub-slot body and the second sub-slot body The positions of the grooves correspond one-to-one.
  • Step S43 placing a chip assembly in the groove body, the chip assembly includes a plurality of first chips located in the first sub-groove body and a plurality of second chips located in the second sub-groove body, Wherein, each of the first chip and the second chip corresponding to its position are connected in series to form a plurality of chip groups; the plurality of chip groups are connected in parallel with each other, and one end of the plurality of chip groups is connected to the first power signal layer, and the other One end is connected to the ground plane.
  • a chip assembly is arranged in the groove body, wherein the chip assembly includes a first chip and a second chip, the first chip is placed in the first sub-groove body, and the second chip is placed in the second sub-groove body.
  • the first chip and the corresponding second chip are connected in series to form a chip set, and multiple chip sets are connected in parallel with each other, that is, one end of the multiple chip sets is connected to the first power signal layer, and the other end is connected to the ground wire layer.
  • FIG. 5 is a schematic flowchart of the second embodiment of the manufacturing method of the circuit board of the present application. Compared with the first embodiment shown in FIG. 4 above, the difference is that after step S43, it further includes:
  • Step S51 a first circuit board is arranged on one side of the core board, and a second circuit layer is arranged on a side of the core board away from the first circuit layer; wherein the first circuit layer includes a first power signal layer and a control signal layer, The second circuit layer includes a ground layer and a second power signal layer.
  • a first circuit layer and a second circuit layer are arranged on both sides of the core board. Specifically, both the first circuit layer and the second circuit layer are circuit networks fabricated on the copper layer.
  • the first power signal layer and the control signal layer are respectively different circuit networks on the first circuit layer, and the ground layer and the second power signal layer are respectively different circuit networks on the second circuit layer.
  • Step S52 Disposing a first insulating layer between the core board and the first circuit layer, and disposing a second insulating layer between the core board and the second circuit layer.
  • a first insulating layer is arranged between the core board and the first circuit layer to bond the core board and the first circuit layer.
  • a second insulating layer is arranged between the core board and the second circuit layer to bond the core board and the second circuit layer.
  • the first insulating layer and the second insulating layer are prepregs, which are used as interlayer bonding layers during lamination.
  • the prepregs are mainly composed of resins and reinforcing materials.
  • Glass fiber cloth is used as reinforcing material, which is impregnated with resin glue, and then pre-baked into thin sheets by heat treatment. It will soften under heating and pressure, solidify after cooling, and has viscosity. Glue the two adjacent layers together.
  • FIG. 6 is a schematic flowchart of the third embodiment of the manufacturing method of the circuit board of the present application. Compared with the first embodiment shown in FIG. 4 , the difference is that after step S43, it further includes:
  • Step S61 Disposing a first power signal layer on one side of the core board, and disposing a second power signal layer on a side of the core board away from the first power signal layer.
  • the first power signal layer and the second power signal layer are located on both sides of the core board, and the first power signal layer and the second power signal layer are circuit layers made of copper layers.
  • Step S62 Disposing a first insulating layer between the core board and the first power signal layer, and disposing a second insulating layer between the core board and the second power signal layer.
  • first insulating layer and the second insulating layer are prepregs, which are not repeated here.
  • Step S63 Disposing a control signal layer on the side of the first power signal layer away from the core board, and disposing a ground wire layer on the side of the second power signal layer away from the core board.
  • control signal layer and the ground layer are also circuit layers made of copper layers. Specifically, the control signal layer is located outside the first power signal layer, and the ground layer is located outside the second power signal layer.
  • Step S64 Disposing a third insulating layer between the first power signal layer and the control signal layer, and disposing a fourth insulating layer between the second power signal layer and the ground layer.
  • the fourth insulating layer and the third insulating layer are the same as the first insulating layer and the second insulating layer, both of which are prepregs, and will not be repeated here.
  • FIG. 7 is a schematic flowchart of the fourth embodiment of the manufacturing method of the circuit board of the present application.
  • the second embodiment shown in FIG. 5 and the third embodiment shown in FIG. include:
  • Step S71 Disposing a first conductive hole at the position of the second insulating layer corresponding to the first connection terminal of the first chip, and at the position of the first insulating layer corresponding to the second connection terminal of the second chip A second conductive hole is arranged at the place, and a third conductive hole is arranged between the first chip and the second chip through the core board, the first insulating layer and the second insulating layer, so as to connect the The first connection terminal of the first chip is connected to the second connection terminal of the second chip.
  • Step S72 Disposing a fifth conductive hole at a position of the first insulating layer corresponding to the second connection terminal of the first chip, so as to connect the second connection terminal of the first chip with the first power supply connecting the signal layer; and disposing a sixth conductive hole at the position of the second insulating layer corresponding to the first connection terminal of the second chip, so as to connect the first connection terminal of the second chip to the ground Line layer connection.
  • the fifth conductive hole connects the second connection terminal of the first chip with the first power supply signal layer, and the sixth conductive hole connects the first connection terminal of the second chip with the ground layer, so as to connect the chip sets in parallel with each other.
  • Step S73 Disposing a fourth conductive hole at the position of the first insulating layer corresponding to the third connection terminal of the first chip and the second chip, so as to connect the first chip and the second chip.
  • the third connection terminal is connected to the control signal layer.
  • the fourth conductive hole connects the third connection terminals of the first chip and the second chip to the control signal layer.
  • the circuit board by arranging and burying a plurality of chip arrays in the circuit board, the circuit board can be made light, thin and miniaturized.
  • multiple chips are regularly connected in series and parallel on the circuit board, so that the signal transmission distance is short and the signal loss is reduced.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

本申请提供一种线路板及其制作方法，包括：芯板，开设有槽体，槽体包括多个第一子槽体及多个位于第一子槽体下方且与第一子槽体位置对应的第二子槽体；芯片组件，设置于槽体中；芯片组件包括多个位于第一子槽体中的第一芯片及多个位于第二子槽体中的第二芯片；其中，每一第一芯片与其位置对应的第二芯片串联形成多个芯片组；多个芯片组相互并联，且多个芯片组一端连接第一电源信号层，另一端连接地线层。以此将多个芯片埋入在线路板中，以实现线路板的轻薄化及小型化。

Description

线路板及其制作方法 【技术领域】
本申请涉及芯片埋入技术领域，特别是涉及一种线路板及其制作方法。
【背景技术】
随着电路板制备工艺的越来越完善，电子封装技术也越来越成熟。
今日的电子封装不但要提供芯片的保护，同时还要在一定的成本下满足不断增加的性能、可靠性、散热、功率分配等要求，同时由于用户对超薄，微缩，多功能的需求，而现有的电路板在制作工艺中集成度不高，且功耗和成本相对较高。
因此，提供一种集成度高、功耗低且成本低的线路板尤为必要。
【发明内容】
本申请主要提供一种线路板及其制作方法，以实现线路板的轻薄化及小型化。
为解决上述技术问题，本申请提供的一个技术方案是：提供一种线路板，包括：芯板，开设有槽体，所述槽体包括多个第一子槽体及多个位于所述第一子槽体下方且与所述第一子槽体位置对应的第二子槽体；芯片组件，设置于所述槽体中；所述芯片组件包括多个位于所述第一子槽体中的第一芯片及多个位于所述第二子槽体中的第二芯片；其中，每一所述第一芯片与其位置对应的所述第二芯片串联形成多个芯片组；所述多个芯片组相互并联，且所述多个芯片组一端连接第一电源信号层，另一端连接地线层。
其中，所述线路板还包括：第一线路层，设置在所述芯板的一侧；第二线路层，设置在所述芯板远离所述第一线路层的一侧；第一绝缘层，设置在所述芯板与所述第一线路层之间；第二绝缘层，设置在所述芯板与所述第二线路层之间；其中，所述第一线路层包括所述第一电源信号 层及控制信号层；所述第二线路层包括所述地线层及第二电源信号层。
其中，所述线路板还包括：第一电源信号层，设置在所述芯板的一侧；第二电源信号层，设置在所述芯板远离所述第一电源信号层的一侧；第一绝缘层，设置在所述芯板与所述第一电源信号层之间；第二绝缘层，设置在所述芯板与所述第二电源信号层之间；位于所述第一电源信号层远离所述芯板的一侧的控制信号层；位于所述第二电源信号层远离所述芯板的一侧的地线层；位于所述第一电源信号层及所述控制信号层之间的第三绝缘层；位于所述第二电源信号层及所述地线层之间的第四绝缘层。
其中，每个所述第一芯片及所述第二芯片均包括：靠近所述第一线路层一侧的第二连接端子及第三连接端子，及靠近所述第二线路层的第一连接端子；其中，所述第一芯片的所述第一连接端子耦接与其位置对应的第二芯片的所述第二连接端子；所述第一芯片的第二连接端子耦接所述第一电源信号层，所述第一芯片的第三连接端子耦接所述控制信号层，所述第二芯片的第三连接端子耦接所述控制信号层，所述第二芯片的第一连接端子连接所述地线层。
其中，所述第二绝缘层对应所述第一芯片的第一连接端子的位置处具有第一导电孔，以将所述第二电源信号层与所述第一芯片的第一连接端子连接；所述第一绝缘层对应所述第二芯片的第二连接端子的位置处具有第二导电孔，以将所述第一电源信号层与所述第二芯片的第二连接端子连接；所述第一芯片及所述第二芯片之间具有第三导电孔，以将所述第一电源信号层及所述第二电源信号层连接，进而将所述第一芯片的所述第一连接端子与所述第二芯片的所述第二连接端子连接，以将所述第一芯片及所述第二芯片串联形成多个芯片组。
其中，所述第一绝缘层对应所述第一芯片及所述第二芯片的第三连接端子的位置处具有第四导电孔，以将所述第一芯片及所述第二芯片的第三连接端子与所述控制信号层连接；或所述第一绝缘层及所述第三绝缘层对应所述第一芯片及所述第二芯片的第三连接端子的位置处具有第四导电孔，以将所述第一芯片及所述第二芯片的第三连接端子与所述 控制信号层连接。
其中，所述第一绝缘层对应所述第一芯片的所述第二连接端子的位置处具有第五导电孔，以将所述第一芯片的所述第二连接端子与所述第一电源信号层连接；所述第二绝缘层对应所述第二芯片的所述第一连接端子的位置处具有第六导电孔，以将所述第二芯片的所述第一连接端子与所述地线层电连接；或所述第一绝缘层对应所述第一芯片的所述第二连接端子的位置处具有第五导电孔，以将每一所述第一芯片的第二连接端子与所述第一电源信号层连接；所述第二绝缘层及所述第四绝缘层对应所述第二芯片的所述第一连接端子的位置处具有第六导电孔，以将每一所述第二芯片的所述第二连接端子与所述地线层电连接。
为解决上述即使问题，本申请提供的另一个技术方案为：提供一种线路板的制作方法，包括：提供芯板；在所述芯板上开设槽体，所述槽体包括多个第一子槽体及多个位于所述第一子槽体下方且与所述第一子槽体位置对应的第二子槽体；在所述槽体中放置芯片组件，所述芯片组件包括多个位于所述第一子槽体中的第一芯片及多个位于所述第二子槽体中的第二芯片，其中，每一所述第一芯片与其位置对应的所述第二芯片串联形成多个芯片组；所述多个芯片组相互并联，且所述多个芯片组一端连接第一电源信号层，另一端连接地线层。
其中，所述在所述槽体中放置芯片组件，所述芯片组件包括多个位于所述第一子槽体中的第一芯片及多个位于所述第二子槽体中的第二芯片；其中，每一所述第一芯片与其位置对应的所述第二芯片串联形成多个芯片组；所述多个芯片组相互并联，且所述多个芯片组一端连接第一电源信号层，另一端连接地线层的步骤之后包括：在所述芯板的一侧设置第一线路板，及在所述芯板远离所述第一线路层的一侧设置第二线路层；其中，所述第一线路层包括第一电源信号层及控制信号层，所述第二线路层包括地线层及第二电源信号层；在所述芯板及所述第一线路层之间设置第一绝缘层，及在所述芯板及所述第二线路层之间设置第二绝缘层；或在所述芯板的一侧设置第一电源信号层，及在所述芯板远离所述第一电源信号层的一侧设置第二电源信号层；在所述芯板及所述第 一电源信号层之间设置第一绝缘层，及在所述芯板及所述第二电源信号层之间设置第二绝缘层；在所述第一电源信号层远离所述芯板的一侧设置控制信号层，及在所述第二电源信号层远离所述芯板的一侧设置地线层；在所述第一电源信号层及所述控制信号层之间设置第三绝缘层，及在所述第二电源信号层及所述地线层之间设置第四绝缘层。
其中，所述方法还包括：在所述第二绝缘层对应所述第一芯片的第一连接端子的位置处设置第一导电孔，在所述第一绝缘层对应所述第二芯片的第二连接端子的位置处设置第二导电孔，及在所述第一芯片及所述第二芯片之间设置贯穿所述芯板、所述第一绝缘层及所述第二绝缘层的第三导电孔，以将所述第一芯片的第一连接端子与所述第二芯片的第二连接端子连接；在所述第一绝缘层对应所述第一芯片的第二连接端子的位置处设置第五导电孔，以将所述第一芯片的所述第二连接端子与所述第一电源信号层连接；在所述第二绝缘层对应所述第二芯片的第一连接端子的位置处设置第六导电孔，以将所述第二芯片的所述第一连接端子与所述地线层连接；在所述第一绝缘层对应所述第一芯片及所述第二芯片的第三连接端子的位置处设置第四导电孔，以将所述第一芯片及所述第二芯片的第三连接端子与所述控制信号层连接。
本申请的有益效果，区别与现有技术，本申请提供的线路板包括芯板，芯板上开设有槽体，槽体包括多个第一子槽体及多个位于第一子槽体下方且与第一子槽体位置对应的第二子槽体；芯片组件设置于槽体中；芯片组件包括多个位于第一子槽体中的第一芯片及多个位于第二子槽体中的第二芯片；其中，每一第一芯片与其位置对应的第二芯片串联形成多个芯片组；多个芯片组相互并联，且多个芯片组一端连接第一电源信号层，另一端连接地线层。以此将芯片嵌入到线路板中与线路板结合，以实现线路板的轻薄化及小型化。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图 仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本申请线路板的第一实施例的结构示意图；
图2是本申请线路板的槽体的结构示意图；
图3是本申请线路板的第二实施例的结构示意图；
图4是本申请线路板的制作方法的第一实施例的流程示意图；
图5是本申请线路板的制作方法的第二实施例的流程示意图；
图6是本申请线路板的制作方法的第三实施例的流程示意图；
图7是本申请线路板的制作方法的第四实施例的流程示意图。
【具体实施方式】
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
请参见图1，为本申请线路板的第一实施例的结构示意图。包括：芯板11及芯片组件12；芯板11上开设有槽体，请参见图2，槽体包括多个第一子槽体111，及位于第一子槽体111下方的多个第二子槽体112。在本实施例中，第一子槽体111及第二子槽体112呈阵列排布，且第二子槽体112位于第一子槽体111下方，且与第一子槽体111一一对应。芯片组件12包括位于第一子槽体111中的第一芯片121及位于第二子槽体112中的第二芯片122。本实施例以三个第一芯片121及三个第二芯片122为例进行说明。图1所示的结构示意图为线路板的侧视图。
在本实施例中，一个第一芯片121对应放置于一个第一子槽体111中，一个第二芯片122对应放置在一个第二子槽体113中。在另一实施例中，还可以一个槽体放置多个芯片，本实施例均以一个槽体放置一个芯片为例进行说明。
图1所示的线路板还包括第一线路层15及第二线路层14，第一线 路层15及第二线路层14分别设置在芯板11的两侧，并通过第一绝缘层17及第二绝缘层16与芯板11连接。具体的，第一绝缘层17设置在芯板11与第一线路层15之间，用于将芯板11与第一线路层15连接；第二绝缘层16设置在芯板11与第二线路层14之间，用于将芯板11与第二线路层14连接。
本申请中，芯板11的材料为覆铜板，覆铜板为制作线路板的基础材料，包括基材板及覆盖在所述基材上的铜箔，所述基材板由纸基板、玻纤布基板、合成纤维布基板、无纺布基板、复合基板等材料浸以树脂，制成粘结片，由多张粘结片组合制成，在制作好的基材板单面或双面覆以铜箔，再进行热压固化以制成覆铜板。第一绝缘层17及第二绝缘层16为半固化片，其作为层压时的层间粘结层，具体地，所述半固化片主要由树脂和增强材料组成，在制作多层线路板时，通常采用玻纤布做增强材料，将其浸渍上树脂胶液，再经热处理预烘制成薄片，其加热加压下会软化，冷却后会固化，且具有黏性，在高温压合过程中能将相邻的两层黏合。
在本实施例中，位于第一子槽体111中的第一芯片121与位于第二子槽体112中的第二芯片122之间相互串联并形成多个芯片组，且多个芯片组并联，即多个芯片组一端连接第一电源信号层，另一端连接地线层。
具体的，第一芯片121及第二芯片122均包括第一连接端子、第二连接端子及第三连接端子。其中，第二连接端子及第三连接端子位于靠近第一线路层一侧，第一连接端子位于靠近第二线路层一侧。在第一芯片121与第二芯片122进行串联形成芯片组时，第一芯片121的第一连接端子连接与其位置对应的第二芯片122的第二连接端子。在各个芯片组相互并联时，芯片组的一端连接第一电源信号层，另一端连接地线层。
如图1所示，本实施例中的线路板中的第一线路层15包括互不连接的第一电源信号层151及控制信号层152；第二线路层14包括互不连接的第二电源信号层141及地线层142。
本实施例中，为实现第一芯片121与第二芯片122的串联，即为实 现第一芯片121的第一连接端子与第二芯片122的第二连接端子之间的连接，第二绝缘层16对应第一芯片121的第一连接端子的位置处具有第一导电孔181，以将第二电源信号层141与第一芯片121的第一连接端子连接。第一绝缘层17对应第二芯片122的第二连接端子的位置处具有第二导电孔182，以将第一电源信号层151与第二芯片122的第二连接端子连接。第一芯片121及第二芯片122之间具有贯穿芯板11、第一绝缘层17及第二绝缘层16的第三导电孔183，以将第一电源信号层151及第二电源信号层141连接，进而将第一芯片121的第一连接端子与第二芯片122的第二连接端子连接，以将第一芯片121与第二芯片122串联。
本实施例中，为实现将芯片组相互并联，将每一第一芯片121的第二连接端子相互连接，将每一第二芯片122的第一连接端子相互连接。具体的，为实现将每一第一芯片121的第二连接端子相互连接，第一绝缘层17对应第一芯片121的第二连接端子的位置处具有第五导电孔185，以将每一第一芯片121的第二连接端子与第一电源信号层151连接；通过第一电源信号层151将第一芯片121的第二连接端子并联。为实现将每一第二芯片122的第一连接端子相互连接，第二绝缘层16对应第二芯片122的第一连接端子的位置处具有第六导电孔186，以将每一第二芯片122的第一连接端子与地线层142连接；通过地线层142将第二芯片122的第一连接端子并联。
进一步的，在本实施例中，第一绝缘层17对应第一芯片121及第二芯片122的第三连接端子的位置处具有第四导电孔184，第四导电孔184用于将第一芯片121及第二芯片122的第三连接端子与控制信号层152连接。
本实施例所示的线路板，通过在线路板中埋入多颗第一芯片121及第二芯片122，且使第一芯片121与对应的第二芯片122串联形成芯片组，使芯片组之间并联，以此实现埋入式线路板的轻薄化及小型化，并能够实现信号传输距离短及减少信号损失的目的。
请参见图3，为本申请线路板的第二实施例的结构示意图。包括： 芯板21及芯片组件22；芯板21上开设有槽体，请参见图2，槽体包括行排列的多个第一子槽体111，及位于第一子槽体111下方的多个第二子槽体112。芯片组件22包括位于第一子槽体111中的第一芯片221及位于第二子槽体112中的第二芯片222。本实施例以三个第一芯片221及三个第二芯片222为例进行说明。图3所示的线路板的结构示意图为线路板的侧视图。
图3所示的线路板还包括第一电源信号层251及第二电源信号层241，第一电源信号层251及第二电源信号层241分别设置在芯板21的两侧，并通过第一绝缘层271及第二绝缘层261与芯板21连接。具体的，第一绝缘层271设置在芯板21与第一电源信号层251之间，用于将芯板21与第一电源信号层251连接；第二绝缘层261设置在芯板21与第二电源信号层241之间，用于将芯板21与第二电源信号层241连接。
本实施例所示的线路板还包括第三绝缘层272、第四绝缘层262、控制信号层252及地线层242。其中，控制信号层252位于第一电源信号层251远离芯板21的一侧，地线层242位于第二电源信号层241远离芯板21的一侧。第三绝缘层272位于第一电源信号层251及控制信号层252之间，用于将第一电源信号层251及控制信号层252粘合，第四绝缘层262位于第二电源信号层241及地线层242之间，用于将第二电源信号层241及地线层242粘合。
具体的，第一芯片221及第二芯片222均包括第一连接端子、第二连接端子及第三连接端子。在第一芯片221与第二芯片222进行串联以形成芯片组时，第一芯片221的第一连接端子连接与其位置对应的第二芯片222的第二连接端子。在每一芯片组之间相互并联时，芯片组的一端连接第一电源信号层251，另一端连接地线层242。具体地，第一芯片221的第二连接端子连接第一电源信号层251，第二芯片222的第一连接端子连接地线层242。
如图3所示，本实施例中，为实现第一芯片221与第二芯片222的串联，即为实现第一芯片221的第一连接端子与第二芯片222的第二连 接端子之间的连接，第二绝缘层261对应第一芯片221的第一连接端子的位置处具有第一导电孔281，以将第二电源信号层241与第一芯片221的第一连接端子连接。第一绝缘层271对应第二芯片222的第二连接端子的位置处具有第二导电孔282，以将第一电源信号层251与第二芯片222的第二连接端子连接。第一芯片221及第二芯片222之间具有贯穿芯板21、第一绝缘层271及第二绝缘层261的第三导电孔183，以将第一电源信号层251与第二电源信号层241连接，进而将第一芯片221的第一连接端子与第二芯片222的第二连接端子连接，以将第一芯片221与第二芯片222串联。
本实施例中，为实现多个芯片组的相互并联，将每一第一芯片221的第二连接端子相互连接且连接至第一电源信号层251，将每一第二芯片222的第一连接端子相互连接且连接至地线层242。具体的，为实现将每一第一芯片221的第二连接端子相互连接，第一绝缘层271对应第一芯片221的第二连接端子的位置处具有第五导电孔285，以将每一第一芯片221的第二连接端子与第一电源信号层251连接；通过第一电源信号层251将第一芯片221的第二连接端子并联。为实现将第二芯片222相互并联，将每一第二芯片222的第一连接端子相互连接。具体的，为实现将每一第二芯片222的第一连接端子相互连接，第二绝缘层261对应第二芯片222的第一连接端子的位置处具有第六导电孔286，以将每一第二芯片222的第一连接端子与地线层242连接；通过地线层242将第二芯片222的第一连接端子并联。
进一步的，在本实施例中，第一绝缘层271及第三绝缘层272对应第一芯片221及第二芯片222的第三连接端子的位置处具有第四导电孔284，第四导电孔284用于将第一芯片221及第二芯片222的第三连接端子与控制信号层252连接。
本实施例所示的线路板，通过在线路板中埋入多颗第一芯片221及第二芯片222，且使第一芯片221与对应的第二芯片222串联形成芯片组，是、使芯片组之间相互并联，以此实现埋入式线路板的轻薄化及小型化，并能够实现信号传输距离短及减少信号损失的目的。
请参见图4，为本申请线路板的制作方法的第一实施例的流程示意图。包括：步骤S41：提供芯板。
本申请中，芯板的材料为覆铜板，覆铜板为制作线路板的基础材料，包括基材板及覆盖在所述基材上的铜箔，所述基材板由纸基板、玻纤布基板、合成纤维布基板、无纺布基板、复合基板等材料浸以树脂，制成粘结片，由多张粘结片组合制成，在制作好的基材板单面或双面覆以铜箔，再进行热压固化以制成覆铜板。
步骤S42：在所述芯板上开设槽体，所述槽体包括多个第一子槽体及多个位于所述第一子槽体下方且与所述第一子槽体位置对应的第二子槽体。
使用蚀刻、激光钻、机械钻等方式在芯板上开设槽体。本申请中由于放置的芯片为多颗且呈阵列排布，因此槽体包括第一子槽体及位于第一子槽体下方的第二子槽体，且第一子槽体及第二子槽体的位置一一对应。
步骤S43：在所述槽体中放置芯片组件，所述芯片组件包括多个位于所述第一子槽体中的第一芯片及多个位于所述第二子槽体中的第二芯片，其中，每一所述第一芯片与其位置对应的所述第二芯片串联形成多个芯片组；所述多个芯片组相互并联，且所述多个芯片组一端连接第一电源信号层，另一端连接地线层。
在槽体中设置芯片组件，其中芯片组件包括第一芯片及第二芯片，第一芯片放置于第一子槽体中，第二芯片放置于第二子槽体中。且第一芯片与相对应的第二芯片一一串联形成芯片组，多个芯片组相互并联，即多个芯片组一端连接第一电源信号层，另一端连接地线层。
具体地，请参照图5，为本申请线路板的制作方法的第二实施例的流程示意图，与上述图4所示的第一实施例相比，区别在于：在步骤S43之后还包括：
步骤S51：在芯板的一侧设置第一线路板，及在芯板远离第一线路层的一侧设置第二线路层；其中，第一线路层包括第一电源信号层及控制信号层，第二线路层包括地线层及第二电源信号层。
在芯板的两侧设置第一线路层及第二线路层。具体地，第一线路层及第二线路层均为在铜层上制作的线路网络。第一电源信号层及控制信号层为分别为第一线路层上的不同的线路网络，地线层及第二电源信号层分别为第二线路层上不同的线路网络。
步骤S52：在所述芯板及所述第一线路层之间设置第一绝缘层，及在所述芯板及所述第二线路层之间设置第二绝缘层。
在芯板及第一线路层之间设置第一绝缘层，以将芯板与第一线路层粘合。在芯板及所述第二线路层之间设置第二绝缘层，以将芯板与第二线路层粘合。具体地，第一绝缘层及第二绝缘层为半固化片，其作为层压时的层间粘结层，具体地，所述半固化片主要由树脂和增强材料组成，在制作多层线路板时，通常采用玻纤布做增强材料，将其浸渍上树脂胶液，再经热处理预烘制成薄片，其加热加压下会软化，冷却后会固化，且具有黏性，在高温压合过程中能将相邻的两层黏合。
请参见图6，为本申请线路板的制作方法的第三实施例的流程示意图，与图4所示的第一实施例相比，区别在于：在步骤S43之后还包括：
步骤S61：在所述芯板的一侧设置第一电源信号层，及在所述芯板远离所述第一电源信号层的一侧设置第二电源信号层。
其中，第一电源信号层及第二电源信号层均位于芯板的两侧，第一电源信号层及第二电源信号层为铜层制作的线路层。
步骤S62：在所述芯板及所述第一电源信号层之间设置第一绝缘层，及在所述芯板及所述第二电源信号层之间设置第二绝缘层。
其中，第一绝缘层及第二绝缘层为半固化片，在此不再赘述。
步骤S63：在所述第一电源信号层远离所述芯板的一侧设置控制信号层，及在所述第二电源信号层远离所述芯板的一侧设置地线层。
其中，控制信号层及地线层同样为铜层制作的线路层。具体地，控制信层位于第一电源信号层的外侧，地线层位于第二电源信号层的外侧。
步骤S64：在所述第一电源信号层及所述控制信号层之间设置第三绝缘层，及在所述第二电源信号层及所述地线层之间设置第四绝缘层。
其中，第四绝缘层及第三绝缘层与第一绝缘层及第二绝缘层相同，均为半固化片，在此不再赘述。
请参见图7，为本申请线路板的制作方法的第四实施例的流程示意图，与上述图5所示的第二实施例及图6所示的第三实施例相比，区别在于，还包括：
步骤S71：在所述第二绝缘层对应所述第一芯片的第一连接端子的位置处设置第一导电孔，在所述第一绝缘层对应所述第二芯片的第二连接端子的位置处设置第二导电孔，及在所述第一芯片及所述第二芯片之间设置贯穿所述芯板、所述第一绝缘层及所述第二绝缘层的第三导电孔，以将所述第一芯片的第一连接端子与所述第二芯片的第二连接端子连接。
通过连接第一芯片的第一连接端子及第二电源信号层的第一导电孔、连接第二芯片的第二连接端子及第一电源信号层的第二导电孔及连接第二电源信号层及第一电源信号层的第三导电孔将第一芯片的第一连接端子与第二芯片的第二连接端子连接，以使第一芯片及第二芯片形成相互串联的芯片组。
步骤S72：在所述第一绝缘层对应所述第一芯片的第二连接端子的位置处设置第五导电孔，以将所述第一芯片的所述第二连接端子与所述第一电源信号层连接；及在所述第二绝缘层对应所述第二芯片的第一连接端子的位置处设置第六导电孔，以将所述第二芯片的所述第一连接端子与所述地线层连接。
第五导电孔将第一芯片的第二连接端子与第一电源信号层连接，第六导电孔将第二芯片的第一连接端子与地线层连接，以将芯片组相互并联。
步骤S73：在所述第一绝缘层对应所述第一芯片及所述第二芯片的第三连接端子的位置处设置第四导电孔，以将所述第一芯片及所述第二芯片的第三连接端子与所述控制信号层连接。
第四导电孔将第一芯片及所述第二芯片的第三连接端子与所述控制信号层连接。
本申请提供的线路板及其制作方法，通过将多个芯片阵列排布且埋入在线路板中，以实现线路板的轻薄化及小型化。且使多颗芯片在线路板中有规律的进行串联及并联，以使信号传输距离短，减少信号的损失。
以上仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

  1. 一种线路板，其中，包括
    芯板，开设有槽体，所述槽体包括多个第一子槽体及多个位于所述第一子槽体下方且与所述第一子槽体位置对应的第二子槽体；
    芯片组件，设置于所述槽体中；所述芯片组件包括多个位于所述第一子槽体中的第一芯片及多个位于所述第二子槽体中的第二芯片；
    其中，每一所述第一芯片与其位置对应的所述第二芯片串联形成多个芯片组；所述多个芯片组相互并联，且所述多个芯片组一端连接第一电源信号层，另一端连接地线层。
  2. 根据权利要求1所述的线路板，其中，所述线路板还包括：第一线路层，设置在所述芯板的一侧；
    第二线路层，设置在所述芯板远离所述第一线路层的一侧；
    第一绝缘层，设置在所述芯板与所述第一线路层之间；
    第二绝缘层，设置在所述芯板与所述第二线路层之间；
    其中，所述第一线路层包括所述第一电源信号层及控制信号层；所述第二线路层包括所述地线层及第二电源信号层。
  3. 根据权利要求2所述的线路板，其中，所述线路板还包括：第一电源信号层，设置在所述芯板的一侧；
    第二电源信号层，设置在所述芯板远离所述第一电源信号层的一侧；
    第一绝缘层，设置在所述芯板与所述第一电源信号层之间；
    第二绝缘层，设置在所述芯板与所述第二电源信号层之间；
    位于所述第一电源信号层远离所述芯板的一侧的控制信号层；
    位于所述第二电源信号层远离所述芯板的一侧的地线层；
    位于所述第一电源信号层及所述控制信号层之间的第三绝缘层；
    位于所述第二电源信号层及所述地线层之间的第四绝缘层。
  4. 根据权利要求3所述的线路板，其中，每个所述第一芯片及所述第二芯片均包括：靠近所述第一线路层一侧的第二连接端子及第三连接端子，及靠近所述第二线路层的第一连接端子；
    其中，所述第一芯片的所述第一连接端子耦接与其位置对应的第二芯片的所述第二连接端子；所述第一芯片的第二连接端子耦接所述第一电源 信号层，所述第一芯片的第三连接端子耦接所述控制信号层，所述第二芯片的第三连接端子耦接所述控制信号层，所述第二芯片的第一连接端子连接所述地线层。
  5. 根据权利要求4所述的线路板，其中，
    所述第二绝缘层对应所述第一芯片的第一连接端子的位置处具有第一导电孔，以将所述第二电源信号层与所述第一芯片的第一连接端子连接；
    所述第一绝缘层对应所述第二芯片的第二连接端子的位置处具有第二导电孔，以将所述第一电源信号层与所述第二芯片的第二连接端子连接；
    所述第一芯片及所述第二芯片之间具有第三导电孔，以将所述第一电源信号层及所述第二电源信号层连接，进而将所述第一芯片的所述第一连接端子与所述第二芯片的所述第二连接端子连接，以将所述第一芯片及所述第二芯片串联形成多个芯片组。
  6. 根据权利要求4所述的线路板，其中，
    所述第一绝缘层对应所述第一芯片及所述第二芯片的第三连接端子的位置处具有第四导电孔，以将所述第一芯片及所述第二芯片的第三连接端子与所述控制信号层连接；或
    所述第一绝缘层及所述第三绝缘层对应所述第一芯片及所述第二芯片的第三连接端子的位置处具有第四导电孔，以将所述第一芯片及所述第二芯片的第三连接端子与所述控制信号层连接。
  7. 根据权利要求4所述的线路板，其中，
    所述第一绝缘层对应所述第一芯片的所述第二连接端子的位置处具有第五导电孔，以将所述第一芯片的所述第二连接端子与所述第一电源信号层连接；
    所述第二绝缘层对应所述第二芯片的所述第一连接端子的位置处具有第六导电孔，以将所述第二芯片的所述第一连接端子与所述地线层电连接；或
    所述第一绝缘层对应所述第一芯片的所述第二连接端子的位置处具有第五导电孔，以将每一所述第一芯片的第二连接端子与所述第一电源信号层连接；
    所述第二绝缘层及所述第四绝缘层对应所述第二芯片的所述第一连接 端子的位置处具有第六导电孔，以将每一所述第二芯片的所述第二连接端子与所述地线层电连接。
  8. 一种线路板的制作方法，其中，包括：
    提供芯板；
    在所述芯板上开设槽体，所述槽体包括多个第一子槽体及多个位于所述第一子槽体下方且与所述第一子槽体位置对应的第二子槽体；
    在所述槽体中放置芯片组件，所述芯片组件包括多个位于所述第一子槽体中的第一芯片及多个位于所述第二子槽体中的第二芯片，其中，每一所述第一芯片与其位置对应的所述第二芯片串联形成多个芯片组；所述多个芯片组相互并联，且所述多个芯片组一端连接第一电源信号层，另一端连接地线层。
  9. 根据权利要求8所述的制作方法，其中，所述在所述槽体中放置芯片组件，所述芯片组件包括多个位于所述第一子槽体中的第一芯片及多个位于所述第二子槽体中的第二芯片；其中，每一所述第一芯片与其位置对应的所述第二芯片串联形成多个芯片组；所述多个芯片组相互并联，且所述多个芯片组一端连接第一电源信号层，另一端连接地线层的步骤之后包括：
    在所述芯板的一侧设置第一线路板，及在所述芯板远离所述第一线路层的一侧设置第二线路层；其中，所述第一线路层包括第一电源信号层及控制信号层，所述第二线路层包括地线层及第二电源信号层；
    在所述芯板及所述第一线路层之间设置第一绝缘层，及在所述芯板及所述第二线路层之间设置第二绝缘层；或
    在所述芯板的一侧设置第一电源信号层，及在所述芯板远离所述第一电源信号层的一侧设置第二电源信号层；
    在所述芯板及所述第一电源信号层之间设置第一绝缘层，及在所述芯板及所述第二电源信号层之间设置第二绝缘层；
    在所述第一电源信号层远离所述芯板的一侧设置控制信号层，及在所述第二电源信号层远离所述芯板的一侧设置地线层；
    在所述第一电源信号层及所述控制信号层之间设置第三绝缘层，及在所述第二电源信号层及所述地线层之间设置第四绝缘层。
  10. 根据权利要求9所述的制作方法，其中，所述方法还包括：
    在所述第二绝缘层对应所述第一芯片的第一连接端子的位置处设置第一导电孔，在所述第一绝缘层对应所述第二芯片的第二连接端子的位置处设置第二导电孔，及在所述第一芯片及所述第二芯片之间设置贯穿所述芯板、所述第一绝缘层及所述第二绝缘层的第三导电孔，以将所述第一芯片的第一连接端子与所述第二芯片的第二连接端子连接；
    在所述第一绝缘层对应所述第一芯片的第二连接端子的位置处设置第五导电孔，以将所述第一芯片的所述第二连接端子与所述第一电源信号层连接；及在所述第二绝缘层对应所述第二芯片的第一连接端子的位置处设置第六导电孔，以将所述第二芯片的所述第一连接端子与所述地线层连接；
    在所述第一绝缘层对应所述第一芯片及所述第二芯片的第三连接端子的位置处设置第四导电孔，以将所述第一芯片及所述第二芯片的第三连接端子与所述控制信号层连接。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112201652A (zh) * 2019-07-07 2021-01-08 深南电路股份有限公司 线路板及其制作方法
WO2023272642A1 (zh) * 2021-06-30 2023-01-05 深南电路股份有限公司 电子元件封装体、电子组件、电压调节模块以及稳压器件
WO2023272644A1 (zh) * 2021-06-30 2023-01-05 深南电路股份有限公司 一种电子组件、电压调节模块以及稳压器件
CN115732943A (zh) * 2021-09-01 2023-03-03 深南电路股份有限公司 用于相控阵天线收发组件的印制线路板、收发组件及雷达
CN115209609A (zh) * 2022-07-01 2022-10-18 深圳中富电路股份有限公司 埋入元件的多层线路板及线路板的制作方法
CN115206190B (zh) * 2022-07-11 2023-11-28 武汉华星光电半导体显示技术有限公司 显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097427A (zh) * 2009-11-10 2011-06-15 英飞凌科技股份有限公司 层叠型电子器件
US20140003012A1 (en) * 2012-07-02 2014-01-02 Samsung Electro-Mechanics Co., Ltd. Capacitor-embedded printed circuit board
CN103703874A (zh) * 2011-07-13 2014-04-02 揖斐电株式会社 电子部件内置电路板及其制造方法
US20160174381A1 (en) * 2014-12-10 2016-06-16 Samsung Electro-Mechanics Co., Ltd. Embedded printed circuit board and method of manufacturing the same
US20200111748A1 (en) * 2018-10-04 2020-04-09 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With Face-Up and Face-Down Embedded Components

Family Cites Families (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3462282B2 (ja) * 1994-11-29 2003-11-05 株式会社東芝 樹脂封止型半導体装置、電子回路装置およびこの製造方法
JP2001102749A (ja) * 1999-09-17 2001-04-13 Internatl Business Mach Corp <Ibm> 回路基板
KR100488412B1 (ko) * 2001-06-13 2005-05-11 가부시키가이샤 덴소 내장된 전기소자를 갖는 인쇄 배선 기판 및 그 제조 방법
JP2004235266A (ja) * 2003-01-28 2004-08-19 Kyocera Corp 電子素子内蔵多層配線基板
US6928726B2 (en) * 2003-07-24 2005-08-16 Motorola, Inc. Circuit board with embedded components and method of manufacture
US7148577B2 (en) * 2003-12-31 2006-12-12 Intel Corporation Materials for electronic devices
TWI301739B (en) * 2004-12-03 2008-10-01 Via Tech Inc Structure and method for embedded passive component assembly
JP4682606B2 (ja) * 2004-12-07 2011-05-11 ソニー株式会社 インダクタンス素子及びその製造方法、並びに配線基板
CA2589485A1 (en) * 2004-12-07 2006-06-15 Ronald W. Whittaker Miniature circuitry and inductive components and methods for manufacturing same
US7687724B2 (en) * 2005-01-10 2010-03-30 Endicott Interconnect Technologies, Inc. Circuitized substrate with internal resistor, method of making said circuitized substrate, and electrical assembly utilizing said circuitized substrate
US20060286696A1 (en) * 2005-06-21 2006-12-21 Peiffer Joel S Passive electrical article
KR100704936B1 (ko) * 2005-06-22 2007-04-09 삼성전기주식회사 전자부품 내장 인쇄회로기판 및 그 제작방법
TWI269365B (en) * 2005-08-08 2006-12-21 Advanced Semiconductor Eng Substrate process and structure for embedded component
KR100700922B1 (ko) * 2005-10-17 2007-03-28 삼성전기주식회사 수동 소자를 내장한 기판 및 그 제조 방법
TWI260075B (en) * 2005-10-24 2006-08-11 Via Tech Inc Embedded inductor element and chip package applying the same
DE102005054233A1 (de) * 2005-11-14 2007-05-16 Grieshaber Vega Kg Hohlleiterübergang
WO2007054355A1 (de) * 2005-11-14 2007-05-18 Vega Grieshaber Kg Hohlleiterübergang
KR100736635B1 (ko) * 2006-02-09 2007-07-06 삼성전기주식회사 베어칩 내장형 인쇄회로기판 및 그 제조 방법
CN100542379C (zh) * 2006-03-15 2009-09-16 日月光半导体制造股份有限公司 具有嵌入式元件的基板及其制造方法
KR100796523B1 (ko) * 2006-08-17 2008-01-21 삼성전기주식회사 전자부품 내장형 다층 인쇄배선기판 및 그 제조방법
TWI376088B (en) * 2006-11-14 2012-11-01 Pulse Eng Inc Wire-less inductive devices and methods
TWI327363B (en) * 2006-11-17 2010-07-11 Unimicron Technology Corp Carrier structure for semiconductor chip and method for manufacturing the same
KR100788213B1 (ko) * 2006-11-21 2007-12-26 삼성전기주식회사 전자소자 내장형 인쇄회로기판의 제조방법
KR20080076241A (ko) * 2007-02-15 2008-08-20 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조방법
TWI315658B (en) * 2007-03-02 2009-10-01 Phoenix Prec Technology Corp Warp-proof circuit board structure
TWI341577B (en) * 2007-03-27 2011-05-01 Unimicron Technology Corp Semiconductor chip embedding structure
CN101364581A (zh) * 2007-08-10 2009-02-11 全懋精密科技股份有限公司 嵌埋有芯片的承载板结构及其制作方法
JP2009054930A (ja) * 2007-08-29 2009-03-12 Cmk Corp 部品内蔵型多層プリント配線板及びその製造方法
JP5125567B2 (ja) * 2008-02-07 2013-01-23 株式会社デンソー 多層回路基板
JP5284155B2 (ja) * 2008-03-24 2013-09-11 日本特殊陶業株式会社 部品内蔵配線基板
CN101616541A (zh) * 2008-06-24 2009-12-30 华为技术有限公司 印制电路板及其制造方法、相关设备
TWI363411B (en) * 2008-07-22 2012-05-01 Advanced Semiconductor Eng Embedded chip substrate and fabrication method thereof
JP2010114434A (ja) * 2008-10-08 2010-05-20 Ngk Spark Plug Co Ltd 部品内蔵配線基板及びその製造方法
CN201345363Y (zh) * 2008-10-30 2009-11-11 欣兴电子股份有限公司 埋入式电路板结构
CN101511148B (zh) * 2009-03-13 2011-03-09 深圳市深南电路有限公司 一种集成于pcb上的谐振腔制备方法
CN101795539B (zh) * 2010-01-13 2011-11-09 深南电路有限公司 埋电感电路板的加工方法
CN102254885B (zh) * 2010-05-20 2014-01-15 深南电路有限公司 无源器件、无源器件埋入式电路板及其制造方法
CN201797029U (zh) * 2010-06-11 2011-04-13 深南电路有限公司 一种具有谐振腔的高频滤波器
KR101289140B1 (ko) * 2010-09-28 2013-07-23 삼성전기주식회사 임베디드 인쇄회로기판 및 그 제조방법
US8879276B2 (en) * 2011-06-15 2014-11-04 Power Gold LLC Flexible circuit assembly and method thereof
KR20130014122A (ko) * 2011-07-29 2013-02-07 삼성전기주식회사 전자 소자 내장 인쇄회로기판 및 그 제조방법
CN102300406B (zh) * 2011-08-19 2013-06-26 深南电路有限公司 埋入式电路板及其制作方法
CN103188882B (zh) * 2011-12-31 2015-12-16 深南电路有限公司 一种电路板及其制作方法
JP2013211426A (ja) * 2012-03-30 2013-10-10 Dainippon Printing Co Ltd 部品内蔵配線板、及びその製造方法
CN102933040A (zh) * 2012-10-23 2013-02-13 东莞生益电子有限公司 具有埋入电感器件的pcb板的制作方法
CN103840238A (zh) * 2012-11-20 2014-06-04 深圳光启创新技术有限公司 一种谐振腔、滤波器件及电磁波设备
KR101987285B1 (ko) * 2012-11-30 2019-06-10 삼성전기주식회사 인쇄회로기판용 수지 조성물, 절연필름, 프리프레그 및 인쇄회로기판
CN103871996A (zh) * 2012-12-11 2014-06-18 宏启胜精密电子(秦皇岛)有限公司 封装结构及其制作方法
CN103906372B (zh) * 2012-12-27 2017-03-01 碁鼎科技秦皇岛有限公司 具有内埋元件的电路板及其制作方法
KR101472640B1 (ko) * 2012-12-31 2014-12-15 삼성전기주식회사 회로 기판 및 회로 기판 제조방법
JP6113510B2 (ja) * 2013-01-16 2017-04-12 アルプス電気株式会社 磁気素子
US20140210111A1 (en) * 2013-01-25 2014-07-31 Apple Inc. Embedded package on package systems
CN104051405A (zh) * 2013-03-11 2014-09-17 欣兴电子股份有限公司 嵌埋有电子组件的线路板结构及其制法
US9142501B2 (en) * 2013-03-14 2015-09-22 International Business Machines Corporation Under ball metallurgy (UBM) for improved electromigration
CN203150678U (zh) * 2013-04-02 2013-08-21 武汉凡谷电子技术股份有限公司 介质谐振腔耦合连接结构
JP5639242B2 (ja) * 2013-04-12 2014-12-10 太陽誘電株式会社 電子部品内蔵基板
CN103327750B (zh) * 2013-06-03 2015-12-02 东莞生益电子有限公司 埋电感式印制电路板的制作方法以及该方法制得的电路板
US9082626B2 (en) * 2013-07-26 2015-07-14 Infineon Technologies Ag Conductive pads and methods of formation thereof
KR102192356B1 (ko) * 2013-07-29 2020-12-18 삼성전자주식회사 반도체 패키지
CN103489841B (zh) * 2013-08-08 2016-08-24 华进半导体封装先导技术研发中心有限公司 同时埋入电容、电感、电阻的pcb板及其制备方法
JP2015035497A (ja) * 2013-08-09 2015-02-19 イビデン株式会社 電子部品内蔵配線板
KR20150046615A (ko) * 2013-10-22 2015-04-30 삼성전기주식회사 다층 인쇄회로기판
CN104853522B (zh) * 2014-02-13 2018-02-23 深南电路有限公司 电路板制作方法和嵌入有金属基的电路板
AT515447B1 (de) * 2014-02-27 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte
JP6334962B2 (ja) * 2014-03-05 2018-05-30 新光電気工業株式会社 配線基板、及び、配線基板の製造方法
JP6373605B2 (ja) * 2014-03-05 2018-08-15 新光電気工業株式会社 配線基板、及び、配線基板の製造方法
WO2015149364A1 (zh) * 2014-04-04 2015-10-08 史利利 印制线路板
CN105322909A (zh) * 2014-06-06 2016-02-10 精工爱普生株式会社 电子器件封装用基板、电子器件封装、电子器件及制造方法
TWI513379B (zh) * 2014-07-02 2015-12-11 Nan Ya Printed Circuit Board 內埋元件的基板結構與其製造方法
JP2016076656A (ja) * 2014-10-08 2016-05-12 イビデン株式会社 電子部品内蔵配線板及びその製造方法
JP2016076658A (ja) * 2014-10-08 2016-05-12 イビデン株式会社 電子部品内蔵配線板及びその製造方法
JP2016096297A (ja) * 2014-11-17 2016-05-26 イビデン株式会社 金属塊内蔵配線板及びその製造方法
KR102281452B1 (ko) * 2014-11-20 2021-07-27 삼성전기주식회사 전자부품 내장 인쇄회로기판 및 그 제조방법
DE102014118462A1 (de) * 2014-12-11 2016-06-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Semiflexible Leiterplatte mit eingebetteter Komponente
DE102014118464A1 (de) * 2014-12-11 2016-06-16 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Leiterplatte mit einem asymmetrischen Schichtenaufbau
KR102139755B1 (ko) * 2015-01-22 2020-07-31 삼성전기주식회사 인쇄회로기판 및 그 제조방법
CN106163128A (zh) * 2015-04-07 2016-11-23 深南电路股份有限公司 一种扁平化集成电路结构及其加工方法
EP3091821A1 (en) * 2015-05-08 2016-11-09 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Printed circuit board
JP2016219478A (ja) * 2015-05-15 2016-12-22 イビデン株式会社 配線基板及びその製造方法
CN105047630B (zh) * 2015-07-08 2018-05-22 华进半导体封装先导技术研发中心有限公司 芯片后组装有源埋入封装结构及其生产工艺
CN106470526A (zh) * 2015-08-18 2017-03-01 宏启胜精密电子(秦皇岛)有限公司 电感结构、柔性电路板及其制作方法
CN208338048U (zh) * 2016-01-07 2019-01-04 株式会社村田制作所 多层基板
JP2017123459A (ja) * 2016-01-08 2017-07-13 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板
KR102493463B1 (ko) * 2016-01-18 2023-01-30 삼성전자 주식회사 인쇄회로기판, 이를 가지는 반도체 패키지, 및 인쇄회로기판의 제조 방법
CN107295747B (zh) * 2016-03-31 2021-03-12 奥特斯(中国)有限公司 器件载体及制造器件载体的方法
JP2017195261A (ja) * 2016-04-20 2017-10-26 イビデン株式会社 インターポーザ及びインターポーザの製造方法
CN106332447B (zh) * 2016-08-31 2018-09-21 电子科技大学 一种用于印制电路板埋嵌技术的电感结构及其制作方法
CN106848519B (zh) * 2017-01-17 2020-11-17 电子科技大学 一种人工复合介质填充的介质集成悬置线
CN108347820B (zh) * 2017-01-25 2020-09-15 奥特斯(中国)有限公司 容纳部件的基底结构上的高导热涂层
EP3478033A1 (en) * 2017-10-25 2019-05-01 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding component with pre-connected pillar in component carrier
KR101963293B1 (ko) * 2017-11-01 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
EP3483929B1 (en) * 2017-11-08 2022-04-20 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with electrically conductive and insulating layers and a component embedded therein and manufacturing method thereof
CN207491318U (zh) * 2017-12-08 2018-06-12 中国电子科技集团公司第三十研究所 一种基于埋容材料的板级电源分配网络
JP2019117910A (ja) * 2017-12-27 2019-07-18 イビデン株式会社 プリント配線板
CN207783281U (zh) * 2018-02-27 2018-08-28 浙江万正电子科技有限公司 埋平面电阻聚酰亚胺多层线路板
CN109195327A (zh) * 2018-08-20 2019-01-11 深圳崇达多层线路板有限公司 一种解决埋磁位表面凹坑及分层爆板的方法
US10879575B2 (en) * 2018-10-04 2020-12-29 International Business Machines Corporation Embedded filtering in PCB integrated ultra high speed dielectric waveguides using photonic band gap structures
CN109257874A (zh) * 2018-11-16 2019-01-22 深圳市和美精艺科技有限公司 一种在pcb板制作过程中芯片埋入的方法及其结构
CN112201652A (zh) * 2019-07-07 2021-01-08 深南电路股份有限公司 线路板及其制作方法
CN111564414B (zh) * 2019-12-12 2021-09-24 奥特斯(中国)有限公司 部件承载件及制造部件承载件的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097427A (zh) * 2009-11-10 2011-06-15 英飞凌科技股份有限公司 层叠型电子器件
CN103703874A (zh) * 2011-07-13 2014-04-02 揖斐电株式会社 电子部件内置电路板及其制造方法
US20140003012A1 (en) * 2012-07-02 2014-01-02 Samsung Electro-Mechanics Co., Ltd. Capacitor-embedded printed circuit board
US20160174381A1 (en) * 2014-12-10 2016-06-16 Samsung Electro-Mechanics Co., Ltd. Embedded printed circuit board and method of manufacturing the same
US20200111748A1 (en) * 2018-10-04 2020-04-09 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With Face-Up and Face-Down Embedded Components

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