WO2022007274A1 - 一种电路板及其制作方法 - Google Patents

一种电路板及其制作方法 Download PDF

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Publication number
WO2022007274A1
WO2022007274A1 PCT/CN2020/127017 CN2020127017W WO2022007274A1 WO 2022007274 A1 WO2022007274 A1 WO 2022007274A1 CN 2020127017 W CN2020127017 W CN 2020127017W WO 2022007274 A1 WO2022007274 A1 WO 2022007274A1
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Prior art keywords
layer
circuit
insulating
sublayer
core board
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PCT/CN2020/127017
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English (en)
French (fr)
Inventor
黄立湘
王泽东
缪桦
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深南电路股份有限公司
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Publication of WO2022007274A1 publication Critical patent/WO2022007274A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/08—Magnetic details
    • H05K2201/083—Magnetic materials
    • H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present application relates to the technical field of chip embedding, and in particular, to a circuit board and a manufacturing method thereof.
  • the present application mainly provides a circuit board and a manufacturing method thereof, which are compact in structure, convenient in process steps, high in integration, reduce in manufacturing cost, have wide adaptability, and are safe and reliable.
  • the present application provides a method for manufacturing a circuit board, comprising: providing a core board with a first surface and a second surface arranged oppositely; At least one groove body is opened on it; at least one chip is placed in the corresponding groove body; the first insulating sublayer and the first circuit sublayer are alternately stacked on the first surface in turn; the second surface is alternately stacked on the second surface.
  • the present application provides a circuit board, the circuit board includes: a first functional layer, a buried capacitance material layer, a spacer insulating layer, a core board layer and a second functional layer that are stacked in sequence; the core board layer includes a core board and at least one chip, at least one groove body is formed on the core board, and the chip is arranged in the corresponding groove body.
  • the present application provides a method for manufacturing a circuit board, comprising: providing a core board layer, wherein the core board layer includes a core board and at least one chip, at least one groove is formed on the core board, and the chip is disposed on the In the corresponding tank body; a spacer insulation layer is arranged on the core board layer; a buried capacitance material layer is arranged on the side of the spacer insulation layer away from the core board layer; a first functional layer is arranged on the side of the buried capacitance material layer away from the spacer insulation layer ; Disposing a second functional layer on the side of the core board layer away from the spacer insulating layer; pressing the first functional layer and the second functional layer to obtain a circuit board.
  • a groove body is formed on the core board, and the chip is arranged in the groove body of the core board, and the first functional layer and the spacer are set in the buried capacity material layer.
  • the capacitor is embedded.
  • FIG. 1 is a schematic structural diagram of an embodiment of the circuit board of the present application.
  • FIG. 2 is a schematic structural diagram of an embodiment of a manufacturing method of a circuit board of the present application
  • FIG. 3 is a schematic structural diagram of another embodiment of the manufacturing method of the circuit board of the present application.
  • FIG. 4 is a schematic structural diagram of yet another embodiment of a method for manufacturing a circuit board of the present application.
  • FIG. 1 is a schematic structural diagram of an embodiment of a circuit board of the present application.
  • the circuit board 100 includes: a first functional layer 10, a buried capacitance material layer 20, a spacer insulating layer 30, a core board layer 40 and a second functional layer 50 which are stacked in sequence.
  • the core board layer 40 includes a core board 41 , at least one groove body 410 is formed on the core board 41 , and at least one chip 42 is disposed in the corresponding groove body 410 .
  • the chip 42 may include a camera chip 42 for photographing, a fingerprint chip 42 for light-sensitive fingerprint identification, a speaker chip 42 and the like, which are not limited herein.
  • the core board 41 can be a copper clad laminate, that is, a basic material for making the circuit board 100, including a base material board and a copper foil 22 covering the base material board.
  • a copper clad laminate that is, a basic material for making the circuit board 100, including a base material board and a copper foil 22 covering the base material board.
  • Substrates, synthetic fiber cloth substrates, non-woven substrates, composite substrates and other materials are impregnated with resin to form a bonding sheet, which is made by combining multiple bonding sheets, and is covered on one or both sides of the prepared base material.
  • the copper foil 22 is then cured by hot pressing to form a copper clad laminate.
  • the spacer insulating layer 30 is used to separate the buried capacitance material layer 20 from the core board layer 40 , so that the buried capacitance material layer 20 and the core board layer 40 are spaced apart and insulated from each other.
  • the circuit board 100 and the manufacturing method thereof provided by the present application by opening a groove body 410 on the core board 41, and arranging the chip 42 in the groove body 410 of the core board 41, and burying the material
  • the layer 20 is arranged between the first functional layer 10 and the spacer insulating layer 30, that is, a capacitor is embedded between the core board layer 40 and the first functional layer 10, and the buried capacitor material layer 20 is prevented from warping by a symmetrical lamination process.
  • the manufacturing cost is reduced, the product qualification rate is improved, the structure is compact, the process steps are convenient, the integration is high, the adaptability is wide, and it is safe and reliable.
  • the first functional layer 10 includes a first insulating layer 11 and a first circuit layer 12 , and the first insulating layer 11 and the first circuit layer 12 are alternately stacked and disposed on the insulating layer far from the spaced insulating layer of the buried capacitance material layer 20 . 30 on one side, and the first insulating layer 11 is attached to the buried capacitance material layer 20 .
  • the second functional layer 50 includes a second insulating layer 51 and a second circuit layer 52. The second insulating layer 51 and the second circuit layer 52 are alternately stacked on the side of the core board layer 40 away from the spacer insulating layer 30, and the first The two insulating layers 51 are attached to the core layer 40 .
  • the first circuit layer 12 includes a ground wire, and the conductive hole 200 electrically connects the metal layer of the core board 41 to the ground wire on the first circuit layer 12 .
  • the metal layer of the core board 41 can be used as the ground terminal of the components, and the signal of the mounted components can be shielded by connecting with the ground wire.
  • connecting the metal layer of the core board 41 to the ground wire is more conducive to heat dissipation, and since this connection method reduces the ground loop between the first circuit layer 12 and the metal layer of the core board 41, it is beneficial to reduce the secondary
  • the generation of inductance and parasitic capacitance is beneficial to reduce the influence of secondary inductance and parasitic capacitance on the transmission signal, which is beneficial to improve the transmission performance of high-frequency signals or other signals, and is conducive to improving the miniaturization and integration of the circuit board 100 level.
  • the core board 41 has a first surface 411 and a second surface 412 which are oppositely disposed.
  • the core board layer 40 further includes: a first core board functional layer 42 and a second core board functional layer 43 .
  • the first core board functional layer 42 includes a first insulating sub-layer 421 and a first circuit sub-layer 422.
  • the first insulating sub-layer 421 and the first circuit sub-layer 422 are alternately stacked on the first surface 411, and the first insulator The layer 421 is adhered to the first surface 411 .
  • the second core board functional layer 43 includes a second insulating sub-layer 431 and a second circuit sub-layer 432.
  • the second insulating sub-layer 431 and the second circuit sub-layer 432 are alternately stacked on the second surface 412 in sequence, and the second insulating sub-layer 431 It is attached to the second surface 412 .
  • the core board 41 , the spacer insulating layer 30 , the first insulating sublayer 421 , the second insulating sublayer 431 , the first insulating layer 11 and the second insulating layer 51 are all provided with conductive holes 200 for interlayer connection.
  • the chip 42 has connection terminals 421 , and the connection terminals 421 of the chip 42 are electrically connected to the buried capacitance material layer 20 through the conductive holes 200 and the first circuit sub-layer 422 .
  • the first wiring layer 12 is electrically connected to the first wiring sublayer 422 , the second wiring sublayer 432 and the second wiring layer 52 through the conductive holes 200 .
  • the conductive holes 200A may be provided at the positions of the first insulating sublayer 421 and the second insulating sublayer 431 corresponding to the connection terminals 421 of the chip 42, and the conductive holes 200A are through holes, so that the connection terminals 421 of the chip 42 pass through the first
  • the conductive holes 200A in the insulating sub-layer 421 and the second insulating sub-layer 431 are electrically connected to the first circuit sub-layer 422 and the second circuit sub-layer 432 .
  • the spacer insulating layer 30 , the first insulating layer 11 , the second insulating layer 51 , and the core board 41 may be patterned to form the spacer insulating layer 30 , the first insulating layer 11 , the second insulating layer 51 and the core board 41 .
  • a conductive hole 200B is formed thereon, and the conductive hole 200B is a through hole to electrically connect the first circuit layer 12 to the first circuit sublayer 422 , the second circuit sublayer 432 and the second circuit layer 52 through the conductive hole 200B.
  • the thicknesses of 51 and the second circuit layer 52 are 10-40 ⁇ m (for example, 10 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m).
  • the spacer insulating layer 30 , the first insulating sub-layer 421 , the second insulating sub-layer 431 , the first insulating layer 11 and the second insulating layer 51 are prepregs.
  • the spacer insulating layer 30 , the first insulating sublayer 421 , the second insulating sublayer 431 , the first insulating layer 11 , and the second insulating layer 51 serve as interlayer adhesive layers during lamination.
  • the prepreg is mainly composed of resin and reinforcing material.
  • glass fiber cloth is usually used as the reinforcing material, which is impregnated with resin glue, and then pre-baked into thin sheets by heat treatment. It softens when pressed, solidifies after cooling, and is sticky, which can bond two adjacent layers during high temperature pressing. That is, the spacer insulating layer 30 will be melted during high temperature pressing, and then the buried capacitance material layer 20 and the core board layer 40 will be bonded together.
  • the first insulating sub-layer 421 will be melted during high temperature pressing, and then the first circuit sub-layers 422 will be bonded together, and the innermost first circuit sub-layer 422 will be bonded to the first surface 411 of the core board 41 . Together.
  • the second insulating sub-layer 431 will be melted during high-temperature lamination, thereby bonding the second circuit sub-layers 432 together, and bonding the innermost second circuit sub-layer 432 to the second surface 412 of the core board 41 on the Together.
  • the first insulating layer 11 will be melted during high temperature lamination, thereby bonding the first circuit layers 12 together, and bonding the innermost first circuit layer 12 and the buried capacitance material layer 20 together.
  • the second insulating layer 51 will be melted during high temperature lamination, thereby bonding the second circuit layers 52 together, and bonding the innermost second circuit layer 52 and the core board layer 40 together.
  • the thermal expansion coefficient of the spacer insulating layer 30 and the first insulating sub-layer 421 is smaller than that of the second insulating sub-layer 431 . Since the thermal expansion coefficients of the spacer insulating layer 30 and the first insulating sub-layer 421 are small, the spacer insulating layer 30 and the first insulating sub-layer 421 are not easily thermally deformed. The layer 421 can maintain a low coefficient of thermal expansion to minimize warpage of the buried capacitance material layer 20 .
  • first insulating sub-layer 421 , the second insulating sub-layer 431 and the spacer insulating layer 30 are three kinds of curable adhesive colloids with different expansion coefficients.
  • the curable viscous colloids described above are in a liquid or semi-liquid state during the thermocompression bonding process to flow or form around the various circuit layers.
  • thermally induced stresses at the seams of the various wiring layers and the curable adhesive colloid can be reduced.
  • the likelihood of separation of the seams of the individual circuit layers and the curable adhesive gel is reduced, thereby reducing the likelihood that fluids will undesirably seep or diffuse between the individual circuit layers and the curable adhesive gel.
  • the thickness of the buried capacitance material layer 20 is 10-200 ⁇ m (eg, 10 ⁇ m, 50 ⁇ m, 100 ⁇ m, 200 ⁇ m).
  • the buried capacitance material layer 20 includes a first electrode layer 21 , a copper foil 22 and a second electrode layer 23 that are stacked in sequence.
  • the first electrode layer 21 is attached to the first insulating layer 11
  • the second electrode layer 23 is insulated from spacers. Layer 30 fits.
  • the material of the first electrode layer 21 and the second electrode layer 23 is a copper layer
  • the third surface 221 and the fourth surface 223 of the copper foil 22 can be subjected to chemical copper deposition treatment to form the first electrode layer 21 and the fourth surface 223.
  • Two electrode layers 23 the fabricated copper layer may also be attached to the third surface 221 and the fourth surface 223 of the copper foil 22 .
  • the circuit board 100 further includes: a dielectric layer 60 , and the dielectric layer 60 is disposed between the buried capacitance material layer 20 and the sidewall of the groove body 410 .
  • the distance between the buried capacitance material layer 20 and the sidewall of the tank body 410 is 20-200 ⁇ m (eg, 20 ⁇ m, 50 ⁇ m, 100 ⁇ m, 150 ⁇ m, 200 ⁇ m).
  • the buried capacitance material layer 20 and the sidewall of the tank body 410 The distance between is 50-150 ⁇ m (eg 50 ⁇ m, 100 ⁇ m, 150 ⁇ m).
  • the dielectric layer 60 is one or any combination of resin and molding silica gel.
  • molding silica gel which is a colorless and transparent liquid, can be vulcanized at high temperature above 150°C, and has certain air permeability and elasticity during curing. It mainly has temperature resistance, weather resistance, electrical insulation, physiological inertness, low surface tension and low surface energy.
  • Resin refers to an organic polymer that has a softening or melting range after being heated, and has a tendency to flow under the action of external force when softened. It is solid, semi-solid, and sometimes liquid at room temperature.
  • FIG. 2 is a schematic structural diagram of an embodiment of a manufacturing method of a circuit board of the present application.
  • the manufacturing method of the circuit board 100 includes the following steps:
  • a core board layer 40 is provided.
  • the core board layer 40 includes a core board 41 and at least one chip 42 .
  • the core board 41 can be a copper clad laminate, that is, a basic material for making the circuit board 100, including a base material board and a copper foil 22 covering the base material board.
  • the base material board is made of paper substrate, glass fiber cloth substrate, and synthetic fiber cloth substrate. , non-woven substrates, composite substrates and other materials are impregnated with resin to make a bonding sheet, which is made of a combination of multiple bonding sheets, and the prepared substrate plate is covered with copper foil 22 on one or both sides, and then the Hot pressing and curing to make copper clad laminates.
  • At least one groove body 410 is provided at a designated position of the core board 41 , and the groove body 410 is used for placing the chip 42 . Therefore, in one embodiment, the groove body 410 needs to be larger than the chip 42 .
  • the distance between the buried capacitance material layer 20 and the sidewall of the groove body 410 is 20-200 ⁇ m (eg, 20 ⁇ m, 50 ⁇ m, 100 ⁇ m, 150 ⁇ m, 200 ⁇ m).
  • the groove body 410 may also be the same size as the core board 41 , as long as the chip 42 can be accommodated.
  • the chips 42 are placed in the groove bodies 410 , and the chips 42 are in one-to-one correspondence with the groove bodies 410 , that is, one chip 42 is placed in each groove body 410 .
  • the chip 42 needs to be bonded to the core board 41 , that is, the groove body 410 needs to be filled with a dielectric layer 60 , and the chip 42 and the core board 41 need to be connected through the dielectric layer 60 .
  • Glue is Glue.
  • the dielectric layer 60 is one or any combination of resin and molding silica gel.
  • molding silica gel which is a colorless and transparent liquid, can be vulcanized at high temperature above °C, and has certain air permeability and elasticity during curing. It mainly has temperature resistance, weather resistance, electrical insulation, physiological inertness, low surface tension and low surface energy.
  • Resin refers to an organic polymer that has a softening or melting range after being heated, and has a tendency to flow under the action of external force when softened. It is solid, semi-solid, and sometimes liquid at room temperature.
  • the above-mentioned step S40 specifically includes: the first insulating layer 11 and the first circuit layer 12 are alternately stacked on the side of the buried capacitance material layer 20 away from the spacer insulating layer 30, wherein the first insulating layer 11 is far from the buried capacitance material layer 20.
  • One side of the spacer insulating layer 30 is attached.
  • the above step S50 specifically includes: alternately stacking a second circuit layer 52 and a second insulating layer 51 on the side of the core board layer 40 away from the spacer insulating layer 30, wherein the second insulating layer 51 is spaced away from the core board layer 40. One side of the insulating layer 30 is attached.
  • the spacer insulating layer 30 , the first insulating layer 11 , and the second insulating layer 51 are prepregs.
  • the spacer insulating layer 30 , the first insulating layer 11 , and the second insulating layer 51 serve as interlayer adhesive layers during lamination.
  • the prepreg is mainly composed of resin and reinforcing material.
  • glass fiber cloth is usually used as the reinforcing material, which is impregnated with resin glue, and then pre-baked into thin sheets by heat treatment. It softens when pressed, solidifies after cooling, and is sticky, which can bond two adjacent layers during high temperature pressing. That is, the spacer insulating layer 30 will be melted during high temperature pressing, and then the buried capacitance material layer 20 and the core board 41 will be bonded together.
  • the first insulating layer 11 will be melted during high temperature lamination, thereby bonding the first circuit layers 12 together, and bonding the first circuit layers 12 and the core board 41 together.
  • the second insulating layer 51 will be melted during high temperature lamination, thereby bonding the second circuit layers 52 together, and bonding the second circuit layers 52 and the buried capacitance material layer 20 together.
  • the thermal expansion coefficient of the spacer insulating layer 30 is smaller than the thermal expansion coefficients of the first insulating layer 11 and the second insulating layer 51 . Since the thermal expansion coefficient of the spacer insulating layer 30 is small, the spacer insulating layer 30 is not easily thermally deformed. Therefore, in the process of thermocompression, the spacer insulating layer 30 can maintain a low thermal expansion coefficient, so that the buried capacitance material layer 20 is warped. Distortion is minimized.
  • the first functional layer 10 and the second functional layer 50 are pressed together on the outside of the first functional layer 10 and the second functional layer 50 to obtain the circuit board 100 .
  • FIG. 3 is a schematic structural diagram of another embodiment of the manufacturing method of the circuit board of the present application. The method also includes:
  • the copper foil 22 has a third surface 221 and a fourth surface 223 disposed opposite to each other.
  • the material of the first electrode layer 21 and the second electrode layer 23 is a copper layer
  • the third surface 221 and the fourth surface 223 of the copper foil 22 can be subjected to chemical copper deposition treatment to form the first electrode layer 21 and the fourth surface 223.
  • Two electrode layers 23 the fabricated copper layer may also be attached to the third surface 221 and the fourth surface 223 of the copper foil 22 .
  • the method also includes:
  • connection terminal 421 of the chip 42 is electrically connected to the buried capacitance material layer 20 through the conductive hole 200 and the first circuit sub-layer 422 .
  • the first wiring layer 12 is electrically connected to the first wiring sublayer 422 , the second wiring sublayer 432 and the second wiring layer 52 through the conductive holes 200 .
  • FIG. 4 is a schematic structural diagram of another embodiment of the method for fabricating a circuit board of the present application.
  • the step S10 also includes the following steps:
  • a core board 41 is provided.
  • the manufacture of the circuit board 100 starts from the processing of the core board 41 , which is the basic material for manufacturing the circuit board 100 .
  • the core board 41 has a first surface 411 and a second surface 412 that are opposite to each other.
  • At least one groove body 410 is formed on the core board 41 .
  • At least one groove 410 can be formed on the substrate by controlled depth milling, or by etching and laser ablation, which is not limited here.
  • the groove body 410 should have a certain depth to facilitate the subsequent embedding of the chips 42 .
  • the size of the groove body 410 is determined according to the size of the chips 42 to be embedded.
  • S13 Place at least one chip 42 in the corresponding slot body 410 .
  • the glue can be resin for sticking bare chip 42 or silver-based resin or other non-conductive glue that can fix the chip 42 in the tank body 410, so that the chip 42 is fixed in the tank body 410. in the tank body 410 .
  • a dielectric material is selected to fill the gap between the tank body 410 and the chip 42.
  • the dielectric material is a material used for semiconductor packaging, usually a liquid, which has the functions of heat dissipation and insulation, and is heated at 120°C ⁇ 300°C °C becomes solid.
  • the medium material can be one or any combination of resin and molding silica gel.
  • the dielectric material can also be a material that is usually liquid, has heat dissipation and electrical conductivity, and becomes solid at 120°C to 300°C. If there is a pad at the bottom of the chip 42, this material can be used. It is electrically connected to the bottom of the groove body 410, which is not limited here.
  • S14 Arrange the first insulating sub-layers 421 and the first circuit sub-layers 422 alternately on the first surface 411 in sequence.
  • S15 Arrange the second insulating sub-layers 431 and the second circuit sub-layers 432 alternately on the second surface 412 in sequence.
  • the core board layer 40 may be a multi-layer board.
  • the multi-layer board may be fabricated by a gap method, a build-up method, a plating-through method, or the like.
  • multi-layer boards are boards with more than two layers, such as four-layer, six-layer, eight-layer, etc., that is to say, multi-layer building templates larger than two-layer boards have insulating materials between the layers.
  • the printed board formed by drilling and sticking, and the layers must be connected according to the requirements, is called a multi-layer board.
  • the advantage of the multi-layer board is that the density of the multi-layer drilling pressure is high. It will be relatively small and the weight is relatively lighter.
  • a groove is formed on the core board, and the chip is arranged in the groove of the core board, and the buried capacitance material layer is provided between the first functional layer and the spacer insulating layer, that is, The capacitor is embedded between the core board layer and the first functional layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本申请涉及芯片埋入技术领域，具体公开了一种电路板及其制作方法，该电路板包括：芯板，开设有至少一个槽体；至少一个芯片，设置在相应的槽体中；埋容材料层，与芯板间隔且绝缘设置；第一功能层，设置在芯板的远离埋容材料层的第一表面上；第二功能层，设置在埋容材料层的远离芯板的第二表面上。通过上述方式，本申请的电路板结构紧凑，工艺步骤方便，集成度高，降低制造成本，适应范围广，安全可靠。

Description

一种电路板及其制作方法 【技术领域】
本申请涉及芯片埋入技术领域，特别是涉及一种电路板及其制作方法。
【背景技术】
今日的电子封装不但要提供芯片的保护，同时还要在一定的成本下满足不断增加的性能、可靠性、散热、功率分配等要求，功能芯片速度及处理能力的增加需要更多的引脚数，更快的时钟频率和更好的电源分配。同时由于用户对超薄，微缩，多功能，高性能且低耗电的智能移动电子产品的需求越来越大，直接促成移动终端芯片计算和通信功能的融合，出现集成度，复杂度越来越高，功耗和成本越来越低的趋势。
【发明内容】
本申请主要提供一种电路板及其制作方法，其结构紧凑，工艺步骤方便，集成度高，降低制造成本，适应范围广，安全可靠。
一方面，本申请提供了一种电路板的制作方法，包括：提供一芯板，具有相对设置的第一表面和第二表面；通过控深铣或通过蚀刻和激光烧蚀的方式在芯板上开设至少一个槽体；将至少一个芯片放置在相应的槽体中；在第一表面上依次交替层叠设置第一绝缘子层和第一线路子层；在第二表面上依次交替层叠设置第二绝缘子层和第二线路子层；在芯板层上设置间隔绝缘层；在间隔绝缘层远离芯板层的一侧设置埋容材料层；在埋容材料层远离间隔绝缘层的一侧设置第一功能层；在芯板层远离间隔绝缘层的一侧设置第二功能层；压合第一功能层和第二功能层，以得到电路板。
另一方面，本申请提供了一种电路板，电路板包括：依次层叠设置的第一功能层、埋容材料层、间隔绝缘层、芯板层以及第二功能层；芯板层包括芯板以及至少一个芯片，芯板上开设有至少一个槽体，芯片设置在相应的槽体中。
又一方面，本申请提供了一种电路板的制作方法，包括：提供一芯板层，其中，芯板层包括芯板以及至少一个芯片，芯板上开设有至少一个槽体，芯片设置在相应的槽体中；在芯板层上设置间隔绝缘层；在间隔绝缘层远离芯板层的一侧设置埋容材料层；在埋容材料层远离间隔绝缘层的一侧设置第一功能层；在芯板层远离间隔绝缘层的一侧设置第二功能层；压合第一功能层和第二功能层，以得到电路板。
本申请的有益效果是：区别于现有技术的情况，本申请通过在芯板上开设槽体，并将芯片设置在芯板的槽体中，而埋容材料层设置第一功能层与间隔绝缘层之间，即在芯板层与第一功能层之间埋入电容，通过对称压合工艺，避免埋容材料层发生翘曲，降低了制造成本，提高了产品合格率，结构紧凑，工艺步骤方便，集成度高，适应范围广，安全可靠。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1为本申请电路板的一实施例的结构示意图；
图2为本申请电路板的制作方法的一实施例的结构示意图；
图3为本申请电路板的制作方法的另一实施例的结构示意图；
图4为本申请电路板的制作方法的又一实施例的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参见图1，图1为本申请电路板的一实施例的结构示意图。电路 板100包括：依次层叠设置的第一功能层10、埋容材料层20、间隔绝缘层30、芯板层40以及第二功能层50。
芯板层40包括芯板41，芯板41上开设有至少一个槽体410，至少一个芯片42设置在相应的槽体410中。在一实施例中，芯片42可包括用于拍摄的摄像芯片42、用于光感指纹识别的指纹芯片42、扬声器芯片42等等，在此不做限定。
在本实施例中，芯板41可以为覆铜板，即为制作电路板100的基础材料，包括基材板及覆盖在基材板上的铜箔22，基材板由纸基板、玻纤布基板、合成纤维布基板、无纺布基板、复合基板等材料浸以树脂，制成粘结片，由多张粘结片组合制成，在制作好的基材板单面或双面覆以铜箔22，再进行热压固化以制成覆铜板。
间隔绝缘层30用于隔开埋容材料层20与芯板层40，以使埋容材料层20与芯板层40间隔且绝缘设置。
区别于现有技术的情况，本申请提供的电路板100及其制作方法，通过在芯板41上开设槽体410，并将芯片42设置在芯板41的槽体410中，而埋容材料层20设置第一功能层10与间隔绝缘层30之间，即在芯板层40与第一功能层10之间埋入电容，通过对称压合工艺，避免埋容材料层20发生翘曲，降低了制造成本，提高了产品合格率，结构紧凑，工艺步骤方便，集成度高，适应范围广，安全可靠。
在一实施例中，第一功能层10包括第一绝缘层11和第一线路层12，第一绝缘层11和第一线路层12依次交替层叠设置在埋容材料层20的远离间隔绝缘层30的一侧上，且第一绝缘层11与埋容材料层20贴合。第二功能层50包括第二绝缘层51和第二线路层52，第二绝缘层51和第二线路层52依次交替层叠在芯板层40的远离间隔绝缘层30的一侧上，且第二绝缘层51与芯板层40贴合。
其中，第一线路层12上包括接地线，导电孔200将芯板41的金属层与第一线路层12上的接地线电连接。这样在芯板41的金属层上若是安装有其他元器件时，芯板41的金属层可作为元器件的接地端，且通过与接地线的连接，可屏蔽安装的元器件的信号。
进一步地，将芯板41的金属层连接到接地线上，更加有利于散热，且由于此连接方式减少了第一线路层12与芯板41的金属层之间的接地回路，有利于减少次生电感和寄生电容的产生，进而有利于减少次生电感和寄生电容对传输信号的影响，进而有利于提高高频信号或其它信号的传输性能，且有利于提升电路板100的小型化集成化水平。
进一步地，芯板41具有相对设置的第一表面411和第二表面412。芯板层40还包括：第一芯板功能层42和第二芯板功能层43。
其中，第一芯板功能层42包括第一绝缘子层421和第一线路子层422，第一绝缘子层421和第一线路子层422依次交替层叠设置在第一表面411上，且第一绝缘子层421与第一表面411贴合。第二芯板功能层43包括第二绝缘子层431和第二线路子层432，第二绝缘子层431和第二线路子层432依次交替层叠设置在第二表面412上，且第二绝缘子层431与第二表面412贴合。
其中，芯板41、间隔绝缘层30、第一绝缘子层421、第二绝缘子层431、第一绝缘层11以及第二绝缘层51上均开设有用于层间连接的导电孔200。
芯片42具有连接端子421，芯片42的连接端子421通过导电孔200以及第一线路子层422与埋容材料层20电连接。第一线路层12通过导电孔200与第一线路子层422、第二线路子层432以及第二线路层52电连接。
具体地，可以在第一绝缘子层421、第二绝缘子层431对应芯片42的连接端子421的位置处设置导电孔200A，导电孔200A为贯通孔，以将芯片42的连接端子421分别通过第一绝缘子层421、第二绝缘子层431中的导电孔200A与第一线路子层422、第二线路子层432电连接。
另外，可以对间隔绝缘层30、第一绝缘层11、第二绝缘层51以及芯板41进行图形化，以在间隔绝缘层30、第一绝缘层11、第二绝缘层51以及芯板41上形成导电孔200B，导电孔200B为贯通孔，以将第一线路层12通过导电孔200B与第一线路子层422、第二线路子层432以及第二线路层52电连接。
其中，上述间隔绝缘层30、第一绝缘子层421、第一线路子层422、第二绝缘子层431、第二线路子层432、第一绝缘层11、第一线路层12、第二绝缘层51以及第二线路层52的厚度为10-40μm(例如10μm、20μm、30μm、40μm)。
在一实施例中，间隔绝缘层30、第一绝缘子层421、第二绝缘子层431、第一绝缘层11以及第二绝缘层51为半固化片。间隔绝缘层30、第一绝缘子层421、第二绝缘子层431、第一绝缘层11以及第二绝缘层51作为层压时的层间粘结层。
具体地，半固化片主要由树脂和增强材料组成，在制作多层电路板100时，通常采用玻纤布做增强材料，将其浸渍上树脂胶液，再经热处理预烘制成薄片，其加热加压下会软化，冷却后会固化，且具有黏性，在高温压合过程中能将相邻的两层黏合。即间隔绝缘层30在高温压合时会融化，进而将埋容材料层20与芯板层40粘合在一起。第一绝缘子层421在高温压合时会融化，进而将各个第一线路子层422粘合在一起，并将最内侧的第一线路子层422与芯板41的第一表面411粘合在一起。第二绝缘子层431在高温压合时会融化，进而将各个第二线路子层432粘合在一起，并将最内侧的第二线路子层432与芯板41的第二表面412粘合在一起。第一绝缘层11在高温压合时会融化，进而将各个第一线路层12粘合在一起，并将最内侧的第一线路层12与埋容材料层20粘合在一起。第二绝缘层51在高温压合时会融化，进而将各个第二线路层52粘合在一起，并将最内侧的第二线路层52与芯板层40粘合在一起。
进一步地，间隔绝缘层30以及第一绝缘子层421的热膨胀系数小于第二绝缘子层431的热膨胀系数。由于间隔绝缘层30以及第一绝缘子层421的热膨胀系数较小，因此间隔绝缘层30以及第一绝缘子层421不容易热变形，因此在热压合的过程中，间隔绝缘层30以及第一绝缘子层421可以保持低的热膨胀系数，使埋容材料层20的翘曲变形最小化。
进一步地，第一绝缘子层421、第二绝缘子层431与间隔绝缘层30 为可以膨胀系数不同的三种可固化粘性胶体。上述可固化粘性胶体在热压合过程期间处于液体或者半液体状态下，从而在各个线路层周围流动或成形。通过减小热膨胀系数不匹配性，能够会减小在各个线路层与可固化粘性胶体的接缝处的热诱导应力。因此，各个线路层与可固化粘性胶体的接缝分离的可能性减小，从而减小流体会不良地在各个线路层与可固化粘性胶体之间渗流或者扩散的可能性。
在一实施例中，埋容材料层20的厚度为10-200μm(例如10μm、50μm、100μm、200μm)。
其中，埋容材料层20包括依次层叠设置的第一电极层21、铜箔22以及第二电极层23，第一电极层21与第一绝缘层11贴合，第二电极层23与间隔绝缘层30贴合。
具体地，第一电极层21和第二电极层23的材料为铜层，可以对铜箔22的第三表面221和第四表面223进行化学沉铜处理，以形成第一电极层21和第二电极层23。在其他实施例中，也可以将制作好的铜层贴附在铜箔22的第三表面221和第四表面223上。
在一实施例中，电路板100还包括：介质层60，介质层60设置在埋容材料层20与槽体410的侧壁之间。其中，埋容材料层20与槽体410的侧壁之间的距离为20-200μm(例如20μm、50μm、100μm、150μm、200μm)，优选地，埋容材料层20与槽体410的侧壁之间的距离为50-150μm(例如50μm、100μm、150μm)。
具体地，介质层60为树脂、molding硅胶中的一种或任意组合。其中，molding硅胶，其是一种无色透明液体，能够在150℃以上高温下进行硫化，固化时具有一定的透气性及弹性。其主要具有耐温特性、耐候性、电气绝缘性、生理惰性、低表面张力和低表面能。树脂是指受热后有软化或熔融范围，软化时在外力作用下有流动倾向，常温下是固态、半固态，有时也可以是液态的有机聚合物。
请参见图2和图1，图2为本申请电路板的制作方法的一实施例的结构示意图。该电路板100的制作方法包括以下步骤：
S10：提供一芯板层40。
在本实施例中，芯板层40包括芯板41以及至少一个芯片42。芯板41可以为覆铜板，即为制作电路板100的基础材料，包括基材板及覆盖在基材板上的铜箔22，基材板由纸基板、玻纤布基板、合成纤维布基板、无纺布基板、复合基板等材料浸以树脂，制成粘结片，由多张粘结片组合制成，在制作好的基材板单面或双面覆以铜箔22，再进行热压固化以制成覆铜板。
在芯板41的指定位置设置至少一个槽体410，槽体410是用于放置芯片42的，因此在一实施例中，槽体410需要比芯片42大。优选地，埋容材料层20与槽体410的侧壁之间的距离为20-200μm(例如20μm、50μm、100μm、150μm、200μm)。或者在另一实施例中，槽体410还可以与芯板41等大，只要能够容置芯片42即可。
将芯片42设置到槽体410中，芯片42与槽体410一一对应，即每一槽体410中放入一个芯片42。在一实施例中，将芯片42设置到槽体410中后需要将芯片42与芯板41粘合，即需要在槽体410中填充介质层60，通过介质层60将芯片42与芯板41进行粘合。
其中，介质层60为树脂、molding硅胶中的一种或任意组合。其中，molding硅胶，其是一种无色透明液体，能够在℃以上高温下进行硫化，固化时具有一定的透气性及弹性。其主要具有耐温特性、耐候性、电气绝缘性、生理惰性、低表面张力和低表面能。树脂是指受热后有软化或熔融范围，软化时在外力作用下有流动倾向，常温下是固态、半固态，有时也可以是液态的有机聚合物。
S20：在芯板层40上设置间隔绝缘层30。
S30：在间隔绝缘层30远离芯板层40的一侧设置埋容材料层20。
S40：在埋容材料层20远离间隔绝缘层30的一侧设置第一功能层10。
上述步骤S40具体包括：埋容材料层20远离间隔绝缘层30的一侧上依次交替层叠设置第一绝缘层11和第一线路层12，其中，第一绝缘层11与埋容材料层20远离间隔绝缘层30的一侧贴合。
S50：在芯板层40远离间隔绝缘层30的一侧设置第二功能层50。
上述步骤S50具体包括：在芯板层40远离间隔绝缘层30的一侧上依次交替层叠设置第二线路层52和第二绝缘层51，其中，第二绝缘层51与芯板层40远离间隔绝缘层30的一侧贴合。
在一实施例中，上述间隔绝缘层30、第一绝缘层11、第二绝缘层51为半固化片。间隔绝缘层30、第一绝缘层11、第二绝缘层51作为层压时的层间粘结层。
具体地，半固化片主要由树脂和增强材料组成，在制作多层电路板100时，通常采用玻纤布做增强材料，将其浸渍上树脂胶液，再经热处理预烘制成薄片，其加热加压下会软化，冷却后会固化，且具有黏性，在高温压合过程中能将相邻的两层黏合。即间隔绝缘层30在高温压合时会融化，进而将埋容材料层20与芯板41粘合在一起。第一绝缘层11在高温压合时会融化，进而将各个第一线路层12粘合在一起，并将第一线路层12与芯板41粘合在一起。第二绝缘层51在高温压合时会融化，进而将各个第二线路层52粘合在一起，并将第二线路层52与埋容材料层20粘合在一起。
进一步地，间隔绝缘层30的热膨胀系数小于第一绝缘层11和第二绝缘层51的热膨胀系数。由于间隔绝缘层30的热膨胀系数较小，因此间隔绝缘层30不容易热变形，因此在热压合的过程中，间隔绝缘层30可以保持低的热膨胀系数，使埋容材料层20的翘曲变形最小化。
S60：压合第一功能层10和第二功能层50，以得到电路板100。
具体地，在第一功能层10和第二功能层50的外侧对第一功能层10和第二功能层50进行压合，得到电路板100。
请参见图3和图1，图3为本申请电路板的制作方法的另一实施例的结构示意图。该方法还包括：
S31：提供一铜箔22。
该铜箔22具有相对设置的第三表面221和第四表面223。
S32：在第三表面221上设置第一电极层21。
S33：在第四表面223上设置第二电极层23。
S34：压合第一电极层21和第二电极层23，以得到埋容材料层20。
具体地，第一电极层21和第二电极层23的材料为铜层，可以对铜箔22的第三表面221和第四表面223进行化学沉铜处理，以形成第一电极层21和第二电极层23。在其他实施例中，也可以将制作好的铜层贴附在铜箔22的第三表面221和第四表面223上。
该方法还包括：
S70：在芯板41、间隔绝缘层30、第一绝缘子层421、第二绝缘子层431、第一绝缘层11以及第二绝缘层51上形成用于层间连接的导电孔200。
其中，芯片42的连接端子421通过导电孔200以及第一线路子层422与埋容材料层20电连接。第一线路层12通过导电孔200与第一线路子层422、第二线路子层432以及第二线路层52电连接。
请参见图4和图1，图4为本申请电路板的制作方法的又一实施例的结构示意图。在步骤S10还包括以下步骤：
S11：提供一芯板41。
需要说明的是，电路板100的制造从对芯板41的加工开始，芯板41为制造电路板100的基本材料。本实施例中，该芯板41具有相对设置的第一表面411和第二表面412。
S12：在芯板41上开设至少一个槽体410。
具体地，在芯板41上开设至少一个槽体410，可以通过控深铣，或通过蚀刻和激光烧蚀的方式在基板上开设至少一个槽体410，此处不作限定。
需要说明的是，槽体410要具备一定的深度，以便后续芯片42的埋入，本实施例中，槽体410的尺寸根据需要嵌入的芯片42的尺寸确定。
S13：将至少一个芯片42放置在相应的槽体410中。
使用胶剂，在槽体410内嵌入芯片42，该胶剂可以为贴裸芯片42树脂或银基树脂或其它能够将芯片42固定于槽体410内的非导电胶剂，使得芯片42固定于槽体410内。
选用一介质材料将槽体410与芯片42之间的空隙填满，该介质材 料是一种用于半导体封装的材料，通常情况下为液体，其具有散热、绝缘作用，并在120℃～300℃变成固体。介质材料可以为树脂、molding硅胶中的一种或任意组合。
需要说明的是，介质材料也可以是通常情况下为液体，具有散热、导电作用，并在120℃～300℃变成固体的材料，如若在芯片42底部具有焊盘，可采用这种材料，使其与槽体410底部形成电性连接，此处不作限定。
S14：在第一表面411上依次交替层叠设置第一绝缘子层421和第一线路子层422。
S15：在第二表面412上依次交替层叠设置第二绝缘子层431和第二线路子层432。
本实施例中，芯板层40可以为多层板，可以理解的是，多层板可以采用间隙法、增层法、镀通法等方法制作而成。多层板顾名思议就是两层以上的板，比如说四层，六层，八层等等，也就是说，大于二层板的多层板建筑模板，层与层之间有绝缘材料隔开，且层与层之间必须按要求相连经过钻压、黏台而成的印制板叫做多层板，多层板的优点有因为是多层钻压的密度高，不用展开，体积就会比较小，重量也相对来说轻一点，因为密度高，减少了空间距离因此不是那么容易坏也就是说稳定性比较可靠，层数较多从而加大了设计的灵活性，从而得到广泛应用，正因为有这些优点，相对也有一些不足比如说造价高，生产时间长，检测难等等，不过这些不足对多层板的用途一点也不影响，多层板是建筑模板向高效率、多功能、大面积、小体积方向发展的必然产物。随着多层板技术的不断发展，尤其是大模板和超大模板的广泛深入应用，多层板正迅速向高密度、高精度、高层数化方向发展，提出了微细线条、小孔径贯穿、盲孔埋孔、高板厚孔径比等技术以满足市场的需要。
S16：压合第一线路子层422和第二线路子层432，以得到芯板层40。
本申请提供的电路板及其制作方法，通过在芯板上开设槽体，并将芯片设置在芯板的槽体中，而埋容材料层设置第一功能层与间隔绝缘层 之间，即在芯板层与第一功能层之间埋入电容，通过对称压合工艺，避免埋容材料层发生翘曲，降低了制造成本，提高了产品合格率，结构紧凑，工艺步骤方便，集成度高，适应范围广，安全可靠。
以上仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种电路板的制作方法，其特征在于，包括：
    提供一芯板，具有相对设置的第一表面和第二表面；
    通过控深铣或通过蚀刻和激光烧蚀的方式在所述芯板上开设至少一个所述槽体；
    将至少一个芯片放置在相应的所述槽体中；
    在所述第一表面上依次交替层叠设置第一绝缘子层和第一线路子层；
    在所述第二表面上依次交替层叠设置第二绝缘子层和第二线路子层；
    在所述芯板层上设置间隔绝缘层；
    在所述间隔绝缘层远离所述芯板层的一侧设置埋容材料层；
    在所述埋容材料层远离所述间隔绝缘层的一侧设置第一功能层；
    在所述芯板层远离所述间隔绝缘层的一侧设置第二功能层；
    压合所述第一功能层和所述第二功能层，以得到所述电路板。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    提供一铜箔，具有相对设置的第三表面和第四表面；
    在所述第三表面上设置第一电极层；
    在所述第四表面上设置第二电极层；
    压合所述第一电极层和所述第二电极层，以得到所述埋容材料层。
  3. 根据权利要求1所述的方法，其特征在于，所述在所述埋容材料层远离所述间隔绝缘层的一侧设置第一功能层的步骤包括：在所述埋容材料层远离所述间隔绝缘层的一侧上依次交替层叠设置第一绝缘层和第一线路层；
    所述在所述芯板层远离所述间隔绝缘层的一侧设置第二功能层的步骤包括：在所述芯板层远离所述间隔绝缘层的一侧上依次交替层叠设置第二线路层和第二绝缘层；
  4. 根据权利要求3所述的方法，其特征在于，所述方法还包括：
    在所述芯板、所述间隔绝缘层、所述第一绝缘子层、所述第二绝缘 子层、所述第一绝缘层以及所述第二绝缘层上形成用于层间连接的导电孔；
    其中，所述芯片的连接端子通过所述导电孔以及所述第一线路子层与所述埋容材料层电连接；
    所述第一线路层通过所述导电孔与所述第一线路子层、所述第二线路子层以及所述第二线路层电连接。
  5. 一种电路板，其特征在于，所述电路板包括：依次层叠设置的第一功能层、埋容材料层、间隔绝缘层、芯板层以及第二功能层；
    所述芯板层包括芯板以及至少一个芯片，所述芯板上开设有至少一个槽体，所述芯片设置在相应的所述槽体中。
  6. 根据权利要求5所述的电路板，其特征在于，
    所述第一功能层包括第一绝缘层和第一线路层，所述第一绝缘层和所述第一线路层依次交替层叠设置在所述埋容材料层的远离所述间隔绝缘层的一侧上，且所述第一绝缘层与所述埋容材料层贴合；
    所述第二功能层包括第二绝缘层和第二线路层，所述第二绝缘层和所述第二线路层依次交替层叠在所述芯板层的远离所述间隔绝缘层的一侧上，且所述第二绝缘层与所述芯板层贴合。
  7. 根据权利要求6所述的电路板，其特征在于，
    所述第一线路层包括接地线，所述芯板与所述接地线电连接。
  8. 根据权利要求7所述的电路板，其特征在于，所述芯板具有相对设置的第一表面和第二表面；
    所述芯板层还包括：第一芯板功能层和第二芯板功能层；
    其中，所述第一芯板功能层包括第一绝缘子层和第一线路子层，所述第一绝缘子层和所述第一线路子层依次交替层叠设置在所述第一表面上，且所述第一绝缘子层与所述第一表面贴合；
    所述第二芯板功能层包括第二绝缘子层和第二线路子层，所述第二绝缘子层和所述第二线路子层依次交替层叠设置在所述第二表面上，且所述第二绝缘子层与所述第二表面贴合。
  9. 根据权利要求7所述的电路板，其特征在于，所述芯板、所述间 隔绝缘层、所述第一绝缘子层、所述第二绝缘子层、所述第一绝缘层以及所述第二绝缘层上均开设有用于层间连接的导电孔；
    其中，所述芯片具有连接端子，所述芯片的连接端子通过所述导电孔以及所述第一线路子层与所述埋容材料层电连接；
    所述第一线路层通过所述导电孔与所述第一线路子层、所述第二线路子层以及所述第二线路层电连接。
  10. 根据权利要求8所述的电路板，其特征在于，所述间隔绝缘层、所述第一绝缘子层、所述第二绝缘子层、所述第一绝缘层以及所述第二绝缘层为半固化片。
  11. 根据权利要求8所述的电路板，其特征在于，所述间隔绝缘层以及所述第一绝缘子层的热膨胀系数小于所述第二绝缘子层的热膨胀系数。
  12. 根据权利要求8所述的电路板，其特征在于，第一绝缘子层、所述第二绝缘子层与所述间隔绝缘层为膨胀系数不同的三种可固化粘性胶体。
  13. 根据权利要求6所述的电路板，其特征在于，所述埋容材料层包括：依次层叠设置的第一电极层、铜箔以及第二电极层；
    所述第一电极层与所述第一绝缘层贴合；
    所述第二电极层与所述间隔绝缘层贴合。
  14. 根据权利要求8所述的电路板，其特征在于，
    所述间隔绝缘层、所述第一绝缘子层、所述第一线路子层、所述第二绝缘子层、所述第二线路子层、所述第一绝缘层、所述第一线路层、所述第二绝缘层以及所述第二线路层的厚度为10-40μm；
    所述埋容材料层的厚度为10-200μm。
  15. 根据权利要求5所述的电路板，其特征在于，所述电路板还包括：
    介质层，设置在所述芯片与所述槽体的侧壁之间；
    其中，所述介质层为树脂、molding硅胶中的一种或任意组合。
  16. 根据权利要求15所述的电路板，其特征在于，
    所述芯片与所述槽体的侧壁之间的距离为20-200μm。
  17. 一种电路板的制作方法，其特征在于，包括：
    提供一芯板层，其中，所述芯板层包括芯板以及至少一个芯片，所述芯板上开设有至少一个槽体，所述芯片设置在相应的所述槽体中；
    在所述芯板层上设置间隔绝缘层；
    在所述间隔绝缘层远离所述芯板层的一侧设置埋容材料层；
    在所述埋容材料层远离所述间隔绝缘层的一侧设置第一功能层；
    在所述芯板层远离所述间隔绝缘层的一侧设置第二功能层；
    压合所述第一功能层和所述第二功能层，以得到所述电路板。
  18. 根据权利要求17所述的方法，其特征在于，所述方法还包括：
    提供一铜箔，具有相对设置的第三表面和第四表面；
    在所述第三表面上设置第一电极层；
    在所述第四表面上设置第二电极层；
    压合所述第一电极层和所述第二电极层，以得到所述埋容材料层。
  19. 根据权利要求17所述的方法，其特征在于，提供一芯板层包括：
    提供一芯板，具有相对设置的第一表面和第二表面；
    在所述芯板上开设至少一个所述槽体；
    将至少一个所述芯片放置在相应的所述槽体中；
    在所述第一表面上依次交替层叠设置第一绝缘子层和第一线路子层；
    在所述第二表面上依次交替层叠设置第二绝缘子层和第二线路子层；
    压合所述第一线路子层和所述第二线路子层，以得到所述芯板层。
  20. 根据权利要求17所述的方法，其特征在于，所述在所述埋容材料层远离所述间隔绝缘层的一侧设置第一功能层的步骤包括：在所述埋容材料层远离所述间隔绝缘层的一侧上依次交替层叠设置第一绝缘层和第一线路层；
    所述在所述芯板层远离所述间隔绝缘层的一侧设置第二功能层的步骤包括：在所述芯板层远离所述间隔绝缘层的一侧上依次交替层叠设 置第二线路层和第二绝缘层；
    所述方法还包括：
    在所述芯板、所述间隔绝缘层、所述第一绝缘子层、所述第二绝缘子层、所述第一绝缘层以及所述第二绝缘层上形成用于层间连接的导电孔；
    其中，所述芯片的连接端子通过所述导电孔以及所述第一线路子层与所述埋容材料层电连接；
    所述第一线路层通过所述导电孔与所述第一线路子层、所述第二线路子层以及所述第二线路层电连接。
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