US20100018761A1 - Embedded chip substrate and fabrication method thereof - Google Patents

Embedded chip substrate and fabrication method thereof Download PDF

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Publication number
US20100018761A1
US20100018761A1 US12/500,841 US50084109A US2010018761A1 US 20100018761 A1 US20100018761 A1 US 20100018761A1 US 50084109 A US50084109 A US 50084109A US 2010018761 A1 US2010018761 A1 US 2010018761A1
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United States
Prior art keywords
layer
insulation layer
chip
side wall
insulation
Prior art date
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Abandoned
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US12/500,841
Inventor
Yung-Hui Wang
Ying-Te Ou
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC. reassignment ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OU, YING-TE, WANG, YUNG-HUI
Publication of US20100018761A1 publication Critical patent/US20100018761A1/en
Priority to US13/564,421 priority Critical patent/US9253887B2/en
Assigned to BOAT EAGLE S.R.L. reassignment BOAT EAGLE S.R.L. CHANGE OF ADDRESS OF ASSIGNEE Assignors: BOAT EAGLE S.R.L.
Priority to US14/990,425 priority patent/US9768103B2/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention generally relates to a substrate and a fabrication method thereof. More particularly, the present invention relates to an embedded chip substrate and a fabrication method thereof.
  • a circuit board is often disposed for carrying various electronic elements.
  • the electronic elements occupy the carrying area on the circuit board.
  • the carrying area on the circuit board is required to be extended.
  • the area occupied by the circuit board is inevitably increased as well, which deteriorates miniaturization of the electronic products.
  • the circuit boards used in chip packages also encounter the similar issue.
  • the present invention is directed to an embedded chip substrate in which a chip does not occupy a carrying area of a circuit board.
  • the present invention further provides a fabrication method of an embedded chip substrate.
  • a chip in the embedded chip substrate formed by conducting said fabrication method does not occupy a carrying area of a circuit board.
  • an embedded chip substrate including a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer.
  • the core layer is disposed on the first insulation layer and has an opening that exposes a portion of the first insulation layer.
  • the chip is adhered into a recess formed by the opening and the first insulation layer.
  • the second insulation layer is disposed on the core layer for covering the chip.
  • the first circuit layer is disposed at the outer side of the first insulation layer, and the first insulation layer is located between the first circuit layer and the core layer.
  • the second circuit layer is disposed at the outer side of the second insulation layer, and the second insulation layer is located between the second circuit layer and the core layer.
  • the first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.
  • a material of the first insulation layer includes a two-stage curable compound.
  • the embedded chip substrate further includes a side wall adhesion layer that is disposed between the inner side wall of the recess and the side wall of the chip.
  • the embedded chip substrate further includes a side wall adhesion layer that is disposed between the inner side wall of the recess and the side wall of the chip.
  • the first insulation layer is extended between the inner side wall of the recess and the side wall of the chip.
  • the embedded chip substrate further includes a plurality of conductive blind vias penetrating the second insulation layer and electrically connected to the second circuit layer and the chip.
  • the embedded chip substrate further includes a plurality of conductive through holes penetrating the second insulation layer, the core layer, and the first insulation layer and electrically connected to the first circuit layer and the second circuit layer.
  • the core layer further includes a core dielectric layer and two core circuit layers.
  • the two core circuit layers are respectively disposed at opposite sides of the core layer.
  • the embedded chip substrate further includes two build-up structures respectively disposed at the outer side of the second insulation layer and the outer side of the first insulation layer, and a plurality of solder pads are respectively located at the outer sides of the two build-up structures.
  • the embedded chip substrate further includes two solder mask layers respectively disposed at the outer sides of the build-up structures and respectively exposing the corresponding solder pads.
  • a fabrication method of an embedded chip substrate is further provided hereinafter.
  • a core layer that has an opening is provided.
  • a first insulation layer and a first conductive layer are provided.
  • the first conductive layer is disposed on the first insulation layer.
  • the core layer is then disposed on the first insulation layer that is located between the core layer and the first conductive layer.
  • a chip is adhered into a recess formed by the opening and the first insulation layer.
  • a second insulation layer and a second conductive layer are provided.
  • the second conductive layer is disposed on the second insulation layer.
  • the second insulation layer is then disposed on the core layer.
  • the second insulation layer is located between the core layer and the second conductive layer and covers the recess.
  • the first conductive layer, the first insulation layer, the core layer, the second insulation layer, and the second conductive layer are laminated.
  • the first conductive layer and the second conductive layer are respectively patterned, so as to form a first circuit layer and a second circuit layer.
  • the first circuit layer is electrically connected to the second circuit layer, and the second circuit layer is electrically connected to the chip.
  • the fabrication method of the embedded chip substrate further includes forming a plurality of conductive blind vias penetrating the second insulation layer before the first conductive layer is patterned, such that the chip is electrically connected to the second conductive layer.
  • the fabrication method of the embedded chip substrate further includes forming a plurality of conductive through holes penetrating the second insulation layer, the core layer, and the first insulation layer after the first conductive layer and the second conductive layer are patterned, such that the first circuit layer is electrically connected to the second circuit layer.
  • the fabrication method of the embedded chip substrate further includes heating the first insulation layer in the step of laminating the first conductive layer, the first insulation layer, the core layer, the second insulation layer, and the second conductive layer, such that the first insulation layer overflows between the side wall of the chip and the inner side wall of the recess.
  • a method of adhering the chip into the recess includes disposing a bottom adhesion layer on the first insulation layer that is located in the recess and disposing the chip on the bottom adhesion layer.
  • the method of adhering the chip into the recess further includes forming a side wall adhesion layer between the inner side wall of the recess and the side wall of the chip.
  • the fabrication method of the embedded chip substrate further includes respectively forming a build-up structure at the outer side of the first insulation layer and the outer side of the second insulation layer.
  • a plurality of solder pads are located at the outer sides of the two build-up structures, respectively.
  • FIGS. 1A through 1L are schematic cross-sectional flowcharts illustrating a process of manufacturing an embedded chip substrate according to an embodiment of the present invention.
  • FIGS. 2A and 2B are schematic cross-sectional flowcharts illustrating a process of manufacturing an embedded chip substrate according to another embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional flowchart illustrating a process of manufacturing an embedded chip substrate according to still another embodiment of the present invention.
  • FIGS. 1A through 1L are schematic cross-sectional flowcharts illustrating a process of manufacturing an embedded chip substrate according to an embodiment of the present invention.
  • FIGS. 2A and 2B are schematic cross-sectional flowcharts illustrating a process of manufacturing an embedded chip substrate according to another embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional flowchart illustrating a process of manufacturing an embedded chip substrate according to still another embodiment of the present invention.
  • the core layer 10 includes a core dielectric layer 12 and two conductive layers 14 that are disposed at opposite sides of the core dielectric layer 12 , respectively.
  • the core dielectric layer 12 can be an insulation board. Additionally, in other embodiments that are not depicted in the drawings, a multi-layered board can serve as a substitute for the core dielectric layer 12 of the present embodiment.
  • the multi-layered board can be composed of multiple circuit layers and multiple insulation layers alternately arranged.
  • a method of forming the opening 16 includes performing a routing process, such as a mechanical drilling process, a punching process, or any other appropriate routing processes.
  • a material of the bottom adhesion layer 142 is, for example, polyimide (PI), or any other appropriate adhesive materials.
  • a material of the side wall adhesion layer 144 is, for example, epoxy resin, or any other appropriate adhesive materials.
  • a second insulation layer 150 and a second conductive layer 160 are provided.
  • the second conductive layer 160 is disposed on the second insulation layer 150 .
  • the RCC can be used to form the second insulation layer 150 and the second conductive layer 160 .
  • the second insulation layer 150 is then disposed on the core layer 10 .
  • the second insulation layer 150 is located between the core layer 10 and the second conductive layer 160 and covers the recess R.
  • the first conductive layer 120 , the first insulation layer 110 , the core layer 10 , the second insulation layer 150 , and the second conductive layer 160 are laminated.
  • the first insulation layer 110 can be heated during the lamination. Since the first insulation layer 110 can be made of the two-stage curable compound, a portion of the first insulation layer 110 overflows between the side wall of the chip 130 and the inner side wall of the recess R.
  • a material of the second insulation layer 150 can also include the two-stage curable compound, which is conducive to filling up the space between the side wall of the chip 130 and the inner side wall of the recess R.
  • the lamination of the first conductive layer 120 , the first insulation layer 110 , the core layer 10 , the second insulation layer 150 , and the second conductive layer 160 and the heating of the first insulation layer 110 allow the space between the side wall of the chip 130 and the inner side wall of the recess R to be filled with a portion of the first insulation layer 110 (as shown in FIG. 2B ). As such, it is not necessary to fill the space between the side wall of the chip 130 and the inner side wall of the recess R with other fillers for preventing the occurrence of the popcorn effect.
  • a plurality of conductive blind vias B penetrating the second insulation layer 150 are formed in the present embodiment, so as to electrically connect the chip 130 to the second conductive layer 160 .
  • the first conductive layer 120 and the second conductive layer 160 are respectively patterned, so as to form a first circuit layer 122 and a second circuit layer 162 .
  • a plurality of conductive through holes T penetrating the second insulation layer 150 , the core layer 10 , and the first insulation layer 110 are then formed in the present embodiment, so as to electrically connect the first circuit layer 122 to the second circuit layer 162 .
  • a build-up structure 170 can be further formed at the outer side of the first insulation layer 110 and the outer side of the second insulation layer 150 , respectively.
  • a plurality of solder pads 172 are respectively disposed at the outer sides of the build-up structures 170 .
  • a solder mask layer 180 is formed on the build-up structures 170 , respectively, so as to expose the corresponding solder pads 172 .
  • an electrical connection layer 190 can then be formed on the solder pads 172 .
  • the electrical connection layer 190 is, for example, a Ni/Au composite layer.
  • FIGS. 4 and 5 are schematic cross-sectional views illustrating two modifications of the embedded chip substrate depicted in FIG. 1L .
  • an embedded chip substrate 200 of the present embodiment includes a first insulation layer 110 , a core layer 10 , a chip 130 , a second insulation layer 150 , a first circuit layer 122 , and a second circuit layer 162 .
  • the first insulation layer 110 is made of a two-stage curable compound, for example.
  • the core layer 10 is disposed on the first insulation layer 110 and has an opening 16 that exposes a portion of the first insulation layer 110 .
  • the opening 16 and the first insulation layer 110 together form a recess R where the chip 130 is adhered.
  • a bottom adhesion layer 142 is disposed between the chip 130 and the first insulation layer 110
  • a side wall adhesion layer 144 is disposed between the inner side wall of the recess R and the side wall of the chip 130 , so as to adhere the chip 130 into the recess R.
  • the chip 130 can be adhered into the recess R only by means of the bottom adhesion layer 142 .
  • the first insulation layer 110 can be extended into the space between the inner side wall of the recess R and the side wall of the chip 130 , and therefore it is not necessary to fill the space with other fillers for preventing the occurrence of the popcorn effect.
  • the material of the second insulation layer 150 can also include the two-stage curable compound, and thus the second insulation layer 150 can also be extended into the space between the inner side wall of the recess R and the side wall of the chip 130 (not shown).
  • the chip 130 can be adhered into the recess R only by means of the side wall adhesion layer 144 .
  • the second insulation layer 150 is disposed on the core layer 10 for covering the chip 130 .
  • the material of the second insulation layer 150 can include the two-stage curable compound.
  • the first circuit layer 122 is disposed at the outer side of the first insulation layer 110 , and the first insulation layer 110 is located between the first circuit layer 122 and the core layer 10 .
  • the second circuit layer 162 is disposed at the outer side of the second insulation layer 150 , and the second insulation layer 150 is located between the second circuit layer 162 and the core layer 10 .
  • the first circuit layer 122 and the second circuit layer 162 can be electrically connected to each other through a plurality of conductive through holes T penetrating the second insulation layer 150 , the core layer 10 , and the first insulation layer 110 .
  • the second circuit layer 162 and the chip 130 can be electrically connected to each other through a plurality of conductive blind vias B penetrating the second insulation layer 150 .
  • a build-up process can be performed at the outer side of the second insulation layer 150 and the outer side of the first insulation layer 110 based on actual demands.
  • a build-up structure 170 is formed respectively at the outer side of the second insulation layer 150 and the outer side of the first insulation layer 110 , and a plurality of solder pads 172 are formed at the outer side of each of the built-up structures 170 .
  • a solder mask layer 180 is formed respectively at the outer sides of the two build-up structures 170 in the present embodiment, and each of the solder mask layers 180 exposes the corresponding solder pads 172 .
  • an electrical connection layer 190 can be further formed on each of the solder pads 172 .
  • the electrical connection layer 190 is, for example, a Ni/Au composite layer.
  • the chip is embedded into the circuit board according to the present invention, and therefore the chip does not occupy the carrying area on the circuit board.
  • the first insulation layer can be made of the two-stage curable compound.
  • the first insulation layer can be heated, such that the first insulation layer overflows between the side wall of the chip and the inner side wall of the recess. Thereby, no air or moisture would exist between the side wall of the chip and the inner side wall of the recess, so as to prevent the occurrence of the popcorn effect.

Abstract

An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority benefit of Taiwan application serial no. 97127864, filed on Jul. 22, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to a substrate and a fabrication method thereof. More particularly, the present invention relates to an embedded chip substrate and a fabrication method thereof.
  • 2. Description of Related Art
  • With recent progress of electronic technologies, electronic products that are more user-friendly and with better functions are continuously developed. Further, these products are designed to satisfy requirements for lightness, slimness, shortness, and compactness. In a housing of the electronic product, a circuit board is often disposed for carrying various electronic elements. The electronic elements occupy the carrying area on the circuit board. Hence, when the number of the electronic elements increases, the carrying area on the circuit board is required to be extended. As such, the area occupied by the circuit board is inevitably increased as well, which deteriorates miniaturization of the electronic products. In addition, the circuit boards used in chip packages also encounter the similar issue.
    • SUMMARY OF THE INVENTION
  • The present invention is directed to an embedded chip substrate in which a chip does not occupy a carrying area of a circuit board.
  • The present invention further provides a fabrication method of an embedded chip substrate. A chip in the embedded chip substrate formed by conducting said fabrication method does not occupy a carrying area of a circuit board.
  • In the present invention, an embedded chip substrate including a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer is provided. The core layer is disposed on the first insulation layer and has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess formed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer, and the first insulation layer is located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer, and the second insulation layer is located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.
  • In an embodiment of the present invention, a material of the first insulation layer includes a two-stage curable compound.
  • In an embodiment of the present invention, a material of the second insulation layer includes a two-stage curable compound.
  • In an embodiment of the present invention, the embedded chip substrate further includes a bottom adhesion layer that is disposed on the first insulation layer in the recess and located between the chip and the first insulation layer.
  • In an embodiment of the present invention, the embedded chip substrate further includes a side wall adhesion layer that is disposed between the inner side wall of the recess and the side wall of the chip.
  • In an embodiment of the present invention, the embedded chip substrate further includes a side wall adhesion layer that is disposed between the inner side wall of the recess and the side wall of the chip.
  • In an embodiment of the present invention, the first insulation layer is extended between the inner side wall of the recess and the side wall of the chip.
  • In an embodiment of the present invention, the embedded chip substrate further includes a plurality of conductive blind vias penetrating the second insulation layer and electrically connected to the second circuit layer and the chip.
  • In an embodiment of the present invention, the embedded chip substrate further includes a plurality of conductive through holes penetrating the second insulation layer, the core layer, and the first insulation layer and electrically connected to the first circuit layer and the second circuit layer.
  • In an embodiment of the present invention, the core layer further includes a core dielectric layer and two core circuit layers. The two core circuit layers are respectively disposed at opposite sides of the core layer.
  • In an embodiment of the present invention, the embedded chip substrate further includes two build-up structures respectively disposed at the outer side of the second insulation layer and the outer side of the first insulation layer, and a plurality of solder pads are respectively located at the outer sides of the two build-up structures.
  • In an embodiment of the present invention, the embedded chip substrate further includes two solder mask layers respectively disposed at the outer sides of the build-up structures and respectively exposing the corresponding solder pads.
  • In the present invention, a fabrication method of an embedded chip substrate is further provided hereinafter. First, a core layer that has an opening is provided. Next, a first insulation layer and a first conductive layer are provided. The first conductive layer is disposed on the first insulation layer. The core layer is then disposed on the first insulation layer that is located between the core layer and the first conductive layer. After that, a chip is adhered into a recess formed by the opening and the first insulation layer. Thereafter, a second insulation layer and a second conductive layer are provided. The second conductive layer is disposed on the second insulation layer. The second insulation layer is then disposed on the core layer. The second insulation layer is located between the core layer and the second conductive layer and covers the recess. Afterwards, the first conductive layer, the first insulation layer, the core layer, the second insulation layer, and the second conductive layer are laminated. Next, the first conductive layer and the second conductive layer are respectively patterned, so as to form a first circuit layer and a second circuit layer. The first circuit layer is electrically connected to the second circuit layer, and the second circuit layer is electrically connected to the chip.
  • In an embodiment of the present invention, the fabrication method of the embedded chip substrate further includes forming a plurality of conductive blind vias penetrating the second insulation layer before the first conductive layer is patterned, such that the chip is electrically connected to the second conductive layer.
  • In an embodiment of the present invention, the fabrication method of the embedded chip substrate further includes forming a plurality of conductive through holes penetrating the second insulation layer, the core layer, and the first insulation layer after the first conductive layer and the second conductive layer are patterned, such that the first circuit layer is electrically connected to the second circuit layer.
  • In an embodiment of the present invention, the fabrication method of the embedded chip substrate further includes heating the first insulation layer in the step of laminating the first conductive layer, the first insulation layer, the core layer, the second insulation layer, and the second conductive layer, such that the first insulation layer overflows between the side wall of the chip and the inner side wall of the recess.
  • In an embodiment of the present invention, a method of adhering the chip into the recess includes disposing a bottom adhesion layer on the first insulation layer that is located in the recess and disposing the chip on the bottom adhesion layer.
  • In an embodiment of the present invention, the method of adhering the chip into the recess further includes forming a side wall adhesion layer between the inner side wall of the recess and the side wall of the chip.
  • In an embodiment of the present invention, a method of adhering the chip into the recess includes forming a side wall adhesion layer between the inner side wall of the recess and the side wall of the chip.
  • In an embodiment of the present invention, the fabrication method of the embedded chip substrate further includes respectively forming a build-up structure at the outer side of the first insulation layer and the outer side of the second insulation layer. A plurality of solder pads are located at the outer sides of the two build-up structures, respectively.
  • In light of the foregoing, the chip is embedded into the circuit board according to the present invention, and therefore the chip does not occupy the carrying area of the circuit board.
  • In order to make the above and other features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings constituting a part of this specification are incorporated herein to provide a farther understanding of the invention. Here, the drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIGS. 1A through 1L are schematic cross-sectional flowcharts illustrating a process of manufacturing an embedded chip substrate according to an embodiment of the present invention.
  • FIGS. 2A and 2B are schematic cross-sectional flowcharts illustrating a process of manufacturing an embedded chip substrate according to another embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional flowchart illustrating a process of manufacturing an embedded chip substrate according to still another embodiment of the present invention.
  • FIGS. 4 and 5 are schematic cross-sectional views illustrating two modifications of the embedded chip substrate depicted in FIG. 1L.
    •  DESCRIPTION OF EMBODIMENTS
  • FIGS. 1A through 1L are schematic cross-sectional flowcharts illustrating a process of manufacturing an embedded chip substrate according to an embodiment of the present invention. FIGS. 2A and 2B are schematic cross-sectional flowcharts illustrating a process of manufacturing an embedded chip substrate according to another embodiment of the present invention. FIG. 3 is a schematic cross-sectional flowchart illustrating a process of manufacturing an embedded chip substrate according to still another embodiment of the present invention.
  • First, referring to FIG. 1A, a core layer 10 is provided. The core layer 10 includes a core dielectric layer 12 and two conductive layers 14 that are disposed at opposite sides of the core dielectric layer 12, respectively. The core dielectric layer 12 can be an insulation board. Additionally, in other embodiments that are not depicted in the drawings, a multi-layered board can serve as a substitute for the core dielectric layer 12 of the present embodiment. The multi-layered board can be composed of multiple circuit layers and multiple insulation layers alternately arranged.
  • Next, referring to FIG. 1B, the two conductive layers 14 are patterned, respectively, so as to form two core circuit layers 14 a. After that, referring to FIG. 1C, an opening 16 is formed on the core layer 10. Here, a method of forming the opening 16 includes performing a routing process, such as a mechanical drilling process, a punching process, or any other appropriate routing processes.
  • Thereafter, referring to FIG. 1D, a first insulation layer 110 and a first conductive layer 120 are provided. The first conductive layer 120 is disposed on the first insulation layer 110, and a material of the first insulation layer 110 is, for example, a two-state curable compound. In the present embodiment, a resin coated copper (RCC) can be used to form the first insulation layer 110 and the first conductive layer 120. After that, the core layer 10 is disposed on the first insulation layer 110, and the first insulation layer 110 is located between the core layer 10 and the first conductive layer 120. Besides, the opening 16 and the first insulation layer 110 together form a recess R.
  • Afterwards, referring to FIG. 1E, a chip 130 is adhered into the recess R. In the present embodiment, the chip 130 is adhered into the recess R by disposing a bottom adhesion layer 142 on the first insulation layer 110, so as to adhere the chip 130 onto the first insulation layer 110. Additionally, a side wall adhesion layer 144 is formed between the inner side wall of the recess R and the side wall of the chip 130, so as to adhere the chip 130 to the inner side wall of the recess R. Besides, in other embodiments, the chip 130 can also be adhered into the recess R only by means of the bottom adhesion layer 142 (as shown in FIG. 2A) or the side wall adhesion layer 144 (as shown in FIG. 3).
  • A material of the bottom adhesion layer 142 is, for example, polyimide (PI), or any other appropriate adhesive materials. By contrast, a material of the side wall adhesion layer 144 is, for example, epoxy resin, or any other appropriate adhesive materials.
  • Next, referring to FIG. 1F, a second insulation layer 150 and a second conductive layer 160 are provided. The second conductive layer 160 is disposed on the second insulation layer 150. In the present embodiment, the RCC can be used to form the second insulation layer 150 and the second conductive layer 160. The second insulation layer 150 is then disposed on the core layer 10. Here, the second insulation layer 150 is located between the core layer 10 and the second conductive layer 160 and covers the recess R.
  • After that, referring to FIG. 1G, the first conductive layer 120, the first insulation layer 110, the core layer 10, the second insulation layer 150, and the second conductive layer 160 are laminated. Besides, the first insulation layer 110 can be heated during the lamination. Since the first insulation layer 110 can be made of the two-stage curable compound, a portion of the first insulation layer 110 overflows between the side wall of the chip 130 and the inner side wall of the recess R.
  • Thereby, no air or moisture would exist between the side wall of the chip 130 and the inner side wall of the recess R, such that an occurrence of a popcorn effect can be avoided. Moreover, a material of the second insulation layer 150 can also include the two-stage curable compound, which is conducive to filling up the space between the side wall of the chip 130 and the inner side wall of the recess R.
  • According to other embodiments, when the chip 130 is adhered into the recess R only by means of the bottom adhesion layer 142 (as shown in FIG. 2A), the lamination of the first conductive layer 120, the first insulation layer 110, the core layer 10, the second insulation layer 150, and the second conductive layer 160 and the heating of the first insulation layer 110 allow the space between the side wall of the chip 130 and the inner side wall of the recess R to be filled with a portion of the first insulation layer 110 (as shown in FIG. 2B). As such, it is not necessary to fill the space between the side wall of the chip 130 and the inner side wall of the recess R with other fillers for preventing the occurrence of the popcorn effect.
  • After that, referring to FIG. 1H, a plurality of conductive blind vias B penetrating the second insulation layer 150 are formed in the present embodiment, so as to electrically connect the chip 130 to the second conductive layer 160. Next, referring to FIG. 11, the first conductive layer 120 and the second conductive layer 160 are respectively patterned, so as to form a first circuit layer 122 and a second circuit layer 162.
  • Referring to FIG. 1J, a plurality of conductive through holes T penetrating the second insulation layer 150, the core layer 10, and the first insulation layer 110 are then formed in the present embodiment, so as to electrically connect the first circuit layer 122 to the second circuit layer 162.
  • Thereafter, referring to FIG. 1K, in the present embodiment, a build-up structure 170 can be further formed at the outer side of the first insulation layer 110 and the outer side of the second insulation layer 150, respectively. A plurality of solder pads 172 are respectively disposed at the outer sides of the build-up structures 170. Next, referring to FIG. 1L, a solder mask layer 180 is formed on the build-up structures 170, respectively, so as to expose the corresponding solder pads 172. To avoid the surfaces of the solder pads 172 from being oxidized, an electrical connection layer 190 can then be formed on the solder pads 172. Here, the electrical connection layer 190 is, for example, a Ni/Au composite layer.
  • The structure of the embedded chip substrate in FIG. 1L is elaborated hereinafter.
  • FIGS. 4 and 5 are schematic cross-sectional views illustrating two modifications of the embedded chip substrate depicted in FIG. 1L.
  • As shown in FIG. 1L, an embedded chip substrate 200 of the present embodiment includes a first insulation layer 110, a core layer 10, a chip 130, a second insulation layer 150, a first circuit layer 122, and a second circuit layer 162. The first insulation layer 110 is made of a two-stage curable compound, for example.
  • The core layer 10 is disposed on the first insulation layer 110 and has an opening 16 that exposes a portion of the first insulation layer 110. The opening 16 and the first insulation layer 110 together form a recess R where the chip 130 is adhered. In the present embodiment, a bottom adhesion layer 142 is disposed between the chip 130 and the first insulation layer 110, and a side wall adhesion layer 144 is disposed between the inner side wall of the recess R and the side wall of the chip 130, so as to adhere the chip 130 into the recess R.
  • Besides, referring to FIG. 4, in other embodiments, the chip 130 can be adhered into the recess R only by means of the bottom adhesion layer 142. Note that the first insulation layer 110 can be extended into the space between the inner side wall of the recess R and the side wall of the chip 130, and therefore it is not necessary to fill the space with other fillers for preventing the occurrence of the popcorn effect. Moreover, the material of the second insulation layer 150 can also include the two-stage curable compound, and thus the second insulation layer 150 can also be extended into the space between the inner side wall of the recess R and the side wall of the chip 130 (not shown). Besides, referring to FIG. 5, in other embodiments, the chip 130 can be adhered into the recess R only by means of the side wall adhesion layer 144.
  • As shown in FIG. 1L, the second insulation layer 150 is disposed on the core layer 10 for covering the chip 130. In addition, the material of the second insulation layer 150 can include the two-stage curable compound. The first circuit layer 122 is disposed at the outer side of the first insulation layer 110, and the first insulation layer 110 is located between the first circuit layer 122 and the core layer 10. The second circuit layer 162 is disposed at the outer side of the second insulation layer 150, and the second insulation layer 150 is located between the second circuit layer 162 and the core layer 10.
  • In the present embodiment, the first circuit layer 122 and the second circuit layer 162 can be electrically connected to each other through a plurality of conductive through holes T penetrating the second insulation layer 150, the core layer 10, and the first insulation layer 110. The second circuit layer 162 and the chip 130 can be electrically connected to each other through a plurality of conductive blind vias B penetrating the second insulation layer 150.
  • Additionally, in the present embodiment, a build-up process can be performed at the outer side of the second insulation layer 150 and the outer side of the first insulation layer 110 based on actual demands. According to the present embodiment, a build-up structure 170 is formed respectively at the outer side of the second insulation layer 150 and the outer side of the first insulation layer 110, and a plurality of solder pads 172 are formed at the outer side of each of the built-up structures 170. Moreover, a solder mask layer 180 is formed respectively at the outer sides of the two build-up structures 170 in the present embodiment, and each of the solder mask layers 180 exposes the corresponding solder pads 172.
  • To avoid the surfaces of the solder pads 172 from being oxidized, an electrical connection layer 190 can be further formed on each of the solder pads 172. Here, the electrical connection layer 190 is, for example, a Ni/Au composite layer.
  • Based on the above, the chip is embedded into the circuit board according to the present invention, and therefore the chip does not occupy the carrying area on the circuit board. Further, in the aforesaid embodiments, the first insulation layer can be made of the two-stage curable compound. Thus, when the first conductive layer, the first insulation layer, the core layer, the second insulation layer, and the second conductive layer are laminated, the first insulation layer can be heated, such that the first insulation layer overflows between the side wall of the chip and the inner side wall of the recess. Thereby, no air or moisture would exist between the side wall of the chip and the inner side wall of the recess, so as to prevent the occurrence of the popcorn effect.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (20)

1. An embedded chip substrate, comprising:
a first insulation layer;
a core layer, disposed on the first insulation layer and having an opening for exposing a portion of the first insulation layer;
a chip, adhered into a recess formed by the opening and the first insulation layer;
a second insulation layer, disposed on the core layer for covering the chip;
a first circuit layer, disposed at the outer side of the first insulation layer, the first insulation layer being disposed between the first circuit layer and the core layer; and
a second circuit layer, disposed at the outer side of the second insulation layer, wherein the second insulation layer is located between the second circuit layer and the core layer, the first circuit layer is electrically connected to the second circuit layer, and the second circuit layer is electrically connected to the chip.
2. The embedded chip substrate as claimed in claim 1, wherein a material of the first insulation layer comprises a two-stage curable compound.
3. The embedded chip substrate as claimed in claim 1, wherein a material of the second insulation layer comprises a two-stage curable compound.
4. The embedded chip substrate as claimed in claim 1, further comprising:
a bottom adhesion layer, disposed on the first insulation layer in the recess and located between the chip and the first insulation layer.
5. The embedded chip substrate as claimed in claim 4, further comprising:
a side wall adhesion layer, disposed between the inner side wall of the recess and the side wall of the chip.
6. The embedded chip substrate as claimed in claim 1, further comprising:
a side wall adhesion layer, disposed between the inner side wall of the recess and the side wall of the chip.
7. The embedded chip substrate as claimed in claim 1, wherein the first insulation layer is extended between the inner side wall of the recess and the side wall of the chip.
8. The embedded chip substrate as claimed in claim 1, further comprising:
a plurality of conductive blind vias, penetrating the second insulation layer and electrically connected to the second circuit layer and the chip.
9. The embedded chip substrate as claimed in claim 1, further comprising:
a plurality of conductive through holes, penetrating the second insulation layer, the core layer, and the first insulation layer and electrically connected to the first circuit layer and the second circuit layer.
10. The embedded chip substrate as claimed in claim 1, wherein the core layer comprises:
a core dielectric layer; and
two core circuit layers, respectively disposed at opposite sides of the core layer.
11. The embedded chip substrate as claimed in claim 1, further comprising:
two build-up structures, respectively disposed at the outer side of the second insulation layer and the outer side of the first insulation layer, a plurality of solder pads being located at the outer sides of the two build-up structures, respectively.
12. The embedded chip substrate as claimed in claim 11, further comprising:
two solder mask layers, respectively disposed at the outer sides of the build-up structures and respectively exposing the corresponding solder pads.
13. A fabrication method of an embedded chip substrate, the fabrication method comprising: providing a core layer that has an opening;
providing a first insulation layer and a first conductive layer, the first conductive layer being disposed on the first insulation layer;
disposing the core layer on the first insulation layer, the first insulation layer being located between the core layer and the first conductive layer;
adhering a chip into a recess formed by the opening and the first insulation layer;
providing a second insulation layer and a second conductive layer, the second conductive layer being disposed on the second insulation layer;
disposing the second insulation layer on the core layer, the second insulation layer being located between the core layer and the second conductive layer and covering the recess;
laminating the first conductive layer, the first insulation layer, the core layer, the second insulation layer, and the second conductive layer; and
respectively patterning the first conductive layer and the second conductive layer, so as to form a first circuit layer and a second circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer, and the second circuit layer is electrically connected to the chip.
14. The fabrication method of the embedded chip substrate as claimed in claim 13, further comprising:
forming a plurality of conductive blind vias penetrating the second insulation layer before the first conductive layer is patterned, such that the chip is electrically connected to the second conductive layer.
15. The fabrication method of the embedded chip substrate as claimed in claim 13, further comprising:
forming a plurality of conductive through holes penetrating the second insulation layer, the core layer, and the first insulation layer after the first conductive layer and the second conductive layer are patterned, such that the first circuit layer is electrically connected to the second circuit layer.
16. The fabrication method of the embedded chip substrate as claimed in claim 13, further comprising:
heating the first insulation layer in the step of laminating the first conductive layer, the first insulation layer, the core layer, the second insulation layer, and the second conductive layer, such that the first insulation layer overflows between the side wall of the chip and the inner side wall of the recess.
17. The fabrication method of the embedded chip substrate as claimed in claim 13, wherein a method of adhering the chip into the recess comprises:
disposing a bottom adhesion layer on the first insulation layer that is located in the recess; and
disposing the chip on the bottom adhesion layer.
18. The fabrication method of the embedded chip substrate as claimed in claim 17, wherein the method of adhering the chip into the recess further comprises:
forming a side wall adhesion layer between the inner side wall of the recess and the side wall of the chip.
19. The fabrication method of the embedded chip substrate as claimed in claim 13, wherein a method of adhering the chip into the recess comprises:
forming a side wall adhesion layer between the inner side wall of the recess and the side wall of the chip.
20. The fabrication method of the embedded chip substrate as claimed in claim 13, further comprising:
respectively forming a build-up structure at the outer side of the first insulation layer and the outer side of the second insulation layer, a plurality of solder pads being located at the outer sides of the two build-up structures, respectively.
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US20120295403A1 (en) 2012-11-22
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US9253887B2 (en) 2016-02-02
TW201005892A (en) 2010-02-01

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