TWI513379B - 內埋元件的基板結構與其製造方法 - Google Patents
內埋元件的基板結構與其製造方法 Download PDFInfo
- Publication number
- TWI513379B TWI513379B TW103122800A TW103122800A TWI513379B TW I513379 B TWI513379 B TW I513379B TW 103122800 A TW103122800 A TW 103122800A TW 103122800 A TW103122800 A TW 103122800A TW I513379 B TWI513379 B TW I513379B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- substrate
- forming
- component
- electronic component
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10181—Fuse
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/072—Electroless plating, e.g. finish plating or initial plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明有關一種半導體元件之製造方法,且特別是有關於一種內埋元件的基板結構與其製造方法。
在新一代的電子產品中,不斷追求更輕薄短小,更要求產品具有多功能與高性能,因此,積體電路(Integrated circuit,IC)必須在有限的空間中容納更多電子元件以達到高密度與微型化之要求。
因此,電子產業開發新穎的構裝技術,將電子元件埋入基板中,大幅縮小封裝體積,也縮短內埋電子元件與晶片的傳輸路徑。近年來發展出內埋元件電路板技術(embedded passive or integral substrate)。內埋元件電路板技術能提高電子元件效能,且能降低電子元件佔用的電路板面積,以大幅減少整體封裝尺寸。
然而,為了符合高密度的佈線需求,內埋元件電路板技術仍面臨許多挑戰。
本發明提供一種內埋元件的基板結構,包括:一基板,其中該基板具有一個或一個以上凹槽、一第一表面與一
第二表面;一個或一個以上電子元件,其中該電子元件形成於該凹槽中;以及一第一線路層,形成於該電子元件與該凹槽之間的空隙中,其中該第一線路層從該基板之第一表面延伸至該凹槽之側壁,且該第一線路層直接接觸該電子元件。
本發明另提供一種內埋元件的基板結構,包括:一基板,其中該基板具有一第一表面與一第二表面,且該基板具有一個或一個以上貫通孔(through hole)貫穿該基板;一個或一個以上電子元件,其中該電子元件形成於該貫通孔中;以及一第一線路層,形成於該於該電子元件與該凹槽之間的空隙中,其中該第一線路層從該基板之第一表面,沿著該凹槽之側壁延伸至該第二表面,且該第一線路層直接接觸該電子元件。
本發明亦提供一種內埋元件的基板結構之製造方法,包括以下步驟:提供一基板,其中該基板具有一第一表面與一第二表面;形成一個或一個以上凹槽於該基板之中;形成一個或一個以上電子元件於該凹槽之中;以及形成一第一線路層於該電子元件與該凹槽之間的空隙中,其中該第一線路層從該基板之第一表面延伸至該凹槽之側壁,且該第一線路層直接接觸該電子元件。
本發明又提供一種內埋元件的基板結構之製造方法,包括以下步驟:提供一基板,其中該基板具有一第一表面與一第二表面;形成一個或一個以上貫通孔(through hole)貫穿該基板;形成一個或一個以上電子元件於該貫通孔之中;以及形成一第一線路層於該電子元件與該凹槽之間的空隙中,其中該第一線路層從該基板之第一表面,沿著該凹槽之側壁延伸至
該第二表面,且該第一線路層直接接觸該電子元件。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
10‧‧‧電子元件
12‧‧‧金屬結構
14‧‧‧絕緣結構
102‧‧‧基板
102a‧‧‧第一表面
102b‧‧‧第二表面
104‧‧‧銅層
105‧‧‧凹槽
106‧‧‧黏著層
107‧‧‧貫通孔
114‧‧‧化學金屬層
124‧‧‧電鍍金屬層
125‧‧‧導電層
128‧‧‧油墨
135‧‧‧第一線路層
140‧‧‧絕緣層
142‧‧‧盲孔
145‧‧‧第二線路層
150‧‧‧保護層
155‧‧‧錫球
第1A~1L圖為一系列剖面圖,用以說明本發明第一實施例之內埋元件的基板結構之製造方法。
第2A~2I圖為一系列剖面圖,用以說明本發明第二實施例之內埋元件的基板結構之製造方法。
第3A-3H圖為一系列剖面圖,用以說明本發明第三實施例之內埋元件的基板結構之製造方法。
以下特舉出本發明之實施例,並配合所附圖式作詳細說明。以下實施例的元件和設計係為了簡化所揭露之發明,並非用以限定本發明。本發明於各個實施例中可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施例及/或所述結構之間的關係。此外,說明書中提及形成第一結構特徵位於第二結構特徵之上,其包括第一結構特徵與第二結構特徵是直接接觸的實施例,另外也包括於第一結構特徵與第二結構特徵之間另外有其他結構特徵的實施例,亦即,第一結構特徵與第二結構特徵並非直接接觸。
本發明提供一種內埋元件的基板結構與其製造方
法。第1A~1L圖為一系列剖面圖,用以顯示本發明第一實施例之內埋元件的基板結構之製造方法。請參見本案第1圖,首先提供一基板102,基板102之核心材質包括紙質酚醛樹脂(paper phenolic resin)、複合環氧樹脂(composite epoxy)、聚亞醯胺樹脂(polyimide resin)或玻璃纖維(glass fiber)或雙面含浸上述材料。基板102包括第一表面102a與第二表面102b,第一表面102a與第二表面102b之上具有銅層104。銅層104係利用習知之電鍍、壓合與塗佈的製程製備而得,接著利用影像轉移製程,即經由覆蓋光阻、曝光(exposure)、顯影(developing)、蝕刻(etching)和去膜(striping)的步驟,使基板100之上形成銅層104。
請參見第1B圖,形成凹槽105與貫通孔107於基板102之中。形成凹槽105的目的是為了將後續形成的電子元件10(請參見第1D圖)內埋於其中,以使整體封裝體積大幅縮小。在一些實施例中,形成凹槽105之方法包括物理性的金屬機械加工技術或化學性的蝕刻技術。凹槽105的尺寸視實際應用時電子元件10尺寸大小而定,一般而言,凹槽105的尺寸通常會略大於電子元件10,使電子元件10得以順利地固定與對準。
請再次參見第1B圖,貫通孔107貫穿基板102。形成貫通孔107之目的在於建立基板102上下兩面之導電通路,以利後續之雙面增層線路。在一些實施例中,形成貫通孔107的方法可利用數值控制工具機(numerical control,NC)鑽孔或其他鑽孔之技術。
請參見第1C圖,形成黏著層106於凹槽105之底部。黏著層106之目的在於固定後續形成之電子元件10。
請參見第1D圖,形成電子元件10於凹槽105之中,更確切地說,電子元件10係形成於黏著層106之上。電子元件10包括主動元件或被動元件。主動元件例如晶片(chip)。被動元件例如電阻器(resistor)、電容(capacitor)、電感(inductor)及/或保險絲(fuse)。
在一些實施例中,請參見第1D’圖,電子元件10為電容結構,此電容結構具有金屬結構12與絕緣結構14,金屬結構位於絕緣結構14之兩側。
請參見第1E圖,形成化學金屬層114於基板102之第一表面102a與第二表面102b上、凹槽105之底部與側壁上、以及形成於電子元件10之上表面與側壁上。
需注意的是,形成化學金屬層114之目的在於作為後續形成之電鍍金屬層124之晶種層,以利後續形成電鍍金屬層124(請參見第1E圖)。在一些實施例中,化學金屬層114之材料包括銅(Cu)、鋁(Al)、鎳(Ni)、金(Cu)、鈀(Pd)或上述之組合。
請參見第1F圖,順應性地形成電鍍金屬層124於化學金屬層114之上,其中化學金屬層114與電鍍金屬層兩者合稱為導電層125。在一些實施例中,電鍍金屬層124之材料包括銅(Cu)、鋁(Al)、鎳(Ni)、金(Cu)或上述之組合。在一些實施例中,化學金屬層114之材料為銅,且電鍍金屬層124之材料也為銅。
需注意的是,電鍍金屬層124填充凹槽105與電子元件10之間的空隙。在一些實施例中,相對於凹槽105與電子元件10之間的空隙,由於貫通孔107具有較大的孔徑,因此,電鍍金屬層124並無法完全將貫通孔107填滿。
請參見第iG圖,進行灌孔步驟,於貫通孔107之中填充油墨128。在一些實施例中,油墨128例如為樹脂油墨,利用烘烤步驟,以使油墨106硬化。此外,由於灌孔時,會有殘餘的油墨128露出,因此需進行一平整步驟,以去除殘餘油墨128,使用之平整方法例如為機械研磨法(mechanical polishing)。
請參見第1H圖,進行圖案化製程,以在基板102之第一表面102a與第二表面102b之上形成第一線路層135,其中第一線路層135直接接觸電子元件10。於一些實施例中,當電子元件10為電容結構時,第一線路層135直接電性接觸電容結構兩側的導電結構12(請參見第1D’圖)。
由於位於基板102之上的銅層104具有導電性,因此,為了簡化說明,本發明將銅層104與導電層125畫成同一層。圖案化製程包括以下步驟:曝光,以及顯影(development)、蝕刻(etching)和去膜(stripping)之步驟,即所謂的DES法。
請參見第1I圖,於圖案化製程之後,形成絕緣層140於第一線路層135之上。絕緣層140可為各種高分子材料,例如:環氧樹脂(expoxy resin)、聚亞醯胺(polyimide)、氰脂(cyanate ester)、雙順丁烯二酸醯亞胺(bismaleimide triazine)、或上述之組合;也可為高分子複合材料,例如高分子材料混合玻璃纖維、黏土或陶瓷等。
接著,請參見第1J圖,形成複數個盲孔142於絕緣層140之中,其中該些盲孔142暴露第一線路層135。在一些實施例中,可藉由雷射鑽孔(laser drilling method)形成該些盲孔
142。
請參見第1K圖,形成第二線路層145於該些盲孔142之中,以使第一線路層135電性連接至第二線路層145。
請參見第1L圖,形成保護層150於第二線路層145與絕緣層140之上。保護層150之作用在於保護內埋之線路,以避免線路氧化。於一些實施例中,保護層150由防焊材料所組成,例如綠漆。之後,可利用植球作業(ball implantation)形成複數個錫球155,以使電子元件10的訊號得以連接至外部裝置。
需注意的是,本發明電子元件10之側壁被第一線路層135所包圍,以將電子元件10的訊號向外傳輸。再者,藉由第一線路層135之設計,以增加電子元件10與第一線路層135之接觸面積,並提高佈線設計的彈性。
在一些實施例中,當電子元件為電容時,電容兩側的金屬結構12可直接電性連接第一線路層135,以增加接觸面積,提高佈線設計的彈性。
第2A~2I圖為一系列剖面圖,用以說明本發明第二實施例之內埋元件的基板結構之製造方法。於第2A-2I圖中的元件標號與第1A-1L圖相同者代表相同符號。
請參見第2A圖,基板102包括第一表面102a與第二表面102b,第一表面102a與第二表面102b之上具有銅層104。
請參見第2B圖,形成貫通孔107於基板102之中。形成貫通孔107的目的是為了將後續形成的電子元件10(請參見第2C圖)內埋於其中,以使整體封裝體積大幅縮小。
請參見第2C圖,形成黏著層106於貫通孔107之底
部。黏著層106之目的在於固定後續形成之電子元件10。電子元件10包括主動元件或被動元件。主動元件例如晶片(chip)。被動元件例如電阻器(resistor)、電容(capacitor)、電感(inductor)及/或保險絲(fuse)。
請參見第2D圖,形成化學金屬層114於基板102之第一表面102a之上、黏著層106上、以及形成於電子元件10之上表面與側壁上。
需注意的是,形成化學金屬層114之目的在於作為後續形成之電鍍金屬層124之晶種層,以利後續形成電鍍金屬層124(請參見第2E圖)。在一些實施例中,化學金屬層114之材料包括銅(Cu)、鋁(Al)、鎳(Ni)、金(Cu)、鈀(Pd)或上述之組合。
請參見第2E圖,順應性地形成電鍍金屬層124於化學金屬層114之上,其中化學金屬層114與電鍍金屬層兩者合稱為導電層125。在一些實施例中,電鍍金屬層124之材料包括銅(Cu)、鋁(Al)、鎳(Ni)、金(Cu)或上述之組合。在一些實施例中,化學金屬層114之材料為銅,且電鍍金屬層124之材料也為銅。
請參見第2F圖,去除黏著層106,以暴露電子元件10之底部,以及暴露位於第二表面102b上的銅層104。
請參見第2G圖,進行圖案化製程,以在基板102之第一表面102a與第二表面102b之上形成第一線路層135。由於位於基板102之上的銅層104具有導電性,因此,為了簡化說明,本發明將銅層104與導電層125畫成同一層。須注意的是,第一線路層135從基板102之第一表面102a,沿著貫通孔107之側壁延伸至第二表面102b,且第一線路層135直接接觸電子元
件10。
請參見第2H圖,於圖案化製程之後,形成絕緣層140於第一線路層135之上。接著,形成複數個盲孔142於絕緣層140之中,其中該些盲孔142暴露第一線路層135。在一些實施例中,可藉由雷射鑽孔(laser drilling method)形成該些盲孔142。
請參見第2I圖,形成第二線路層145於該些盲孔142之中,以使第一線路層135電性連接至第二線路層145。接著,形成保護層150於第二線路層145與絕緣層140之上。保護層150之作用在於保護內埋之線路,以避免線路氧化。於一些實施例中,保護層150由防焊材料所組成,例如綠漆。之後,可利用植球作業(ball implantation)形成複數個錫球155,以使電子元件10的訊號得以連接至外部裝置。
在第二實施例中,電子元件10形成於貫通孔107之中,藉由第一線路層135與第二線路層145之輔助,可將電子元件10的訊號向基板102之兩側傳送,達到雙面的電性連接。
第3A-3H圖為一系列剖面圖,用以說明本發明第三實施例之內埋元件的基板結構之製造方法。於第3A-3H圖中的元件標號與第1A-1L圖相同者代表相同符號。
請參見第3A圖,提供基板102,其中基板102包括第一表面102a與第二表面102b,第一表面102a與第二表面102b之上具有銅層104。
請參見第3B圖,形成凹槽105與貫通孔107於基板102之中。形成凹槽105的目的是為了將後續形成的電子元件
10(請參見第3D圖)內埋於其中,以使整體封裝體積大幅縮小。
請再次參見第3B圖,貫通孔107貫穿基板102。形成貫通孔107之目的在於建立基板102上下兩面之導電通路,以利後續之雙面增層線路。
請參見第3C圖,形成化學金屬層114於基板102之第一表面102a與第二表面102b上、凹槽105之底部與側壁上、以及形成於貫通孔107之側壁上。
請參見第3D圖,形成黏著層106於凹槽105之底部。接著,形成電子元件10於黏著層106之上。黏著層106之目的在於固定電子元件10。
請參見第3E圖,於化學金屬層114之上順應性地形成電鍍金屬層124,其中化學金屬層114與電鍍金屬層124兩者合稱為導電層125。在一些實施例中,化學金屬層114之材料為銅,且電鍍金屬層124之材料也為銅。
須注意的是,在第一實施例中,係先形成黏著層106,之後才形成化學金屬層114。在第三實施例中,係先形成化學金屬層114,之後才形成黏著層106,電子元件10之上表面並未形成化學金屬層114,因此,當進行後續電鍍製程時,可以使電子元件10之部分上表面不形成電鍍金屬層124。如此一來,當電子元件10為電容結構時,可以使電容結構中間的絕緣結構14(請參見第1D’圖)不會與兩側的導電結構12彼此導通。由此可知,相對於第一實施例,第三實施例之優點在於,可以不需要額外移除絕緣結構14上方的導電層125的步驟。
另外地,第三實施例另一個優點在於,電鍍金屬
層124完全地填滿貫通孔107,因此,相對於第一實施例,第三實施例可以減少填充貫通孔107之步驟與節省填充材料。
請參見第3F圖,進行圖案化製程,以在基板102之第一表面102a與第二表面102b之上形成第一線路層135。由於位於基板102之上的銅層104具有導電性,因此,為了簡化說明,本發明將銅層104與導電層125畫成同一層。
請參見第3G圖,於圖案化製程之後,形成絕緣層140於第一線路層135之上。接著,形成複數個盲孔142於絕緣層140之中,其中該些盲孔142暴露第一線路層135。在一些實施例中,可藉由雷射鑽孔(laser drilling method)形成該些盲孔142。
請參見第3H圖,形成第二線路層145於該些盲孔142之中,以使第一線路層135電性連接至第二線路層145。接著,形成保護層150於第二線路層145與絕緣層140之上。保護層150之作用在於保護內埋之線路,以避免線路氧化。之後,可利用植球作業(ball implantation)形成複數個錫球155,以使電子元件10的訊號得以連接至外部裝置。
綜上所述,本案所述之內埋元件的基板結構具有下述優點:
(1)於第一實施例至第三實施例中,藉由第一線路層從基板之上表面延伸至凹槽之側壁,以提高第一線路層與電子元件之間的接觸面積,進而提升基板結構之良率。此外,可以增加線路佈線設計的彈性。
(2)在第二實施例中,藉由將電子元件形成於貫通
孔中,達到雙面傳輸訊號的效果,以節省佈線的面積。
(3)於第三實施例中,當電子元件為電容結構時,可以不需要額外的移除步驟,用於移除電容結構的絕緣結構上方的導電層。此外,電鍍金屬層可完全地填滿貫通孔107,因此可以減少填充貫通孔之步驟與節省填充材料。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧電子元件
102‧‧‧基板
106‧‧‧黏著層
128‧‧‧油墨
135‧‧‧第一線路層
140‧‧‧絕緣層
145‧‧‧第二線路層
150‧‧‧保護層
155‧‧‧錫球
Claims (19)
- 一種內埋元件的基板結構,包括:一基板,其中該基板具有一個或一個以上凹槽、一第一表面與一第二表面;一個或一個以上電子元件,其中該電子元件形成於該凹槽中;一第一線路層,形成於該電子元件與該凹槽之間的空隙中,其中該第一線路層從該基板之第一表面延伸至該凹槽之側壁,且該第一線路層直接接觸該電子元件;以及一黏著層,形成於該凹槽之底部上,其中該電子元件形成於該黏著層之上。
- 如申請專利範圍第1項所述之內埋元件的基板結構,其中該電子元件包括主動元件或被動元件。
- 如申請專利範圍第1項所述之內埋元件的基板結構,其中該第一線路層從該凹槽之側壁延伸至該凹槽之底部,且該黏著層形成於該電子元件與該第一線路層之間。
- 如申請專利範圍第1項所述之內埋元件的基板結構,尚包括:一絕緣層,形成於該第一線路層之上;複數個盲孔,形成於該絕緣層之中,其中該些盲孔暴露該第一線路層;以及一第二線路層形成於該些盲孔中,其中該第一線路層電性連接至該第二線路層。
- 如申請專利範圍第1項所述之內埋元件的基板結構,尚包 括:複數個貫通孔(through hole)貫穿該基板。
- 如申請專利範圍第5項所述之內埋元件的基板結構,其中該第一線路層從該基板之第一表面,沿著該貫通孔之側壁延伸至該第二表面。
- 如申請專利範圍第5項所述之內埋元件的基板結構,其中該第一線路層完全填滿該貫通孔。
- 一種內埋元件的基板結構,包括:一基板,其中該基板具有一第一表面與一第二表面,且該基板具有一個或一個以上貫通孔(through hole)貫穿該基板;一個或一個以上電子元件,其中該電子元件形成於該貫通孔中;以及一第一線路層,形成於該電子元件與該貫通孔之間的空隙中,其中該第一線路層從該基板之第一表面,沿著該貫通孔之側壁延伸至該第二表面,且該第一線路層直接接觸該電子元件。
- 如申請專利範圍第8項所述之內埋元件的基板結構,其中該電子元件包括主動元件或被動元件。
- 如申請專利範圍第8項所述之內埋元件的基板結構,尚包括:一絕緣層,形成於該第一線路層之上;複數個盲孔,形成於該絕緣層之中,其中該些盲孔暴露該第一線路層;以及一第二線路層形成於該些盲孔中,其中該第一線路層電性 連接至該第二線路層。
- 一種內埋元件的基板結構之製造方法,包括以下步驟:提供一基板,其中該基板具有一第一表面與一第二表面;形成一個或一個以上凹槽於該基板之中;形成一個或一個以上電子元件於該凹槽之中;以及形成一第一線路層於該電子元件與該凹槽之間的空隙中,其中該第一線路層從該基板之第一表面延伸至該凹槽之側壁,且該第一線路層直接接觸該電子元件。
- 如申請專利範圍第11項所述之內埋元件的基板結構之製造方法,其中形成該電子元件於該凹槽之中包括以下步驟:形成一黏著層於該凹槽之底部;以及形成該電子元件於該黏著層之上。
- 如申請專利範圍第11項所述之內埋元件的基板結構之製造方法,其中形成該電子元件於該凹槽之中包括以下步驟:形成一化學金屬層於該凹槽之底部;形成一黏著層於該化學金屬層之上;以及形成該電子元件於該黏著層之上。
- 如申請專利範圍第11項所述之內埋元件的基板結構之製造方法,其中形成該第一線路層於該電子元件與該凹槽之間的空隙中的方法包括:順應性地形成一化學金屬層於該凹槽之側壁上;以及形成一電鍍金屬層於該化學金屬層之上,其中該化學金屬層與該電鍍金屬層構成一導電層。
- 如申請專利範圍第14項所述之內埋元件的基板結構之製 造方法,尚包括:圖案化該導電層,以形成該第一線路層;形成一絕緣層於該第一線路層之上;形成複數個盲孔於該絕緣層之中,其中該些盲孔暴露該第一線路層;以及形成一第二線路層於該些盲孔中,其中該第一線路層電性連接至該第二線路層。
- 一種內埋元件的基板結構之製造方法,包括以下步驟:提供一基板,其中該基板具有一第一表面與一第二表面;形成一個或一個以上貫通孔(through hole)貫穿該基板;形成一個或一個以上電子元件於該貫通孔之中;以及形成一第一線路層於該電子元件與該貫通孔之間的空隙中,其中該第一線路層從該基板之第一表面,沿著該貫通孔之側壁延伸至該第二表面,且該第一線路層直接接觸該電子元件。
- 如申請專利範圍第16項所述之內埋元件的基板結構之製造方法,其中形成該電子元件於該貫通孔之中之前尚包括:形成一黏著層於該基板之第二表面上。
- 如申請專利範圍第16項所述之內埋元件的基板結構之製造方法,尚包括:形成一絕緣層於該第一線路層之上;形成複數個盲孔於該絕緣層之中,其中該些盲孔暴露該第一線路層;以及形成一第二線路層於該些盲孔中,其中該第一線路層電性 連接至該第二線路層。
- 如申請專利範圍第16項所述之內埋元件的基板結構之製造方法,其中形成該第一線路層於該電子元件與該貫通孔之間的空隙中包括:順應性地形成一化學金屬層於該貫通孔之側壁上;以及形成一電鍍金屬層於該化學金屬層之上,其中該第一線路層包括該化學金屬層與該電鍍金屬層。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103122800A TWI513379B (zh) | 2014-07-02 | 2014-07-02 | 內埋元件的基板結構與其製造方法 |
US14/790,669 US9894779B2 (en) | 2014-07-02 | 2015-07-02 | Embedded component substrate and method for fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103122800A TWI513379B (zh) | 2014-07-02 | 2014-07-02 | 內埋元件的基板結構與其製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI513379B true TWI513379B (zh) | 2015-12-11 |
TW201603660A TW201603660A (zh) | 2016-01-16 |
Family
ID=55018071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW103122800A TWI513379B (zh) | 2014-07-02 | 2014-07-02 | 內埋元件的基板結構與其製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9894779B2 (zh) |
TW (1) | TWI513379B (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI572265B (zh) * | 2016-03-09 | 2017-02-21 | 欣興電子股份有限公司 | 具有凹槽的線路板的製作方法 |
US10872852B2 (en) | 2016-10-12 | 2020-12-22 | Micron Technology, Inc. | Wafer level package utilizing molded interposer |
CN109148431B (zh) * | 2018-07-18 | 2020-04-17 | 华天科技(昆山)电子有限公司 | 距离传感器芯片封装结构及其晶圆级封装方法 |
CN211045436U (zh) * | 2019-07-07 | 2020-07-17 | 深南电路股份有限公司 | 线路板 |
CN112770495B (zh) * | 2019-10-21 | 2022-05-27 | 宏启胜精密电子(秦皇岛)有限公司 | 全向内埋模组及制作方法、封装结构及制作方法 |
TWI715261B (zh) * | 2019-10-23 | 2021-01-01 | 強茂股份有限公司 | 晶片尺寸封裝結構及其製作方法 |
EP4156874A4 (en) | 2020-07-07 | 2024-02-14 | Shennan Circuits Co., Ltd. | PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING SAME |
TWI728940B (zh) * | 2020-11-19 | 2021-05-21 | 欣興電子股份有限公司 | 封裝載板及其製作方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI357292B (en) * | 2007-11-13 | 2012-01-21 | Advanced Semiconductor Eng | Multilayer circuit board with embedded electronic |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6972964B2 (en) * | 2002-06-27 | 2005-12-06 | Via Technologies Inc. | Module board having embedded chips and components and method of forming the same |
US7242591B2 (en) * | 2002-10-08 | 2007-07-10 | Dai Nippon Printing Co., Ltd. | Wiring board incorporating components and process for producing the same |
KR100598275B1 (ko) * | 2004-09-15 | 2006-07-10 | 삼성전기주식회사 | 수동소자 내장형 인쇄회로기판 및 그 제조 방법 |
TWI301739B (en) * | 2004-12-03 | 2008-10-01 | Via Tech Inc | Structure and method for embedded passive component assembly |
KR100688769B1 (ko) * | 2004-12-30 | 2007-03-02 | 삼성전기주식회사 | 도금에 의한 칩 내장형 인쇄회로기판 및 그 제조 방법 |
KR100726240B1 (ko) * | 2005-10-04 | 2007-06-11 | 삼성전기주식회사 | 전자소자 내장 인쇄회로기판 및 그 제조방법 |
KR100700922B1 (ko) * | 2005-10-17 | 2007-03-28 | 삼성전기주식회사 | 수동 소자를 내장한 기판 및 그 제조 방법 |
TWI351090B (en) * | 2007-01-31 | 2011-10-21 | Advanced Semiconductor Eng | Buried eletronic device structure and methods for forming the same |
TWI360375B (en) * | 2007-03-29 | 2012-03-11 | Advanced Semiconductor Eng | Carrier with embedded component and manufacturing |
TW200901409A (en) * | 2007-06-22 | 2009-01-01 | Nan Ya Printed Circuit Board Corp | Packaging substrate with embedded chip and buried heatsink |
TWI363585B (en) * | 2008-04-02 | 2012-05-01 | Advanced Semiconductor Eng | Method for manufacturing a substrate having embedded component therein |
KR101003585B1 (ko) * | 2008-06-25 | 2010-12-22 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
TWI400998B (zh) * | 2010-08-20 | 2013-07-01 | Nan Ya Printed Circuit Board | 印刷電路板及其製造方法 |
KR101095161B1 (ko) * | 2010-10-07 | 2011-12-16 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 |
US9398694B2 (en) * | 2011-01-18 | 2016-07-19 | Sony Corporation | Method of manufacturing a package for embedding one or more electronic components |
TWI506575B (zh) * | 2012-08-06 | 2015-11-01 | Hung Wei Chen | 產品的登錄方法及其應用程式 |
US8890628B2 (en) * | 2012-08-31 | 2014-11-18 | Intel Corporation | Ultra slim RF package for ultrabooks and smart phones |
KR101343296B1 (ko) * | 2012-11-02 | 2013-12-18 | 삼성전기주식회사 | 전자부품 내장기판 제조방법 및 전자부품 내장기판 |
US20140167273A1 (en) * | 2012-12-19 | 2014-06-19 | Qualcomm Incorporated | Low parasitic package substrate having embedded passive substrate discrete components and method for making same |
CN103906372B (zh) * | 2012-12-27 | 2017-03-01 | 碁鼎科技秦皇岛有限公司 | 具有内埋元件的电路板及其制作方法 |
TW201545614A (zh) * | 2014-05-02 | 2015-12-01 | R&D Circuits Inc | 製備殼體以接收用於嵌入式元件印刷電路板之元件的結構和方法 |
-
2014
- 2014-07-02 TW TW103122800A patent/TWI513379B/zh active
-
2015
- 2015-07-02 US US14/790,669 patent/US9894779B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI357292B (en) * | 2007-11-13 | 2012-01-21 | Advanced Semiconductor Eng | Multilayer circuit board with embedded electronic |
Also Published As
Publication number | Publication date |
---|---|
TW201603660A (zh) | 2016-01-16 |
US9894779B2 (en) | 2018-02-13 |
US20160007469A1 (en) | 2016-01-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI513379B (zh) | 內埋元件的基板結構與其製造方法 | |
US9093459B2 (en) | Package structure having a semiconductor component embedded therein and method of fabricating the same | |
KR100782405B1 (ko) | 인쇄회로기판 제조방법 | |
KR102425753B1 (ko) | 인쇄회로기판, 인쇄회로기판의 제조 방법 및 이를 포함하는 반도체 패키지 | |
JP2007173775A (ja) | 回路基板構造及びその製法 | |
KR102194722B1 (ko) | 패키지 기판, 패키지 기판의 제조 방법 및 이를 포함하는 적층형 패키지 | |
JP5989814B2 (ja) | 埋め込み基板、印刷回路基板及びその製造方法 | |
KR101516072B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
US9247654B2 (en) | Carrier substrate and manufacturing method thereof | |
KR20100065691A (ko) | 금속범프를 갖는 인쇄회로기판 및 그 제조방법 | |
KR102333091B1 (ko) | 인쇄회로기판 및 인쇄회로기판의 제조 방법 | |
KR102194718B1 (ko) | 임베디드 기판 및 임베디드 기판의 제조 방법 | |
KR20170009128A (ko) | 회로 기판 및 그 제조 방법 | |
KR20150102504A (ko) | 임베디드 기판 및 임베디드 기판의 제조 방법 | |
KR20150064976A (ko) | 인쇄회로기판 및 그 제조방법 | |
KR20110003093A (ko) | 금속범프를 갖는 인쇄회로기판의 제조방법 | |
KR102473416B1 (ko) | 인쇄회로기판 및 인쇄회로기판의 제조 방법 | |
US20150156882A1 (en) | Printed circuit board, manufacturing method thereof, and semiconductor package | |
KR102521788B1 (ko) | 딥 캐비티 구조의 다층 인쇄회로기판 제조 방법 | |
JP6798076B2 (ja) | エンベデッド基板及びエンベデッド基板の製造方法 | |
KR102240704B1 (ko) | 패키지 기판, 패키지 기판의 제조 방법 및 이를 이용한 적층형 패키지 | |
KR101158213B1 (ko) | 전자부품 내장형 인쇄회로기판 및 이의 제조 방법 | |
KR20150136914A (ko) | 인쇄회로기판의 제조방법 | |
JP2018101776A (ja) | プリント回路基板及びパッケージ | |
KR100888562B1 (ko) | 능동소자 내장형 인쇄회로기판 제조 방법 |