JP6798076B2 - エンベデッド基板及びエンベデッド基板の製造方法 - Google Patents
エンベデッド基板及びエンベデッド基板の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 239000010410 layer Substances 0.000 claims description 315
- 239000002184 metal Substances 0.000 claims description 113
- 229910052751 metal Inorganic materials 0.000 claims description 113
- 239000000945 filler Substances 0.000 claims description 75
- 238000000034 method Methods 0.000 claims description 62
- 239000011241 protective layer Substances 0.000 claims description 46
- 239000000853 adhesive Substances 0.000 claims description 22
- 230000001070 adhesive effect Effects 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 4
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- 238000005498 polishing Methods 0.000 claims description 3
- 239000010949 copper Substances 0.000 description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 19
- 239000000126 substance Substances 0.000 description 13
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- 238000007747 plating Methods 0.000 description 11
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- 238000009713 electroplating Methods 0.000 description 7
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- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 3
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
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- 229920003192 poly(bis maleimide) Polymers 0.000 description 3
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- 230000002250 progressing effect Effects 0.000 description 1
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
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- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
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- H01L2924/3511—Warping
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10015—Non-printed capacitor
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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Description
110 第1回路層
120 金属フィラー
130 絶縁層
131 第1絶縁層
132 第2絶縁層
140 第2回路層
150 第1電子素子
155 第2電子素子
157 接続パターン
160 接着剤
170 金属層
175 第1ビアホール
176 第2ビアホール
181 第1ビア
182 第2ビア
190 保護層
195 アンダーフィル樹脂
197 第1外部接続端子
200 キャリア基板
210 キャリアコア
220 キャリア金属層
300 メッキレジスト
310 メッキ開口部
Claims (22)
- 第1絶縁層と、
前記第1絶縁層の内部に配置された第1回路層と、
前記第1絶縁層の上面上に配置された第2絶縁層と、
前記第2絶縁層の内部に配置された第2回路層と、
前記第2絶縁層の内部で前記第2回路層の側面から離隔するように配置された第1電子素子と、
前記第1絶縁層の内部に、そして前記第1回路層と前記第2回路層または第1電子素子との間に配置された金属フィラーと、
前記第2絶縁層の内部に、そして前記第2回路層の上面上に配置された第1ビアと、
前記第2絶縁層の上面上に配置され、前記第1ビアの少なくとも一部をソルダが塗布されるために前記第2絶縁層から露出させる開口を有する第1保護層と、を含むエンベデッド基板。 - 前記第1絶縁層は、前記第1回路層の下面を外部に露出させ、前記第2絶縁層は前記第1ビアの上面を外部に露出させる、請求項1に記載のエンベデッド基板。
- 前記第1回路層の下面は、前記第1絶縁層の下面と同一平面に位置する請求項2に記載のエンベデッド基板。
- 前記第1ビアの上面は、前記第2絶縁層の上面と同一平面に位置する請求項2または請求項3に記載のエンベデッド基板。
- 前記金属フィラーは、前記第1回路層と、第2回路層及び第1電子素子のうち少なくとも1つとを電気的に接続するために形成された請求項1から請求項4のいずれか1項に記載のエンベデッド基板。
- 前記金属フィラーと第1電子素子との間に形成された接着剤をさらに含む請求項1から請求項5のいずれか1項に記載のエンベデッド基板。
- 絶縁層と、
前記絶縁層の内部に形成された第1回路層と、
前記絶縁層の内部に形成され、前記第1回路層の上部に形成された第2回路層と、
前記絶縁層の内部で前記第2回路層の側面から離隔するように配置された第1電子素子と、
前記第1回路層と前記第2回路層または第1電子素子との間に形成された金属フィラーと、
前記絶縁層の内部に形成され、前記第2回路層の上部に形成された第1ビアと、を含み、
前記金属フィラーと第1電子素子との間に形成された接着剤をさらに含み、
前記接着剤は、前記金属フィラーと第1電子素子とを電気的に接続する、エンベデッド基板。 - 前記第2絶縁層の内部での前記第1電子素子の上部に形成され、前記第1電子素子と電気的に接続する第2ビアをさらに含む請求項1から請求項6のいずれか1項に記載のエンベデッド基板。
- 前記第2絶縁層は、前記第2ビアの上面を外部に露出する請求項8に記載のエンベデッド基板。
- 前記第1絶縁層の下部に形成される第2保護層をさらに含む請求項1から6、8および9のいずれか1項に記載のエンベデッド基板。
- 前記第2絶縁層の上部及び前記第1絶縁層の下部のうち少なくとも一方に実装される第2電子素子をさらに含む請求項1から6、8から10のいずれか1項に記載のエンベデッド基板。
- 前記第2電子素子と前記第1絶縁層との間に、または前記第2電子素子と前記第2絶縁層との間に形成されるアンダーフィル樹脂をさらに含む請求項11に記載のエンベデッド基板。
- キャリア基板に第1回路層を形成するステップと、
前記第1回路層の上部に金属フィラーを形成するステップと、
前記第1回路層と金属フィラーとが埋め込まれ、前記金属フィラーの上面が外部に露出するように第1絶縁層を形成するステップと、
前記金属フィラーの一部の上部に第2回路層を形成するステップと、
前記外部に露出された金属フィラーの上部に第1電子素子を配置するステップと、
前記第2回路層及び第1電子素子を埋め込む第2絶縁層を形成するステップと、
前記第2回路層の上部に形成され、前記第2絶縁層を貫通する第1ビアを形成するステップと、
前記キャリア基板を除去するステップと、
前記第2絶縁層の上部に第1保護層を形成するステップと、を含み、
前記第1保護層は前記第1ビアの少なくとも一部をソルダが塗布されるために前記第2絶縁層から露出させる開口を有する、エンベデッド基板の製造方法。 - 前記第1絶縁層を形成するステップは、
前記第1回路層と金属フィラーとを埋め込む第1絶縁層を形成するステップと、
前記金属フィラーの上面が外部に露出するように前記第1絶縁層を研磨するステップと、
を含む請求項13に記載のエンベデッド基板の製造方法。 - 前記第1電子素子を配置するステップの前に、
前記外部に露出した金属フィラーの上部に接着剤を形成するステップをさらに含む請求項13または請求項14に記載のエンベデッド基板の製造方法。 - 前記接着剤は、伝導性材質で形成される請求項15に記載のエンベデッド基板の製造方法。
- 前記第1ビアを形成するステップは、
前記第1電子素子の上部に形成され、前記第2絶縁層を貫通する第2ビアを形成するステップをさらに含む請求項13から請求項16のいずれか1項に記載のエンベデッド基板の製造方法。 - 前記第2絶縁層を形成するステップにおいて、
前記第2絶縁層は、上面に金属層がさらに形成された請求項13から請求項17のいずれか1項に記載のエンベデッド基板の製造方法。 - 前記第1ビアを形成するステップの後に、
前記第1ビアの上面が外部に露出するように、前記金属層を除去するステップをさらに含む請求項18に記載のエンベデッド基板の製造方法。 - 前記キャリア基板を除去するステップの後に、
前記第1絶縁層の下部に第2保護層を形成するステップをさらに含む請求項13から請求項19のいずれか1項に記載のエンベデッド基板の製造方法。 - 前記第2保護層を形成するステップの後に、
前記第1絶縁層の下部及び前記第2絶縁層の上部のうち少なくとも一方に第2電子素子を実装するステップをさらに含む請求項20に記載のエンベデッド基板の製造方法。 - 前記第2電子素子を実装するステップの後に、
前記第2電子素子と、前記第1絶縁層及び第2絶縁層のうち少なくとも1つとの間にアンダーフィル樹脂を形成するステップをさらに含む請求項21に記載のエンベデッド基板の製造方法。
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KR1020150010699A KR102281460B1 (ko) | 2015-01-22 | 2015-01-22 | 임베디드 기판 및 임베디드 기판의 제조 방법 |
KR10-2015-0010699 | 2015-01-22 |
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JP2016134622A JP2016134622A (ja) | 2016-07-25 |
JP6798076B2 true JP6798076B2 (ja) | 2020-12-09 |
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KR20210076584A (ko) * | 2019-12-16 | 2021-06-24 | 삼성전기주식회사 | 전자부품 내장기판 |
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JP3920195B2 (ja) * | 2002-11-11 | 2007-05-30 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
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JPWO2010101167A1 (ja) * | 2009-03-05 | 2012-09-10 | 日本電気株式会社 | 半導体装置及びその製造方法 |
WO2012133839A1 (ja) * | 2011-03-30 | 2012-10-04 | 日本電気株式会社 | 機能素子内蔵基板、これを備えた電子機器及び機能素子内蔵基板の製造方法 |
US8883561B2 (en) * | 2011-04-30 | 2014-11-11 | Stats Chippac, Ltd. | Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP |
JP5931483B2 (ja) * | 2012-02-10 | 2016-06-08 | 日本メクトロン株式会社 | 部品内蔵多層プリント配線板の製造方法、および部品内蔵多層プリント配線板 |
JP2013211519A (ja) * | 2012-02-29 | 2013-10-10 | Ngk Spark Plug Co Ltd | 多層配線基板の製造方法 |
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US9113573B2 (en) * | 2012-11-21 | 2015-08-18 | Intel Corporation | Molded insulator in package assembly |
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KR20160090648A (ko) | 2016-08-01 |
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