JP2016134622A - エンベデッドエンベデッド基板及びエンベデッド基板の製造方法 - Google Patents
エンベデッドエンベデッド基板及びエンベデッド基板の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 110
- 229910052751 metal Inorganic materials 0.000 claims abstract description 110
- 239000000945 filler Substances 0.000 claims abstract description 73
- 239000010410 layer Substances 0.000 claims description 298
- 239000000758 substrate Substances 0.000 claims description 126
- 238000000034 method Methods 0.000 claims description 76
- 239000011241 protective layer Substances 0.000 claims description 42
- 239000000853 adhesive Substances 0.000 claims description 21
- 230000001070 adhesive effect Effects 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 20
- 229920005989 resin Polymers 0.000 claims description 13
- 239000011347 resin Substances 0.000 claims description 13
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 2
- 239000012778 molding material Substances 0.000 abstract description 5
- 239000010949 copper Substances 0.000 description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 19
- 239000000463 material Substances 0.000 description 14
- 238000007747 plating Methods 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000011810 insulating material Substances 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 7
- 239000000654 additive Substances 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 3
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229920003192 poly(bis maleimide) Polymers 0.000 description 3
- 239000002952 polymeric resin Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 229920003002 synthetic resin Polymers 0.000 description 3
- 239000004840 adhesive resin Substances 0.000 description 2
- 229920006223 adhesive resin Polymers 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
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- 230000002250 progressing effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
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- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
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- H01L2924/3511—Warping
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
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Abstract
【解決手段】エンベデッド基板及びエンベデッド基板の製造方法を提供する。エンベデッド基板100は、絶縁層130と、絶縁層の内部に形成された第1回路層110と、絶縁層の内部に形成され、第1回路層の上部に形成された第2回路層140と、絶縁層の内部で第2回路層の側面から離隔するように配置された第1電子素子150と、第1回路層と第2回路層または第1電子素子との間に形成された金属フィラー120と、絶縁層の内部に形成され、第2回路層の上部に形成された第1ビア181と、を含む。
【選択図】図1
Description
110 第1回路層
120 金属フィラー
130 絶縁層
131 第1絶縁層
132 第2絶縁層
140 第2回路層
150 第1電子素子
155 第2電子素子
157 接続パターン
160 接着剤
170 金属層
175 第1ビアホール
176 第2ビアホール
181 第1ビア
182 第2ビア
190 保護層
195 アンダーフィル樹脂
197 第1外部接続端子
200 キャリア基板
210 キャリアコア
220 キャリア金属層
300 メッキレジスト
310 メッキ開口部
Claims (22)
- 絶縁層と、
前記絶縁層の内部に形成された第1回路層と、
前記絶縁層の内部に形成され、前記第1回路層の上部に形成された第2回路層と、
前記絶縁層の内部で前記第2回路層の側面から離隔するように配置された第1電子素子と、
前記第1回路層と前記第2回路層または第1電子素子との間に形成された金属フィラーと、
前記絶縁層の内部に形成され、前記第2回路層の上部に形成された第1ビアと、
を含むエンベデッド基板。 - 前記絶縁層は、前記第1回路層の下面及び前記第1ビアの上面を外部に露出する請求項1に記載のエンベデッド基板。
- 前記第1回路層の下面は、前記絶縁層の下面と同一平面に位置する請求項2に記載のエンベデッド基板。
- 前記第1ビアの上面は、前記絶縁層の上面と同一平面に位置する請求項2または請求項3に記載のエンベデッド基板。
- 前記金属フィラーは、前記第1回路層と、第2回路層及び第1電子素子のうち少なくとも1つとを電気的に接続するために形成された請求項1から請求項4のいずれか1項に記載のエンベデッド基板。
- 前記金属フィラーと第1電子素子との間に形成された接着剤をさらに含む請求項1から請求項5のいずれか1項に記載のエンベデッド基板。
- 前記接着剤は、前記金属フィラーと第1電子素子とを電気的に接続する請求項6に記載のエンベデッド基板。
- 前記絶縁層の内部での前記第1電子素子の上部に形成され、前記第1電子素子と電気的に接続する第2ビアをさらに含む請求項1から請求項7のいずれか1項に記載のエンベデッド基板。
- 前記絶縁層は、前記第2ビアの上面を外部に露出する請求項8に記載のエンベデッド基板。
- 前記絶縁層の上部及び下部に形成される保護層をさらに含む請求項1から請求項9のいずれか1項に記載のエンベデッド基板。
- 前記絶縁層の上部及び下部のうち少なくとも一方に実装される第2電子素子をさらに含む請求項1から請求項10のいずれか1項に記載のエンベデッド基板。
- 前記第2電子素子と前記絶縁層との間に形成されるアンダーフィル樹脂をさらに含む請求項11に記載のエンベデッド基板。
- キャリア基板に第1回路層を形成するステップと、
前記第1回路層の上部に金属フィラーを形成するステップと、
前記第1回路層と金属フィラーとが埋め込まれ、前記金属フィラーの上面が外部に露出するように第1絶縁層を形成するステップと、
前記金属フィラーの一部の上部に第2回路層を形成するステップと、
前記外部に露出された金属フィラーの上部に第1電子素子を配置するステップと、
前記第2回路層及び第1電子素子を埋め込む第2絶縁層を形成するステップと、
前記第2回路層の上部に形成され、前記第2絶縁層を貫通する第1ビアを形成するステップと、
前記キャリア基板を除去するステップと、
を含むエンベデッド基板の製造方法。 - 前記第1絶縁層を形成するステップは、
前記第1回路層と金属フィラーとを埋め込む第1絶縁層を形成するステップと、
前記金属フィラーの上面が外部に露出するように前記第1絶縁層を研磨するステップと、
を含む請求項13に記載のエンベデッド基板の製造方法。 - 前記第1電子素子を配置するステップの前に、
前記外部に露出した金属フィラーの上部に接着剤を形成するステップをさらに含む請求項13または請求項14に記載のエンベデッド基板の製造方法。 - 前記接着剤は、伝導性材質で形成される請求項15に記載のエンベデッド基板の製造方法。
- 前記第1ビアを形成するステップは、
前記第1電子素子の上部に形成され、前記第2絶縁層を貫通する第2ビアを形成するステップをさらに含む請求項13から請求項16のいずれか1項に記載のエンベデッド基板の製造方法。 - 前記第2絶縁層を形成するステップにおいて、
前記第2絶縁層は、上面に金属層がさらに形成された請求項13から請求項17のいずれか1項に記載のエンベデッド基板の製造方法。 - 前記第1ビアを形成するステップの後に、
前記第1ビアの上面が外部に露出するように、前記金属層を除去するステップをさらに含む請求項18に記載のエンベデッド基板の製造方法。 - 前記キャリア基板を除去するステップの後に、
前記第1絶縁層の下部及び第2絶縁層の上部に保護層を形成するステップをさらに含む請求項13から請求項19のいずれか1項に記載のエンベデッド基板の製造方法。 - 前記保護層を形成するステップの後に、
前記第1絶縁層の下部及び前記第2絶縁層の上部のうち少なくとも一方に第2電子素子を実装するステップをさらに含む請求項20に記載のエンベデッド基板の製造方法。 - 前記第2電子素子を実装するステップの後に、
前記第2電子素子と、前記第1絶縁層及び第2絶縁層のうち少なくとも1つとの間にアンダーフィル樹脂を形成するステップをさらに含む請求項21に記載のエンベデッド基板の製造方法。
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CN116456619B (zh) * | 2022-01-10 | 2024-06-14 | 无锡深南电路有限公司 | 印制电路板的制作方法 |
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US20160219709A1 (en) | 2016-07-28 |
US10098232B2 (en) | 2018-10-09 |
KR20160090648A (ko) | 2016-08-01 |
JP6798076B2 (ja) | 2020-12-09 |
KR102281460B1 (ko) | 2021-07-27 |
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