WO2022007277A1 - 埋入式电路板、电子装置 - Google Patents

埋入式电路板、电子装置 Download PDF

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Publication number
WO2022007277A1
WO2022007277A1 PCT/CN2020/127020 CN2020127020W WO2022007277A1 WO 2022007277 A1 WO2022007277 A1 WO 2022007277A1 CN 2020127020 W CN2020127020 W CN 2020127020W WO 2022007277 A1 WO2022007277 A1 WO 2022007277A1
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Prior art keywords
core board
layer
board
core
power devices
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PCT/CN2020/127020
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English (en)
French (fr)
Inventor
黄立湘
王泽东
缪桦
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深南电路股份有限公司
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Publication of WO2022007277A1 publication Critical patent/WO2022007277A1/zh

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    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09072Hole or recess under component or special relationship between hole and component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0723Electroplating, e.g. finish plating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present application relates to the technical field of chip embedding, and in particular, to an embedded circuit board and an electronic device.
  • an embedded circuit board comprising: a multi-layer circuit layer; Between two adjacent intermediate layers; a plurality of groove bodies are opened on the first core board and the second core board; and a plurality of components are correspondingly arranged in the plurality of the groove bodies.
  • a plurality of the components are arranged in mirror symmetry with the plane between the first core board and the second core board.
  • the first core board is provided with a first groove body group
  • the second core board is provided with a second groove body group at a position corresponding to the first groove body group
  • the components include a first power device and a second power device, all the first power devices are arranged in the respective slots in the first slot group, and all the second power devices are arranged in the respective slots in the second slot group
  • the first power devices located in the first tank group are interconnected, and the second power devices located in the second tank group are interconnected.
  • the first power device 151 is arranged in the respective slots in the first slot group, and the second power devices 152 are arranged in the respective slots in the second slot group.
  • one component 15 is arranged in one tank, and in another embodiment, a plurality of components 15 may also be arranged in one tank.
  • the third core board 15 when the third core board 15 is disposed on the side of the first core board 11 away from the second core board 12 , the third core board 15 can be directly welded to the surface of the first core board 11 by tin solder, or it can be The third core board 15 is bonded to the first core board 11 by a prepreg.
  • both surfaces of the third core board 15 and the fourth core board 16 provided in this embodiment are covered with copper foil layers.
  • the third core board 15 includes a prepreg 152 and copper layers 151 and 153 located on both sides of the prepreg 152 ;
  • the fourth core board 16 includes a prepreg 162 and copper layers 161 and copper layers located on both sides of the prepreg 162 163.
  • the copper layers 151 and 153 on both surfaces of the third core board 15 and the copper layers 161 and 163 on both surfaces of the fourth core board 16 are It is a thick copper layer with a thickness of 150-200um.
  • the copper layers 151 and 153 on both surfaces of the third core board 15 and the copper layers 161 and 163 on both surfaces of the fourth core board 16 are both 175 ⁇ m.
  • FIG. 4 is a schematic structural diagram of a third embodiment of the embedded circuit board of the present application.
  • the embedded circuit board shown in this embodiment further includes an intermediate layer 13 , a third core board 15 , a first core board 11 and a
  • the second core board 12 , the fourth core board 16 , and the intermediate layer 14 are connected through the through holes 17 .
  • the through hole 17 conducts all circuit layers of the embedded circuit board. It can be understood that the isolation ring is provided at the position where conduction does not need to be performed. It is not repeated here.
  • FIG. 5 is a schematic structural diagram of an embodiment of an electronic device of the present application.
  • the electronic device provided by the present application includes the embedded circuit board 51 described in any of the above embodiments in FIG. 1 to FIG. 4 .
  • the electronic device provided by the present application may be a mobile device, an automobile device, a base station device or a sensor assembly.
  • the electronic device provided by the present application can support large current transmission in applications.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种埋入式电路板、电子装置,包括:多层线路层;至少第一芯板(11)和第二芯板(12),设置在所述线路层的相邻的两个中间层(13,14)之间;所述第一芯板(11)、所述第二芯板(12)上开设有多个槽体;多个元器件(151,152),对应设置在多个所述槽体中。以此在压合过程中,使第一芯板(11)及第二芯板(12)外侧的线路层产生的应力相互抵消,进而防止电路板发生翘曲。

Description

埋入式电路板、电子装置 【技术领域】
本申请涉及芯片埋入技术领域,特别是涉及一种埋入式电路板、电子装置。
【背景技术】
印刷电路板是重要的电子部件,是电子元器件的支撑体,是电子元器件电气连接的提供者。为达到特殊性能要求,越来越多的印刷电路板采用在板内埋入元器件的方式。但是在板内埋入元器件会在制作电路板的压合过程中使电路板发生翘曲。
目前行业中解决电路板翘曲的主要方式有:1、延长层压时间,释放残余应力。但是采用这种方式会导致生产周期成倍增加,降低生产效率;2、钻孔后进行加压烘烤处理,释放机械压力;3、出货前进行热压平整。采用上2及3的方式增加了额外的生产成本,并且不能从源头上解决电路板发生翘曲的问题,导致生产合格率低。
【发明内容】
本申请主要提供一种埋入式电路板、电子装置,以防止电路板发生翘曲。
为解决上述技术问题,本申请提供的一个技术方案为:提供一种埋入式电路板,包括:多层线路层;至少第一芯板和第二芯板,设置在所述线路层的相邻的两个中间层之间;所述第一芯板、所述第二芯板上开设有多个槽体;多个元器件,对应设置在多个所述槽体中。
其中,多个所述元器件对称设置。
其中,多个所述元器件以所述第一芯板和所述第二芯板之间的平面为镜面对称设置。
其中,所述第一芯板及所述第二芯板表面为铜层,且所述第一芯板 及所述第二芯板远离所述中间层的铜层的厚度为60-80um,所述中间层为多层,且所述中间层为铜层,所述中间层的厚度为150-200um。
其中,各层所述线路层的厚度以所述第一芯板和所述第二芯板之间的平面为镜面对称设置。
其中,所述第一芯板背对所述第二芯板一侧的多层线路层之间设有至少第三芯板,所述第二芯板背对所述第一芯板一侧的多层线路层之间设有至少第四芯板;所有所述第一芯板、所述第三芯板构成的第一芯板组和所有所述第二芯板、所述第四芯板构成的第二芯板组以所述第一芯板和所述第二芯板之间的平面为镜面对称设置。
其中,所有埋入式电路板以所述第一芯板和所述第二芯板之间的平面为镜面对称设置;或所有埋入式电路板以所述第一芯板和所述第二芯板之间的中点为中心旋转对称设置。
其中,所述多层线路层还包括外层线路层,所述外层线路层位于所述中间层的外侧,且所述外层线路层的厚度为60-80um,所述中间层的厚度为150-200um,自所述中间层至所述外层线路层之间的所有线路层的厚度为150-200um。
其中,所述第一芯板上设置有第一槽体组,所述第二芯板对应所述第一槽体组的位置处设置有第二槽体组;所述元器件包括第一功率器件及第二功率器件,所有所述第一功率器件设置于所述第一槽体组中的各自槽体内,所有所述第二功率器件设置于所述第二槽体组中的各自槽体内;位于所述第一槽体组内的所述第一功率器件之间互联,位于所述第二槽体组内的所述第二功率器件之间互联。
其中,所有所述第一功率器件在所述第一槽体中的各个槽体内阵列排布,位于同一行的所述第一功率器件之间相互串联形成多个功率器件组,所述多个功率器件组相互并联;所有所述第二功率器件在所述第二槽体中的各个槽体内阵列排布,位于同一行的所述第二功率器件之间相互串联形成多个功率器件组,所述多个功率器件组相互并联。
其中,所述第一功率器件靠近所述中间层的一侧具有第二连接端子及第三连接端子,另一侧具有第一连接端子;其中,一所述第一功率器 件的所述第一连接端子连接同一行相邻的所述第一功率器件的所述第二连接端子,以将同一行的所述第一功率器件相互串联形成多个功率器件组;其中,所述第一功率器件的所述第二连接端子连接靠近所述第一芯板的所述中间层,同一行相邻的所述第一功率器件的所述第一连接端子连接所述第一芯板远离所述中间层的表面的铜层,以将所述多个功率器件组并联;所述第二功率器件靠近所述中间层的一侧具有第二连接端子及第三连接端子,另一侧具有第一连接端子;其中,一所述第二功率器件的所述第一连接端子连接同一行相邻的所述第二功率器件的所述第二连接端子,以将同一行的所述第二功率器件相互串联形成多个功率器件组;其中,所述第二功率器件的所述第二连接端子连接靠近所述第二芯板的所述中间层,同一行相邻的所述第二功率器件的所述第一连接端子连接所述第二芯板远离所述中间层的表面的铜层,以将所述多个功率器件组并联。
其中,所有所述第一功率器件的所述第三连接端子连接所述第一芯板远离所述第二芯板一侧的线路层中的一层;所有所述第二功率器件的所述第三连接端子连接所述第二芯板远离所述第一芯板一侧的线路层中的一层。
其中,所述埋入式电路板应用于移动设备、汽车设备、基站设备或传感组件中。
为解决上述技术问题,本申请提供的第二个技术方案为:提供一种埋入式电路板,至少包括多层线路层;芯板,设置在所述多层线路层的中间层;其中,所述芯板开设有多个槽体;多个元器件,对应设置在多个所述槽体中;其中,所述埋入式电路板以所述芯板为中心至少在部分结构或部分物理量上对称设置,以使得所述埋入式电路板在温度变化时应力均衡,降低翘曲程度。
为解决上述技术问题,本申请提供的第三个技术方案为:提供一种电子装置,所述电子装置包括上述任一项所述的埋入式电路板。
本申请的有益效果,区别与现有技术,本申请提供的埋入式电路板包括多层线路层;其中,多层线路层中的相邻两个中间层之间设置有第 一芯板及第二芯板,第一芯板及第二芯板上开设有槽体,多个元器件分别对应的设置在多个槽体中。以此在埋入式电路板进行压合时或压合后,能够使第一芯板及第二芯板外侧的线路层之间的应力相互抵消,以防止电路板发生翘曲。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。其中:
图1是本申请埋入式电路板的第一实施例的结构示意图;
图2a及图2b为图1所示的第一功率器件互联结构示意图及第二功率器件互联结构示意图;
图3是本申请埋入式电路板的第二实施例的结构示意图;
图4是本申请埋入式电路板的第三实施例的流程示意图;
图5是本申请电子装置的一实施例的结构示意图。
【具体实施方式】
下面将结合本申请实施方式中的附图,对本申请实施方式中的技术方案进行清楚、完整地描述,显然,所描述的实施方式仅仅是本申请一部分实施方式,而不是全部实施方式。基于本申请中的实施方式,本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施方式,都属于本申请保护的范围。
请参见图1,为本申请埋入式电路板的第一实施例的结构示意图。本实施例的埋入式电路板具有多层线路层,除多层线路层外还包括第一芯板11及第二芯板12。第一芯板11及第二芯板12位于多层线路层的相邻的中间层13及中间层14之间。可以理解的,第一芯板11及第二芯板12及中间层13、14之间分别通过半固化片粘合。本实施例以两层线路层为例进行说明。
在本实施例中,第一芯板11及第二芯板12上均开设有多个槽体,且槽体中设置有多个元器件15。第一芯板11及第二芯板12之间通过半固化片21粘合,在一实施例中,半固化片为1080半固化片,为了提高第一芯板11及第二芯板12之间的粘合性,可以设置多层1080半固化片。具体地,本实施例中,第一芯板11上设置有第一槽体组,第二芯板12对应第一槽体组的位置处设置有第二槽体组;元器件15包括第一功率器件151及第二功率器件152,第一功率器件151设置于第一槽体组中的各自槽体内,第二功率器件152设置于第二槽体组中的各自槽体内。本实施例中一个槽体内设置一个元器件15,在另一实施例中,一个槽体内还可以设置多个元器件15。
本实施例中第一芯板11及第二芯板12中的第一槽体组及第二槽体组可以为贯穿第一芯板11及第二芯板的通槽,还可以为不贯穿第一芯板11及第二芯板12的盲槽。本实施例所述的中间层13及中间层14为使用焊料通过焊接的方式直接焊接在第一功率器件151及第二功率器件152的表面。在另一实施例中,中间层13及中间层14还可以通过半固化片压合在第一功率器件151及第二功率器件152的表面。图1所示实施例的结构示意图为使用焊料通过焊接的方式直接焊接在第一功率器件151及第二功率器件152的表面为例进行说明。
在一实施例中,位于第一槽体组内的第一功率器件151之间互联,位于第二槽体组内的第二功率器件152之间互联。第一功率器件151及第二功率器件152的表面均具有连接端子(图未示),在第一槽体组中的各个第一功率器件151进行互联时,可通过与第一功率器件151相邻的中间层13及铜层112进行实现连接。在第二槽体组中的各个第二功率器件152进行互联时,可通过与第二功率器件152相邻的中间层14及铜层122进行实现连接。
具体地,在一实施例中,所有第一功率器件151在第一槽体组中的各个槽体内阵列排布,位于同一行的第一功率器件151之间相互串联形成多个功率器件组。多个功率器件组相互并联。
具体请参见图2a,为第一功率器件151之间互联的一实施方式的结 构示意图。第一功率器件151包括第一连接端子1511、第二连接端子1512及第三连接端子1513。其中,第一连接端子1511位于第一功率器件151靠近第一芯板11的铜层112的一表面,第二连接端子1512及第三连接端子1513位于第一功率器件151靠近中间层13的一侧。其中,在位于同一行的第一功率器件151之间相互串联形成多个功率器件组时,一第一功率器件151的第一连接端子1511连接同一行相邻的第一功率器件151的第二连接端子1512,以将同一行的第一功率器件151相互串联形成多个功率器件组。具体地,通过导电孔113将一第一功率器件151的第一连接端子1511与另一第一功率器件151的第二连接端子1512连接。在形成功率器件组后,将第一功率器件151的第二连接端子1512连接靠近第一芯板11的中间层13,另一第一功率器件151的第一连接端子1511连接第一芯板11远离中间层13的表面的铜层112,以将所述多个功率器件组并联。
可选的,在将多个第一功率器件151互联时,其第一连接端子1511、第二连接端子1512可以连接同一线路层的同一线路网络,也可以连接不同线路网络。进一步地,第一连接端子1511、第二连接端子1512可以连接不同层的不同线路网络。
在本实施例中,所有第一功率器件151的第三连接端子1513连接第一芯板11远离第二芯板12一侧的线路层中的一层。具体地,在一实施例中,第三连接端子1513可以与第一连接端子1511、第二连接端子1512连接同一层线路层,也可以连接不同层线路层。
在一具体实施方式中,第一功率器件151的第一连接端子1511、第二连接端子1512及第三连接端子1513对应可以为源极、漏极及栅极。
所有第二功率器件152在第二槽体组中的各个槽体内阵列排布,位于同一行的第二功率器件152之间相互串联形成多个功率器件组,多个功率器件组相互并联。
具体请参见图2b,为第二功率器件152之间互联的一实施方式的结构示意图。第二功率器件152包括第一连接端子1521、第二连接端子1522及第三连接端子1523。其中,第一连接端子1521位于第二功率器 件152靠近第二芯板12的铜层122的一表面,第二连接端子1522及第三连接端子1523位于第二功率器件152靠近中间层14的一侧。其中,在位于同一行的第二功率器件152之间相互串联形成多个功率器件组时,一第二功率器件152的第一连接端子1521连接同一行相邻的第二功率器件152的第二连接端子1522,以将同一行的第二功率器件152相互串联形成多个功率器件组。具体地,通过导电孔123将一第二功率器件152的第一连接端子1521与另一第二功率器件152的第二连接端子1522连接。在形成功率器件组后,将第二功率器件152的第二连接端子1522连接靠近第二芯板12的中间层14,另一第二功率器件152的第一连接端子1521连接第二芯板12远离中间层14的表面的铜层122,以将所述多个功率器件组并联。
可选的,在将多个第二功率器件152互联时,其第一连接端子1521、第二连接端子1522可以连接同一线路层的同一线路网络,也可以连接不同线路网络。进一步地,第一连接端子1521、第二连接端子1522可以连接不同层的不同线路网络。
在本实施例中,所有第二功率器件152的第三连接端子1523连接第二芯板12远离第一芯板11一侧的线路层中的一层。具体地,在一实施例中,第三连接端子1523可以与第一连接端子1521、第二连接端子1522连接同一层线路层,也可以连接不同层线路层。
在一具体实施方式中,第二功率器件152的第一连接端子1521、第二连接端子1522及第三连接端子1523对应可以为源极、漏极及栅极。
在本实施例中,第一芯板11及第二芯板12均只有一表面设置有铜层,如图1所述,第一芯板11靠近第二芯板12的一表面具有铜层112,第二芯板12靠近第一芯板11的一表面具有铜层122。第一芯板11及第二芯板12没有铜层的表面与中间层连接。具体地,第一芯板11远离第二芯板12的未设置铜层的一表面与中间层13接触,第二芯板12远离第一芯板11的未设置铜层的一表面与中间层14接触。
在本实施例中,多个第一功率器件151及多个第二功率器件152对称设置,具体地,多个第一功率器件151及多个第二功率器件152沿第 一芯板11和第二芯板12之间的平面为镜面对称设置。以此在进行压合时,能够减少第一功率器件151及第二功率器件152形变引起的电路板的翘曲。
进一步地,在本实施例中,第一芯板11、中间层13与第二芯板12、中间层14对称设置。具体地,第一芯板11、中间层13与第二芯板12、中间层14沿第一芯板11和第二芯板12之间的平面为镜面对称设置。
在本实施例中,中间层13及中间层14为多层线路层的外层线路层,为了便于在埋入式电路板表面贴装其他电子器件,且实现电路板的高密度布线,中间层13及中间层14的厚度为60-80um。若中间层13及中间层14的外侧还具有线路层时,为了便于大电流的传输,中间层13及中间层14的厚度为150-200um。
本实施例所述的第一芯板11及第二芯板12均为覆铜板,其由半固化片111、121及铜层112、铜层122组成。其是制作电路板的基础材料。
本实施例提供的埋入式电路板,为了解决在压合过程中电路板发生翘曲,使电路板不平整的问题,将埋入式电路板设置为对称结构,以此在进行压合时,对称线两边的电路板所产生的应力可以相互抵消,进而防止电路板发生翘曲,使得电路板更加平整。
请参见图3,为本申请埋入式电路板的第二实施例的结构示意图。本实施例与图1所示的第一实施例相比,区别在于:本实施例所示的埋入式电路板在第一芯板11远离第二芯板12的一侧还具有第三芯板15,在第二芯板12远离第一芯板11的一侧还具有第四芯板16。
可以理解的,在第一芯板11远离第二芯板12的一侧设置第三芯板15时,可以通过锡焊料直接将第三芯板15焊接在第一芯板11的表面,还可以通过半固化片将第三芯板15与第一芯板11粘合。在第二芯板12远离第一芯板11的一侧设置第四芯板16时,同样可以通过锡焊料直接将第四芯板16焊接在第二芯板12的表面,还可以通过半固化片将第四芯板16与第二芯板12粘合,其只要能够满足第一芯板11、第三芯板15沿第一芯板11与第二芯板12之间的平面与第二芯板12及第四芯板16对称即可,在此不再赘述。
图3所示的埋入式电路板包括一层第三芯板15,及一层第四芯板16,在另一实施方式中,第三芯板15及第四芯板16可以为多层。
进一步地,本实施例提供的第三芯板15及第四芯板16的两表面均覆以铜箔层。如图2所示,第三芯板15包括半固化片152及位于半固化片152两侧的铜层151及铜层153;第四芯板16包括半固化片162及位于半固化片162两侧的铜层161及铜层163。在本实施例中,为了使埋入式电路板在应用中能够实现大电流传输,第三芯板15两表面的铜层151、153及第四芯板16两表面的铜层161、163均为厚铜层,其厚度为150-200um。优选地,在一实施例中,第三芯板15两表面的铜层151、153及第四芯板16两表面的铜层161、163均为175μm。
具体地,本实施例所述的第三芯板15及第四芯板16的各个铜层厚度相同,且其能够沿第一芯板11及第二芯板12之间的平面为镜面对称。以此能够在压合过程中使上下两面产生的应力相互抵消,防止电路板发生翘曲,进而使埋入式电路板的表面更加平整。
具体地,本实施例所示的埋入式电路板还包括位于第三芯板15远离第一芯板11的一侧的中间层13,及位于第四芯板16远离第二芯板12的一侧的中间层14。在本实施例中,中间层13及中间层14位于埋入式电路板的外层,为了便于在埋入式电路板的外侧贴装其余电子器件,并能够实现在埋入式电路板的外侧大密度布线,中间层13及中间层14的厚度为60-80um,优选地,在一实施例中,中间层13及中间层14的厚度为66um、70um、73um或75um。
在本实施例中,中间层13、第一芯板11、第三芯板15与中间层14、第二芯板12、第四芯板16对称。具体地,中间层13、第一芯板11、第三芯板15与中间层14、第二芯板12、第四芯板16沿第一芯板11及第二芯板12之间的平面为镜面对称设置。
可选的,在一实施例中,第一芯板11、中间层13、第三芯板15还可以沿第一芯板11与第二芯板12之间的中心点旋转对称。
可以理解的,为了实现埋入式电路板中各个铜层之间的导通,本申请所述的埋入式电路板中间的各层之间设置有导通孔(图未示)。进一 步地,埋入式电路板中设置的各个导通孔也沿第一芯板11及第二芯板之间的镜面对称设置。
本实施例提供的埋入式电路板,嵌入元器件的第一芯板及第二芯板及第一芯板与第二芯板外侧的各个线路层对称设置,以此在制作电路板完成后进行压合时,能够减小电路板的翘曲。另外,为了使埋入式电路板在应用中适用于大电流传输,本申请提供的埋入式电路板中包括多层厚铜层。
请参见图4,为本申请埋入式电路板的第三实施例的结构示意图。与上述图3所示的第二实施例相比,区别在于:本实施例所示的埋入式电路板还包括用于将中间层13、第三芯板15、第一芯板11及第二芯板12、第四芯板16、中间层14进行导通的通孔17。通孔17将埋入式电路板的所有线路层导通。可以理解的,在不需要进行导通的位置处,设置隔离环。在此不再赘述。
本实施例所述的埋入式电路板还包括用于导通中间层13、第三芯板15及第一芯板11的盲孔18,及用于导通中间层14、第四芯板16及第二芯板12的盲孔19。在本实施例中,通孔17、盲孔18及盲孔19沿第一芯板11及第二芯板12之间的平面对称设置。
在本申请提供的电路板中,还有其他用于导通线路层的导通孔,其中各个导通孔可以沿第一芯板11及第二芯板12之间的平面对称设置,也可以不对称设置,只要能够使埋入式电路板表面保持平整即可。在此不再赘述。
本申请提供的如图1至图4所示的埋入式电路板可应用于移动设备、汽车设备、基站设备或传感组件中。由于其150-200um的铜层设置,在使用中,能够支持大电流的传输。
本申请提供的埋入式电路板,第一芯板及第二芯板设置在多层电路板的相邻两中间层之间,元器件设置在第一芯板及第二芯板的槽体中,以此设置的埋入式电路板在进行压合时,第一芯板及第二芯板外侧的线路层之间的应力相互抵消,能够避免电路板发生翘曲进而使电路板表面不平整。
请参见图5,为本申请电子装置的一实施例的结构示意图。本申请提供的电子装置包括上述图1至图4中任一实施例所述的埋入式电路板51。本申请提供的电子装置可以为移动设备、汽车设备、基站设备或传感组件。可选的,本申请提供的电子装置在应用中能够支持大电流传输。
以上仅为本申请的实施方式,并非因此限制本申请的专利范围,凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本申请的专利保护范围内。

Claims (15)

  1. 一种埋入式电路板,其中,至少包括:
    多层线路层;
    至少第一芯板和第二芯板,设置在所述线路层的相邻的两个中间层之间;
    所述第一芯板、所述第二芯板上开设有多个槽体;
    多个元器件,对应设置在多个所述槽体中。
  2. 根据权利要求1的埋入式电路板,其中,
    多个所述元器件对称设置。
  3. 根据权利要求2的埋入式电路板,其中,
    多个所述元器件以所述第一芯板和所述第二芯板之间的平面为镜面对称设置。
  4. 根据权利要求1所述的埋入式电路板,其中,
    所述第一芯板及所述第二芯板至少相互邻近的各自表面设有铜层,且所述第一芯板及所述第二芯板远离所述中间层的所述铜层的厚度为60-80um,所述中间层为一层或多层,且所述中间层为铜层,所述中间层的厚度为150-200um。
  5. 根据权利要求4所述的埋入式电路板,其中,
    各层所述线路层的厚度以所述第一芯板和所述第二芯板之间的平面为镜面对称设置。
  6. 根据权利要求1所述的埋入式电路板,其中,
    所述第一芯板背对所述第二芯板一侧的所述多层线路层之间设有至少第三芯板,所述第二芯板背对所述第一芯板一侧的所述多层线路层之间设有至少第四芯板;
    所有所述第一芯板、所述第三芯板构成的第一芯板组和所有所述第二芯板、所述第四芯板构成的第二芯板组以所述第一芯板和所述第二芯板之间的平面为镜面对称设置。
  7. 根据权利要求1所述的埋入式电路板,其中,
    所有埋入式电路板以所述第一芯板和所述第二芯板之间的平面为 镜面对称设置;或
    所有埋入式电路板以所述第一芯板和所述第二芯板之间的中点为中心旋转对称设置。
  8. 根据权利要求1所述的埋入式电路板,其中,
    所述多层线路层包括外层线路层,所述外层线路层位于所述中间层的外侧,且所述外层线路层的厚度为60-80um,所述中间层的厚度为150-200um,自所述中间层至所述外层线路层之间的所有线路层的厚度均为150-200um。
  9. 根据权利要求1至8任一项所述的埋入式电路板,其中,
    所述第一芯板上设置有第一槽体组,所述第二芯板对应所述第一槽体组的位置处设置有第二槽体组;所述元器件包括第一功率器件及第二功率器件,所有所述第一功率器件设置于所述第一槽体组中的各自槽体内,所有所述第二功率器件设置于所述第二槽体组中的各自槽体内;
    位于所述第一槽体组内的所述第一功率器件之间互联,位于所述第二槽体组内的所述第二功率器件之间互联。
  10. 根据权利要求9所述的埋入式电路板,其中,
    所有所述第一功率器件在所述第一槽体中的各个槽体内阵列排布,位于同一行的所述第一功率器件之间相互串联形成多个功率器件组,所述多个功率器件组相互并联;
    所有所述第二功率器件在所述第二槽体中的各个槽体内阵列排布,位于同一行的所述第二功率器件之间相互串联形成多个功率器件组,所述多个功率器件组相互并联。
  11. 根据权利要求10所述的埋入式电路板,其中,所述第一功率器件靠近所述中间层的一侧具有第二连接端子及第三连接端子,另一侧具有第一连接端子;
    其中,一所述第一功率器件的所述第一连接端子连接同一行相邻的所述第一功率器件的所述第二连接端子,以将同一行的所述第一功率器件相互串联形成多个功率器件组;其中,所述第一功率器件的所述第二连接端子连接靠近所述第一芯板的所述中间层,同一行相邻的所述第一 功率器件的所述第一连接端子连接所述第一芯板远离所述中间层的表面的铜层,以将所述多个功率器件组并联;
    所述第二功率器件靠近所述中间层的一侧具有第二连接端子及第三连接端子,另一侧具有第一连接端子;
    其中,一所述第二功率器件的所述第一连接端子连接同一行相邻的所述第二功率器件的所述第二连接端子,以将同一行的所述第二功率器件相互串联形成多个功率器件组;其中,所述第二功率器件的所述第二连接端子连接靠近所述第二芯板的所述中间层,同一行相邻的所述第二功率器件的所述第一连接端子连接所述第二芯板远离所述中间层的表面的铜层,以将所述多个功率器件组并联。
  12. 根据权利要求11所述的埋入式电路板,其中,
    所有所述第一功率器件的所述第三连接端子连接所述第一芯板远离所述第二芯板一侧的线路层中的一层;
    所有所述第二功率器件的所述第三连接端子连接所述第二芯板远离所述第一芯板一侧的线路层中的一层。
  13. 根据权利要求12所述的埋入式电路板,其中,所述埋入式电路板应用于移动设备、汽车设备、基站设备或传感组件中。
  14. 一种埋入式电路板,其中,至少包括:
    多层线路层;
    芯板,设置在所述多层线路层的中间层;
    其中,所述芯板开设有多个槽体;
    多个元器件,对应设置在多个所述槽体中;
    其中,所述埋入式电路板以所述芯板为中心至少在部分结构或部分物理量上对称设置,以使得所述埋入式电路板在温度变化时应力均衡,降低翘曲程度。
  15. 一种电子装置,其中,所述电子装置包括上述权利要求1~13任一项所述的埋入式电路板或权利要求14所述的埋入式电路板。
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EP3958656A1 (en) 2022-02-23
US11632861B2 (en) 2023-04-18
CN112203415A (zh) 2021-01-08

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