CN112203415A - 埋入式电路板及其制备方法 - Google Patents

埋入式电路板及其制备方法 Download PDF

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Publication number
CN112203415A
CN112203415A CN202010645933.1A CN202010645933A CN112203415A CN 112203415 A CN112203415 A CN 112203415A CN 202010645933 A CN202010645933 A CN 202010645933A CN 112203415 A CN112203415 A CN 112203415A
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Prior art keywords
electronic device
circuit board
thermal expansion
layer
embedded
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Granted
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CN202010645933.1A
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CN112203415B (zh
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黄立湘
王泽东
缪桦
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Shennan Circuit Co Ltd
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Shennan Circuit Co Ltd
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Priority to PCT/CN2020/127019 priority Critical patent/WO2022007276A1/zh
Publication of CN112203415A publication Critical patent/CN112203415A/zh
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    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
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    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/08—Magnetic details
    • H05K2201/083—Magnetic materials
    • H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
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    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

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Abstract

本申请涉及电路板技术领域，公开了一种埋入式电路板及其制备方法，该埋入式电路板包括：交替层叠设置的若干层子体和若干介质层，其中至少一层子体开设有槽体；电子器件，嵌设在槽体内；其中，邻近电子器件的介质层的热膨胀系数小于远离电子器件的介质层的热膨胀系数。通过上述方式，本申请能够防止因介质层热胀冷缩而对电子器件所在子体产生明显应力而导致子体变形、电子器件断裂或者脱落的情况。同时，由于电路板上并不采用低热膨胀系数的材料作为各层介质层材料，因此本申请能够在使电路板尽量保持平整的状态的前提下，降低生产成本。

Description

埋入式电路板及其制备方法
技术领域
本申请涉及电路板技术领域，特别是涉及一种埋入式电路板及其制备方法。
背景技术
电路板，常使用英文缩写PCB(Printed circuit board)，是重要的电子部件，是电子元件的支撑体，是电子元器件线路连接的提供者。印刷电路板几乎会出现在每一种电子设备当中。目前电路板在热加工制程中会因为温度的变化影响而产生翘曲或膨胀的情况，从而造成包含该电路板的电路板件产生变形。
本申请的发明人在长期研发过程中，发现若使用低热膨胀系数的材料作为各层介质层或各层芯板材料，虽然能够避免电路板发生翘曲，但由于低热膨胀系数材料价格过高，增加了生产成本。
发明内容
本申请主要解决的技术问题是提供一种埋入式电路板及其制备方法，能够在使电路板尽量保持平整的状态的前提下，降低生产成本。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种埋入式电路板，包括：交替层叠设置的若干层子体和若干介质层，其中至少一层子体开设有槽体；电子器件，嵌设在槽体内；其中，邻近电子器件的介质层的热膨胀系数小于远离电子器件的介质层的热膨胀系数。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种埋入式电路板的制备方法，制备方法包括：提供若干层子体，其中至少一层子体开设有槽体；将电子器件嵌设到槽体内；将若干层子体与若干层交替层叠设置，其中，邻近电子器件的介质层的热膨胀系数小于远离电子器件的介质层的热膨胀系数；压合各层子体与介质层以固定子体和电子器件。
本申请的有益效果是：本申请的埋入式电路板中，邻近电子器件的介质层的热膨胀系数小于远离电子器件的介质层的热膨胀系数，即越邻近电子器件的介质层的热膨胀系数越小，能够防止因介质层热胀冷缩而对电子器件所在子体产生明显应力而导致子体变形、电子器件断裂或者脱落的情况。同时，由于电路板上并不采用低热膨胀系数的材料作为各层介质层材料，因此本申请能够在使电路板尽量保持平整的状态的前提下，降低生产成本。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本申请埋入式电路板一实施例的剖面结构示意图；
图2是本申请埋入式电路板另一实施例的剖面结构示意图；
图3是本申请埋入式电路板的制备方法一实施例的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、固有的其它步骤或单元。
参阅图1，本申请实施例提供一种埋入式电路板100，该埋入式电路板100包括：交替层叠设置的若干层子体10、若干介质层20以及电子器件30。
具体地，若干层子体10和若干介质层20在整个埋入式电路板100中起到支撑作用。其中，若干层子体10可以为无铜芯板或覆铜板，覆铜板中的铜层具有良好的导电性能，是印刷电路板100最常用的线路材料。对每一子体10进行图案化处理，即可得到所需要的线路图形，并根据功能设计可以将金属铜层和分为信号层和接地层；其中信号层的图案较接地层的图案复杂。通常，信号层为用于形成电子器件30之间的电连接的多条金属线路所在的层；接地层用于与地连接，通常为大面积连续金属区域的层。
上述其中，电子器件30可以为封装或未封装(即没有金属底座、塑封胶或陶瓷壳)的集成电路、芯片、电阻、电容、三级管、IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)和MOS管(metal oxide semiconductor，场效应晶体管)。
至少一层子体10B开设有槽体101，电子器件30嵌设在槽体101内。其中，槽体101的数量可以与电子器件30的数量相同，此时一个槽体101中设置一个电子器件30，当然，槽体101的数量也可以与电子器件30的数量不同，具体为槽体101的数量小于电子器件30的数量，此时两个或两个以上的电子器件30可以同时设置在一个槽体101中。
槽体101的制作工艺采用控深铣，所谓控深铣就是控制Z方向的深度的一种铣床技术，由于受到铣床Z方向控深铣精度的限制。其中，槽体101的长度、宽度的都大于所需埋入芯片的尺寸，以使槽体101能足够容纳所需埋入的芯片。槽体101的形状可以为规则的长方体，或为梯形体，或阶梯状，可以根据实际的工艺要求进行设计，在此不做限制，说明书附图中为了较直观的表述，统一的将槽体101表示成长方体的形状。
其中，邻近电子器件30的介质层20B、20C的热膨胀系数小于远离电子器件30的介质层20A、20D的热膨胀系数。
具体地，含有该埋入式电路板100的半导体器件在工作时，半导体器件会辐射出热，并且所产生的热又会通过外侧介质层20A、20D传导到层间介质层20B、20C以及其它子体10A、10B、10C，因此，随着温度的增加，介质层20就会发生热膨胀。由于本实施例的埋入式电路板100中，邻近电子器件30的介质层20B、20C的热膨胀系数小于远离电子器件30的介质层20A、20D的热膨胀系数，即越邻近电子器件30的介质层20B、20C的热膨胀系数越小，能够防止因介质层20B、20C骤然的热胀冷缩而导致子体10B变形甚至脱落的情况。
通过上述方式，本实施例的埋入式电路板100中，邻近电子器件30的介质层20的热膨胀系数20B、20C小于远离电子器件30的介质层20的热膨胀系数20A、20D，即越邻近电子器件30的介质层20的热膨胀系数越小，能够防止因介质层20B、20C热胀冷缩而导致子体10B变形甚至脱落的情况。同时，由于电路板100上并不采用低热膨胀系数的材料作为各介质层材料，因此本申请能够在使电路板100尽量保持平整的状态的前提下，降低生产成本。
参阅图2，埋入式电路板100还包括：封装体70。该封装体70包覆在电子器件30外周，以使电子器件30与槽体101的侧壁间隔设置，封装体70的热膨胀系数小于或等于相邻介质层20的热膨胀系数。
具体地，封装体70填充于电子器件30与槽体101的侧壁之间并密封电子器件30，其中封装体70内设置有导电结构(图未示出)，且导电结构用于电连接电子器件30和金属线路层或导电孔60，封装体70内的导电结构可为金属片。该金属片可以为纯金属制成，用到的金属材料包括但不限于铜、铜合金、铝、铝合金、铁、铁合金、镍、镍合金、金、金合金、银、银合金、铂族、铂族合金、铬、铬合金、镁、镁合金、钨、钨合金、钼、钼合金、铅、铅合金、锡、锡合金、铟、铟合金、锌或锌合金等。在另一实施例中，该金属片的材料也可以由金属基块和导电石墨片组成。由于导电石墨片的热阻较普通金属及合金的小，可以在金属中嵌入导电石墨片使得导热更加迅速。
通过上述方式，本实施例的埋入式电路板100中，封装体70的热膨胀系数小于或等于相邻介质层20的热膨胀系数，由于封装体70和相邻介质层20具有非常接近的热膨胀系数以及它们随温度增加而膨胀的程度也非常接近，因此不会产生由于热膨胀系数差异太大而引起的对电子器件30所在子体10的明显应力，有效防止子体10被挤压而弯曲变形，使电路板100尽量保持平整的状态。
进一步地，封装体70与相邻介质层20B、20C的热膨胀系数之间的差值为0-5，例如为0、1、2、3、4或者5。
在一实施例中，封装体70的热膨胀系数范围为1-17，例如为1、5、7、10、13或者17。封装体70的热膨胀系数小于或等于嵌设有电子器件30的子体10B的热膨胀系数。
优选地，封装体70的热膨胀系数范围为3-12，例如为3、7或者12。封装体70的热膨胀系数等于嵌设有电子器件30的子体10B的热膨胀系数。
进一步地，为了保证封装体70可以填满电子器件30与槽体101之间的间隙以保证埋入式电路板100的整体强度，封装体70的直径范围为1-30um，具体为1um、10um、20um或30um。
通过上述方式，本实施例的埋入式电路板100中，封装体70的热膨胀系数小于或等于嵌设有电子器件30的子体10B的热膨胀系数，由于封装体70和嵌设有电子器件30的子体10B具有非常接近的热膨胀系数以及它们随温度增加而膨胀的程度也非常接近，因此不会产生由于热膨胀系数差异太大而引起的对电子器件30明显应力，有效防止电子器件30发生断裂或者电子器件30从子体10上剥落。
在一实施例中，若干介质层20的热膨胀系数沿远离电子器件30的方向逐渐增加，沿远离电子器件30的方向的相邻两层介质层20B、20A或相邻两层介质层的20C、20D的热膨胀系数之间的差值为2-5，例如为2、3、4或者5。
通过上述方式，本实施例中的埋入电路板100中，虽然远离电子器件30的介质层20A、20D的热膨胀系数虽然大于邻近电子器件30的介质层20B、20C的热膨胀系数，但各个子体10相邻两侧的介质层20B、20A或相邻两层介质层的20C、20D具有相近水平的热膨胀系数，因此该子体10A、10B、10D受相邻两侧的介质层20挤压而产生弯曲变形程度较小，进而能够减小远离电子器件30的子体10经过热加工制程后的翘曲程度，使电路板100尽量保持平整的状态，提升裁切电路板100件的方便性及良率。
其中，上述介质层20的热膨胀系数范围为1-27，例如为1、5、7、10、20或者27。同时为了保证介质层20可以填满相邻子体10之间的间隙以保证埋入式电路板100的整体强度，介质层20的厚度范围为60-300um，具体为60um、100um、200um或300um。
在一实施例中，介质层20和封装体70的材料为树脂、molding硅胶中的一种绝缘材料或任意组合。
具体地，树脂是指受热后有软化或熔融范围，软化时在外力作用下有流动倾向，常温下是固态、半固态，有时也可以是液态的有机聚合物。树脂可以为环氧树脂、有机硅树脂、聚酰亚胺树脂、酚醛树脂、聚氨酯、丙烯酸树脂等胶黏剂体系。
molding硅胶是一种无色透明液体，能够在150℃以上高温下进行硫化，固化时具有一定的透气性及弹性，主要具有耐温特性、耐候性、电气绝缘性、生理惰性、低表面张力和低表面能。
进一步地，最外侧介质层20的材料可以是高散热材料、磁性材料或者低传输损耗的材料。当最外侧介质层20A、20D的材料是高散热材料时，可以提高埋入式电路板100的散热性能，当最外侧介质层20A、20D的材料是磁性材料时，可以起到电磁屏蔽的作用，当最外侧介质层20A、20D的材料是低传输损耗的材料时，有利于射频信号、高频信号的传输。
在一实施例中，埋入式电路板100还包括：第一线路层40和第二线路层50，且第一线路层40、第二线路层50分别位于电路板100的相背两外侧。其中，电子器件30具有连接端子，电子器件30的连接端子与第一线路层40和/或第二线路层50电连接。
具体地，在埋入式电路板100上还可以开设导通孔。在本实施例中，该导通孔贯穿各层子体10和各层介质层20，该导通孔内还设置有电连接子体10的信号层和/或接地层的导电层，以得到导电孔60。在本实施例中，可通过电镀的方式对导通孔进行金属化处理。具体地，可在含有欲镀金属的盐类溶液中，以安导通孔的金属为阴极，通过电解作用，使镀液中欲镀金属的阳离子在导通孔的金属表面沉积出来，从而形成导电层。常用的用于电镀的金属包括但不限于钛钯、锌、镉、金或黄铜、青铜等。当然，在其他实施例中，还可以通过例如涂覆的方式实现该导通孔的金属化处理。
各层子体10和各层介质层20中开设有导电孔60，电子器件30的连接端子通过导电孔60与第一线路层40和/或第二线路层50电连接。在此不做限定。或者，电子器件30的连接端子可以与第一线路层40和/或第二线路层50直接接触以实现电连接。
可选地，设置一个或一个以上元器件(图未示出)在第一线路层40远离槽体101的一侧上或第二线路层50远离槽体101的一侧上，还可以有多个元器件分别设置在第一线路层40远离槽体101的一侧上、第二线路层50远离槽体101的一侧上，元器件通过第一线路层40或第二线路层50实现与电子器件30电连接，其中，元器件可以是芯片、电容元件、电阻元件、电源器件中的一种或几种。
参阅图3，图3是本申请埋入式电路板100的制备方法一实施例的流程示意图，该制备方法包括以下步骤：
S10：提供若干层子体10。其中至少一层子体10开设有槽体101。
在本实施例中，可在至少一层子体10上通过控深铣工艺以形成贯穿子体10的槽体101，其成型步骤少，只需选定加工基准一次，且可提高产品的加工精度。槽体101的最大横截面积应当大于电子器件30的最大横截面积。
S20：将电子器件30嵌设到槽体101内。
S30：将若干层子体10与若干层交替层叠设置。
其中，邻近电子器件30的介质层20B、20C的热膨胀系数小于远离电子器件30的介质层20A、20D的热膨胀系数；
S40：压合各层子体10与介质层20以固定子体10和电子器件30。
在制备过程中，将若干层子体10与若干介质层20交替层叠设置后进行压合而使若干层子体10成为一个整体，可选在，在压合后还可进行固化以保证整体的强度。
通过上述方式，本实施例的埋入式电路板100中，邻近电子器件30的介质层20的热膨胀系数20B、20C小于远离电子器件30的介质层20的热膨胀系数20A、20D，即越邻近电子器件30的介质层20的热膨胀系数越小，能够防止因介质层20B、20C热胀冷缩而导致子体10B变形甚至脱落的情况。同时，由于电路板100上并不采用低热膨胀系数的材料作为各介质层材料，因此本申请能够在使电路板100尽量保持平整的状态的前提下，降低生产成本。
除非另作规定，否则本说明书中所述的本申请实施例的操作执行或实施顺序并非必要顺序。即，除非另外指明，否则操作可以任何次序执行，并且本申请的实施例可包括另外或比本说明书公开的那些少的操作。例如，预计在另一操作之前、同时、或之后执行或进行特定操作在本申请的各个方面的范围之内。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

1.一种埋入式电路板，其特征在于，包括：
交替层叠设置的若干层子体和若干介质层，其中至少一层所述子体开设有槽体；
电子器件，嵌设在所述槽体内；
其中，邻近所述电子器件的所述介质层的热膨胀系数小于远离所述电子器件的所述介质层的热膨胀系数。
2.根据权利要求1所述的埋入式电路板，其特征在于，所述埋入式电路板还包括：
封装体，包覆在所述电子器件外周，以使所述电子器件与所述槽体的侧壁间隔设置，所述封装体的热膨胀系数小于或等于相邻所述介质层的热膨胀系数。
3.根据权利要求2所述的埋入式电路板，其特征在于，
所述封装体与相邻所述介质层的热膨胀系数之间的差值为0-5。
4.根据权利要求2所述的埋入式电路板，其特征在于，
所述封装体的热膨胀系数范围为1-17，所述封装体的热膨胀系数小于或等于嵌设有所述电子器件的所述子体的热膨胀系数。
5.根据权利要求4所述的埋入式电路板，其特征在于，
所述封装体的热膨胀系数范围为3-12，所述封装体的热膨胀系数等于嵌设有所述电子器件的所述子体的热膨胀系数。
6.根据权利要求1所述的埋入式电路板，其特征在于，
若干层所述介质层的热膨胀系数沿远离所述电子器件的方向逐渐增加，且沿远离所述电子器件的方向的相邻两层所述介质层的热膨胀系数之间的差值为2-5。
7.根据权利要求1所述的埋入式电路板，所述介质层的热膨胀系数范围为1-27。
8.根据权利要求2所述的埋入式电路板，其特征在于，
所述介质层和所述封装体的材料为树脂、molding硅胶中的一种绝缘材料或任意组合。
9.根据权利要求1所述的埋入式电路板，其特征在于，所述埋入式电路板还包括：
第一线路层和第二线路层，且所述第一线路层、所述第二线路层分别位于电路板的相背两外侧；
其中，所述电子器件具有连接端子，所述电子器件的连接端子与所述第一线路层和/或所述第二线路层电连接。
10.一种埋入式电路板的制备方法，其特征在于，所述制备方法包括：
提供若干层子体，其中至少一层所述子体开设有槽体；
将电子器件嵌设到所述槽体内；
将若干层所述子体与若干层交替层叠设置，其中，邻近所述电子器件的所述介质层的热膨胀系数小于远离所述电子器件的所述介质层的热膨胀系数；
压合各层所述子体与所述介质层以固定所述子体和所述电子器件。
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