KR102750432B1 - 통합 장치 패키지 - Google Patents

통합 장치 패키지 Download PDF

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KR102750432B1
KR102750432B1 KR1020237003430A KR20237003430A KR102750432B1 KR 102750432 B1 KR102750432 B1 KR 102750432B1 KR 1020237003430 A KR1020237003430 A KR 1020237003430A KR 20237003430 A KR20237003430 A KR 20237003430A KR 102750432 B1 KR102750432 B1 KR 102750432B1
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electronic component
die
carrier
article
integrated device
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Korean (ko)
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KR20230029960A (ko
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벨가셈 하바
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아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드
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Priority to KR1020247043566A priority Critical patent/KR20250010110A/ko
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Families Citing this family (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US10719762B2 (en) 2017-08-03 2020-07-21 Xcelsis Corporation Three dimensional chip structure implementing machine trained network
US10672663B2 (en) 2016-10-07 2020-06-02 Xcelsis Corporation 3D chip sharing power circuit
TWI892323B (zh) 2016-10-27 2025-08-01 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
KR102320673B1 (ko) 2016-12-28 2021-11-01 인벤사스 본딩 테크놀로지스 인코포레이티드 적층된 기판의 처리
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
KR20230156179A (ko) 2016-12-29 2023-11-13 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
WO2019090057A1 (en) * 2017-11-02 2019-05-09 Nextinput, Inc. Sealed force sensor with etch stop layer
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US10991804B2 (en) 2018-03-29 2021-04-27 Xcelsis Corporation Transistor level interconnection methodologies utilizing 3D interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10923413B2 (en) 2018-05-30 2021-02-16 Xcelsis Corporation Hard IP blocks with physically bidirectional passageways
KR102878117B1 (ko) 2018-06-13 2025-10-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 패드로서의 ｔｓｖ
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US12406959B2 (en) 2018-07-26 2025-09-02 Adeia Semiconductor Bonding Technologies Inc. Post CMP processing for hybrid bonding
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11296044B2 (en) 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
US11476213B2 (en) 2019-01-14 2022-10-18 Invensas Bonding Technologies, Inc. Bonded structures without intervening adhesive
US11387202B2 (en) 2019-03-01 2022-07-12 Invensas Llc Nanowire bonding interconnect for fine-pitch microelectronics
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US12374641B2 (en) 2019-06-12 2025-07-29 Adeia Semiconductor Bonding Technologies Inc. Sealed bonded structures and methods for forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US12113054B2 (en) 2019-10-21 2024-10-08 Adeia Semiconductor Technologies Llc Non-volatile dynamic random access memory
TW202522760A (zh) * 2019-10-29 2025-06-01 日商東京威力科創股份有限公司 附有晶片之基板的製造方法
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
KR20220120631A (ko) 2019-12-23 2022-08-30 인벤사스 본딩 테크놀로지스 인코포레이티드 결합형 구조체를 위한 전기적 리던던시
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
CN115943489A (zh) 2020-03-19 2023-04-07 隔热半导体粘合技术公司 用于直接键合结构的尺寸补偿控制
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US12199018B2 (en) 2020-09-18 2025-01-14 Intel Corporation Direct bonding in microelectronic assemblies
US11990448B2 (en) * 2020-09-18 2024-05-21 Intel Corporation Direct bonding in microelectronic assemblies
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
WO2022094587A1 (en) * 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
CN116635998A (zh) * 2020-10-29 2023-08-22 美商艾德亚半导体接合科技有限公司 直接键合方法和结构
EP3993021A1 (en) * 2020-11-03 2022-05-04 Infineon Technologies AG Method of manufacturing a bonded substrate stack
WO2022147430A1 (en) 2020-12-28 2022-07-07 Invensas Bonding Technologies, Inc. Structures with through-substrate vias and methods for forming the same
KR20230125309A (ko) 2020-12-28 2023-08-29 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 기판-관통 비아를 가지는 구조체 및 이를 형성하기위한 방법
JP7783896B2 (ja) 2020-12-30 2025-12-10 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 導電特徴部を備えた構造体及びその形成方法
WO2022160102A1 (zh) * 2021-01-26 2022-08-04 华为技术有限公司 芯片堆叠结构及其制备方法、芯片堆叠封装、电子设备
WO2023014616A1 (en) 2021-08-02 2023-02-09 Invensas Bonding Technologies, Inc. Protective semiconductor elements for bonded structures
KR20230025587A (ko) * 2021-08-13 2023-02-22 삼성전자주식회사 반도체 패키지 제조 방법
JP2023043671A (ja) * 2021-09-16 2023-03-29 キオクシア株式会社 半導体記憶装置及びその設計方法
EP4483406A1 (en) * 2022-02-24 2025-01-01 Adeia Semiconductor Bonding Technologies Inc. Bonded structures
JP2023137395A (ja) * 2022-03-18 2023-09-29 キオクシア株式会社 半導体装置及び半導体製造装置
US20230369070A1 (en) * 2022-05-12 2023-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method of manufacturing thereof
US20230395563A1 (en) * 2022-06-02 2023-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple non-active dies in a multi-die package
US20240186268A1 (en) * 2022-12-01 2024-06-06 Adeia Semiconductor Bonding Technologies Inc. Directly bonded structure with frame structure
US12341083B2 (en) 2023-02-08 2025-06-24 Adeia Semiconductor Bonding Technologies Inc. Electronic device cooling structures bonded to semiconductor elements
US20250079366A1 (en) * 2023-09-05 2025-03-06 Micron Technology, Inc. Semiconductor device with layered dielectric
US20250226308A1 (en) * 2024-01-08 2025-07-10 Micron Technology, Inc. Semiconductor device with backside connection mechanism and methods for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101901711B1 (ko) 2017-09-27 2018-09-27 삼성전기 주식회사 팬-아웃 반도체 패키지

Family Cites Families (612)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2626408B1 (fr) 1988-01-22 1990-05-11 Thomson Csf Capteur d'image a faible encombrement
JPH0272642A (ja) 1988-09-07 1990-03-12 Nec Corp 基板の接続構造および接続方法
JPH0344067A (ja) 1989-07-11 1991-02-25 Nec Corp 半導体基板の積層方法
US5019673A (en) 1990-08-22 1991-05-28 Motorola, Inc. Flip-chip package for integrated circuits
JPH04337694A (ja) 1991-05-15 1992-11-25 Nec Yamagata Ltd 電子部品保護用樹脂膜
CA2083072C (en) 1991-11-21 1998-02-03 Shinichi Hasegawa Method for manufacturing polyimide multilayer wiring substrate
US6008126A (en) 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
JPH07193294A (ja) 1993-11-01 1995-07-28 Matsushita Electric Ind Co Ltd 電子部品およびその製造方法
KR960009074A (ko) 1994-08-29 1996-03-22 모리시다 요이치 반도체 장치 및 그 제조방법
DE4433330C2 (de) 1994-09-19 1997-01-30 Fraunhofer Ges Forschung Verfahren zur Herstellung von Halbleiterstrukturen mit vorteilhaften Hochfrequenzeigenschaften sowie eine Halbleiterwaferstruktur
JP3979687B2 (ja) 1995-10-26 2007-09-19 アプライド マテリアルズ インコーポレイテッド ハロゲンをドープした酸化珪素膜の膜安定性を改良する方法
KR100274333B1 (ko) 1996-01-19 2001-01-15 모기 쥰이찌 도체층부착 이방성 도전시트 및 이를 사용한 배선기판
US5956605A (en) 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
US5729896A (en) 1996-10-31 1998-03-24 International Business Machines Corporation Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder
US6221753B1 (en) 1997-01-24 2001-04-24 Micron Technology, Inc. Flip chip technique for chip assembly
JP4032454B2 (ja) 1997-06-27 2008-01-16 ソニー株式会社 三次元回路素子の製造方法
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
US6049124A (en) 1997-12-10 2000-04-11 Intel Corporation Semiconductor package
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
JP2000100679A (ja) 1998-09-22 2000-04-07 Canon Inc 薄片化による基板間微小領域固相接合法及び素子構造
FR2787241B1 (fr) 1998-12-14 2003-01-31 Ela Medical Sa Composant microelectronique cms enrobe, notamment pour un dispositif medical implantable actif, et son procede de fabrication
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6782610B1 (en) 1999-05-21 2004-08-31 North Corporation Method for fabricating a wiring substrate by electroplating a wiring film on a metal base
JP3767246B2 (ja) 1999-05-26 2006-04-19 富士通株式会社 複合モジュール及びプリント回路基板ユニット
JP2001102479A (ja) 1999-09-27 2001-04-13 Toshiba Corp 半導体集積回路装置およびその製造方法
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP2001284520A (ja) 2000-04-04 2001-10-12 Matsushita Electric Ind Co Ltd 半導体チップ搭載用の配線基板、配線基板の製造方法、中継接続用の配線基板、半導体装置および半導体装置間接続構造
JP2001313350A (ja) 2000-04-28 2001-11-09 Sony Corp チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
US7247932B1 (en) 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
JP4322402B2 (ja) 2000-06-22 2009-09-02 大日本印刷株式会社 プリント配線基板及びその製造方法
JP3440057B2 (ja) 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
US6423640B1 (en) 2000-08-09 2002-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Headless CMP process for oxide planarization
US6507115B2 (en) 2000-12-14 2003-01-14 International Business Machines Corporation Multi-chip integrated circuit module
JP3420748B2 (ja) 2000-12-14 2003-06-30 松下電器産業株式会社 半導体装置及びその製造方法
US6686588B1 (en) 2001-01-16 2004-02-03 Amkor Technology, Inc. Optical module with lens integral holder
JP2002359345A (ja) 2001-03-30 2002-12-13 Toshiba Corp 半導体装置及びその製造方法
JP2002353416A (ja) 2001-05-25 2002-12-06 Sony Corp 半導体記憶装置およびその製造方法
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
TWI309074B (en) 2002-02-07 2009-04-21 Advanced Epitaxy Technology Method of forming semiconductor device
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US7319197B2 (en) 2002-05-23 2008-01-15 International Business Machines Corporation Structure of stacked vias in multiple layer electrode device carriers
US7573136B2 (en) 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
US7105980B2 (en) 2002-07-03 2006-09-12 Sawtek, Inc. Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics
JP4083502B2 (ja) 2002-08-19 2008-04-30 株式会社フジミインコーポレーテッド 研磨方法及びそれに用いられる研磨用組成物
JP4579489B2 (ja) 2002-09-02 2010-11-10 新光電気工業株式会社 半導体チップ製造方法及び半導体チップ
US7023093B2 (en) 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same
US6713857B1 (en) 2002-12-05 2004-03-30 Ultra Tera Corporation Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package
JP2004193493A (ja) 2002-12-13 2004-07-08 Nec Machinery Corp ダイピックアップ方法および装置
US7354798B2 (en) 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
TW586677U (en) 2003-01-22 2004-05-01 Via Tech Inc Stack structure of chip package
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
TWI239629B (en) 2003-03-17 2005-09-11 Seiko Epson Corp Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus
US6908027B2 (en) 2003-03-31 2005-06-21 Intel Corporation Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
TWI275168B (en) 2003-06-06 2007-03-01 Sanyo Electric Co Semiconductor device and method for making the same
US6873049B2 (en) 2003-07-31 2005-03-29 The Boeing Company Near hermetic power chip on board device and manufacturing method therefor
US6867073B1 (en) 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
US7183643B2 (en) 2003-11-04 2007-02-27 Tessera, Inc. Stacked packages and systems incorporating the same
US7205233B2 (en) 2003-11-07 2007-04-17 Applied Materials, Inc. Method for forming CoWRe alloys by electroless deposition
JP2005175423A (ja) 2003-11-18 2005-06-30 Denso Corp 半導体パッケージ
TWI228286B (en) 2003-11-24 2005-02-21 Ind Tech Res Inst Bonding structure with buffer layer and method of forming the same
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
KR100538158B1 (ko) 2004-01-09 2005-12-22 삼성전자주식회사 웨이퍼 레벨 적층 칩 접착 방법
US20050161808A1 (en) 2004-01-22 2005-07-28 Anderson Douglas G. Wafer, intermediate wafer assembly and associated method for fabricating a silicon on insulator wafer having an improved edge profile
DE102004013681B3 (de) 2004-03-18 2005-11-17 Infineon Technologies Ag Halbleitermodul mit einem Kopplungssubstrat und Verfahren zur Herstellung desselben
JP4865197B2 (ja) 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5354765B2 (ja) 2004-08-20 2013-11-27 カミヤチョウ アイピー ホールディングス 三次元積層構造を持つ半導体装置の製造方法
US20060057945A1 (en) 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US7566634B2 (en) 2004-09-24 2009-07-28 Interuniversitair Microelektronica Centrum (Imec) Method for chip singulation
US20060076634A1 (en) 2004-09-27 2006-04-13 Lauren Palmateer Method and system for packaging MEMS devices with incorporated getter
US7262492B2 (en) 2004-09-28 2007-08-28 Intel Corporation Semiconducting device that includes wirebonds
WO2006043122A1 (en) 2004-10-21 2006-04-27 Infineon Technologies Ag Semiconductor package and method to produce the same
TWI303864B (en) 2004-10-26 2008-12-01 Sanyo Electric Co Semiconductor device and method for making the same
FR2880184B1 (fr) 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
GB0505680D0 (en) 2005-03-22 2005-04-27 Cambridge Display Tech Ltd Apparatus and method for increased device lifetime in an organic electro-luminescent device
TWI242820B (en) 2005-03-29 2005-11-01 Siliconware Precision Industries Co Ltd Sensor semiconductor device and method for fabricating the same
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
JP4275096B2 (ja) 2005-04-14 2009-06-10 パナソニック株式会社 半導体チップの製造方法
US7354862B2 (en) 2005-04-18 2008-04-08 Intel Corporation Thin passivation layer on 3D devices
US7671449B2 (en) 2005-05-04 2010-03-02 Sun Microsystems, Inc. Structures and methods for an application of a flexible bridge
US7884483B2 (en) 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
JP4983049B2 (ja) 2005-06-24 2012-07-25 セイコーエプソン株式会社 半導体装置および電子機器
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7786572B2 (en) 2005-09-13 2010-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. System in package (SIP) structure
US7682937B2 (en) 2005-11-25 2010-03-23 Advanced Laser Separation International B.V. Method of treating a substrate, method of processing a substrate using a laser beam, and arrangement
KR100804392B1 (ko) 2005-12-02 2008-02-15 주식회사 네패스 반도체 패키지 및 그 제조 방법
US7193423B1 (en) 2005-12-12 2007-03-20 International Business Machines Corporation Wafer-to-wafer alignments
DE102005060081B4 (de) 2005-12-15 2007-08-30 Infineon Technologies Ag Elektronisches Bauteil mit zumindest einer Leiterplatte und mit einer Mehrzahl gleichartiger Halbleiterbausteine und Verfahren
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7781309B2 (en) 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
US20070158024A1 (en) 2006-01-11 2007-07-12 Symbol Technologies, Inc. Methods and systems for removing multiple die(s) from a surface
TWI299552B (en) 2006-03-24 2008-08-01 Advanced Semiconductor Eng Package structure
US7972683B2 (en) 2006-03-28 2011-07-05 Innovative Micro Technology Wafer bonding material with embedded conductive particles
JP4160083B2 (ja) 2006-04-11 2008-10-01 シャープ株式会社 光学装置用モジュール及び光学装置用モジュールの製造方法
JP4844216B2 (ja) * 2006-04-26 2011-12-28 凸版印刷株式会社 多層回路配線基板及び半導体装置
US7385283B2 (en) 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
US7554203B2 (en) 2006-06-30 2009-06-30 Intel Corporation Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture
US7750488B2 (en) 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
KR100809696B1 (ko) 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
TWI305036B (en) 2006-09-28 2009-01-01 Siliconware Precision Industries Co Ltd Sensor-type package structure and fabrication method thereof
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
JP2008130603A (ja) 2006-11-16 2008-06-05 Toshiba Corp イメージセンサ用ウェハレベルパッケージ及びその製造方法
JP5011981B2 (ja) 2006-11-30 2012-08-29 富士通株式会社 デバイス素子製造方法およびダイシング方法
US7812459B2 (en) 2006-12-19 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuits with protection layers
US8178963B2 (en) 2007-01-03 2012-05-15 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving through-hole and method of the same
US8178964B2 (en) 2007-03-30 2012-05-15 Advanced Chip Engineering Technology, Inc. Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
US20080165521A1 (en) 2007-01-09 2008-07-10 Kerry Bernstein Three-dimensional architecture for self-checking and self-repairing integrated circuits
US7803693B2 (en) 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
US7919410B2 (en) 2007-03-14 2011-04-05 Aptina Imaging Corporation Packaging methods for imager devices
US8609463B2 (en) 2007-03-16 2013-12-17 Stats Chippac Ltd. Integrated circuit package system employing multi-package module techniques
JP2008258383A (ja) 2007-04-04 2008-10-23 Spansion Llc 半導体装置及びその製造方法
EP2137757B1 (en) 2007-04-17 2015-09-02 Imec Method for reducing the thickness of substrates
JP4734282B2 (ja) 2007-04-23 2011-07-27 株式会社日立製作所 半導体チップおよび半導体装置
US8119500B2 (en) 2007-04-25 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer bonding
DE102007020656B4 (de) 2007-04-30 2009-05-07 Infineon Technologies Ag Werkstück mit Halbleiterchips, Halbleiterbauteil und Verfahren zur Herstellung eines Werkstücks mit Halbleiterchips
US7723159B2 (en) 2007-05-04 2010-05-25 Stats Chippac, Ltd. Package-on-package using through-hole via die on saw streets
TWI332790B (en) 2007-06-13 2010-11-01 Ind Tech Res Inst Image sensor module with a three-dimensional dies-stacking structure
US7553752B2 (en) 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
US20090001599A1 (en) 2007-06-28 2009-01-01 Spansion Llc Die attachment, die stacking, and wire embedding using film
US20090029274A1 (en) 2007-07-25 2009-01-29 3M Innovative Properties Company Method for removing contamination with fluorinated compositions
US8044497B2 (en) 2007-09-10 2011-10-25 Intel Corporation Stacked die package
US20090127667A1 (en) 2007-11-21 2009-05-21 Powertech Technology Inc. Semiconductor chip device having through-silicon-via (TSV) and its fabrication method
JP2009135348A (ja) 2007-12-03 2009-06-18 Panasonic Corp 半導体チップと半導体装置およびそれらの製造方法
US7871902B2 (en) 2008-02-13 2011-01-18 Infineon Technologies Ag Crack stop trenches
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
JP2009212315A (ja) * 2008-03-04 2009-09-17 Elpida Memory Inc 半導体装置及びその製造方法
EP2963675A1 (en) 2008-03-05 2016-01-06 The Board of Trustees of The University of Illinois Stretchable and foldable electronic devices
WO2009114345A1 (en) 2008-03-07 2009-09-17 3M Innovative Properties Company Dicing tape and die attach adhesive with patterned backing
US8064224B2 (en) 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
KR20090106822A (ko) 2008-04-07 2009-10-12 삼성전자주식회사 웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체
US7968373B2 (en) 2008-05-02 2011-06-28 Stats Chippac Ltd. Integrated circuit package on package system
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
US8349635B1 (en) 2008-05-20 2013-01-08 Silicon Laboratories Inc. Encapsulated MEMS device and method to form the same
US7969009B2 (en) 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
JP2010034294A (ja) * 2008-07-29 2010-02-12 Nec Electronics Corp 半導体装置およびその設計方法
US8193632B2 (en) 2008-08-06 2012-06-05 Industrial Technology Research Institute Three-dimensional conducting structure and method of fabricating the same
WO2010024678A1 (en) 2008-09-01 2010-03-04 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Chip die clamping device and transfer method
US9818680B2 (en) 2011-07-27 2017-11-14 Broadpak Corporation Scalable semiconductor interposer integration
US9893004B2 (en) 2011-07-27 2018-02-13 Broadpak Corporation Semiconductor interposer integration
JP2010073964A (ja) 2008-09-19 2010-04-02 Fujitsu Microelectronics Ltd 半導体装置の製造方法
KR20100037300A (ko) 2008-10-01 2010-04-09 삼성전자주식회사 내장형 인터포저를 갖는 반도체장치의 형성방법
US7843052B1 (en) 2008-11-13 2010-11-30 Amkor Technology, Inc. Semiconductor devices and fabrication methods thereof
WO2010059781A1 (en) 2008-11-19 2010-05-27 Semprius, Inc. Printing semiconductor elements by shear-assisted elastomeric stamp transfer
FR2938976A1 (fr) 2008-11-24 2010-05-28 St Microelectronics Grenoble Dispositif semi-conducteur a composants empiles
US7897481B2 (en) 2008-12-05 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. High throughput die-to-wafer bonding using pre-alignment
US8168458B2 (en) 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices
KR100945800B1 (ko) 2008-12-09 2010-03-05 김영혜 이종 접합 웨이퍼 제조방법
US20100164083A1 (en) 2008-12-29 2010-07-01 Numonyx B.V. Protective thin film coating in chip packaging
US7816856B2 (en) 2009-02-25 2010-10-19 Global Oled Technology Llc Flexible oled display with chiplets
US8610019B2 (en) 2009-02-27 2013-12-17 Mineral Separation Technologies Inc. Methods for sorting materials
CN105140136B (zh) 2009-03-30 2018-02-13 高通股份有限公司 使用顶部后钝化技术和底部结构技术的集成电路芯片
US8476165B2 (en) 2009-04-01 2013-07-02 Tokyo Electron Limited Method for thinning a bonding wafer
JP2010245383A (ja) 2009-04-08 2010-10-28 Elpida Memory Inc 半導体装置および半導体装置の製造方法
US20100258952A1 (en) 2009-04-08 2010-10-14 Interconnect Portfolio Llc Interconnection of IC Chips by Flex Circuit Superstructure
US8013525B2 (en) 2009-04-09 2011-09-06 Global Oled Technology Llc Flexible OLED display with chiplets
US8072056B2 (en) 2009-06-10 2011-12-06 Medtronic, Inc. Apparatus for restricting moisture ingress
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US8263434B2 (en) 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
JP5304536B2 (ja) 2009-08-24 2013-10-02 ソニー株式会社 半導体装置
US8482132B2 (en) 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
JP5697898B2 (ja) 2009-10-09 2015-04-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
JP2011128140A (ja) 2009-11-19 2011-06-30 Dainippon Printing Co Ltd センサデバイス及びその製造方法
US9202769B2 (en) 2009-11-25 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming thermal lid for balancing warpage and thermal management
EP2339614A1 (en) 2009-12-22 2011-06-29 Imec Method for stacking semiconductor chips
FR2954585B1 (fr) 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
US8138014B2 (en) 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
JP5609144B2 (ja) 2010-02-19 2014-10-22 ソニー株式会社 半導体装置および貫通電極のテスト方法
JP2011171614A (ja) 2010-02-22 2011-09-01 Casio Computer Co Ltd 半導体装置及び半導体装置の製造方法
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
JP5423874B2 (ja) 2010-03-18 2014-02-19 日本電気株式会社 半導体素子内蔵基板およびその製造方法
US8241964B2 (en) 2010-05-13 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
US8674513B2 (en) 2010-05-13 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for substrate
JP5517800B2 (ja) 2010-07-09 2014-06-11 キヤノン株式会社 固体撮像装置用の部材および固体撮像装置の製造方法
SG177816A1 (en) 2010-07-15 2012-02-28 Soitec Silicon On Insulator Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
US8481406B2 (en) 2010-07-15 2013-07-09 Soitec Methods of forming bonded semiconductor structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8415808B2 (en) 2010-07-28 2013-04-09 Sandisk Technologies Inc. Semiconductor device with die stack arrangement including staggered die and efficient wire bonding
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8288201B2 (en) 2010-08-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die
US8435835B2 (en) 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
US9224647B2 (en) 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
KR20120032254A (ko) 2010-09-28 2012-04-05 삼성전자주식회사 반도체 적층 패키지 및 이의 제조 방법
FR2966283B1 (fr) 2010-10-14 2012-11-30 Soi Tec Silicon On Insulator Tech Sa Procede pour realiser une structure de collage
US8377798B2 (en) 2010-11-10 2013-02-19 Taiwan Semiconductor Manufacturing Co., Ltd Method and structure for wafer to wafer bonding in semiconductor packaging
US9202715B2 (en) 2010-11-16 2015-12-01 Stats Chippac Ltd. Integrated circuit packaging system with connection structure and method of manufacture thereof
US8476146B2 (en) 2010-12-03 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing wafer distortion through a low CTE layer
US8987137B2 (en) 2010-12-16 2015-03-24 Lsi Corporation Method of fabrication of through-substrate vias
US8620164B2 (en) 2011-01-20 2013-12-31 Intel Corporation Hybrid III-V silicon laser formed by direct bonding
JP5682327B2 (ja) 2011-01-25 2015-03-11 ソニー株式会社 固体撮像素子、固体撮像素子の製造方法、及び電子機器
US20120194719A1 (en) 2011-02-01 2012-08-02 Scott Churchwell Image sensor units with stacked image sensors and image processors
JP5659033B2 (ja) 2011-02-04 2015-01-28 株式会社東芝 半導体装置の製造方法
US20120199960A1 (en) 2011-02-07 2012-08-09 Texas Instruments Incorporated Wire bonding for interconnection between interposer and flip chip die
US8988299B2 (en) 2011-02-17 2015-03-24 International Business Machines Corporation Integrated antenna for RFIC package applications
US8623702B2 (en) 2011-02-24 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming conductive THV and RDL on opposite sides of semiconductor die for RDL-to-RDL bonding
EP2686878B1 (en) 2011-03-16 2016-05-18 MEMC Electronic Materials, Inc. Silicon on insulator structures having high resistivity regions in the handle wafer and methods for producing such structures
US8501537B2 (en) 2011-03-31 2013-08-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods
US8716105B2 (en) 2011-03-31 2014-05-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
KR20120123919A (ko) 2011-05-02 2012-11-12 삼성전자주식회사 칩 적층 반도체 패키지 제조 방법 및 이에 의해 제조된 칩 적층 반도체 패키지
KR102378636B1 (ko) 2011-05-24 2022-03-25 소니그룹주식회사 반도체 장치
US9252172B2 (en) 2011-05-31 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region
US9029242B2 (en) 2011-06-15 2015-05-12 Applied Materials, Inc. Damage isolation by shaped beam delivery in laser scribing process
KR20130007371A (ko) 2011-07-01 2013-01-18 삼성전자주식회사 반도체 패키지
JP5982748B2 (ja) 2011-08-01 2016-08-31 ソニー株式会社 半導体装置、半導体装置の製造方法、および電子機器
US8697493B2 (en) 2011-07-18 2014-04-15 Soitec Bonding surfaces for direct bonding of semiconductor structures
US8710648B2 (en) 2011-08-09 2014-04-29 Alpha & Omega Semiconductor, Inc. Wafer level packaging structure with large contact area and preparation method thereof
US9190297B2 (en) 2011-08-11 2015-11-17 Stats Chippac, Ltd. Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures
US8441131B2 (en) 2011-09-12 2013-05-14 Globalfoundries Inc. Strain-compensating fill patterns for controlling semiconductor chip package interactions
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US20130075923A1 (en) 2011-09-23 2013-03-28 YeongIm Park Integrated circuit packaging system with encapsulation and method of manufacture thereof
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
WO2013069798A1 (ja) 2011-11-11 2013-05-16 住友ベークライト株式会社 半導体装置の製造方法
TWI467736B (zh) 2012-01-04 2015-01-01 國立交通大學 立體積體電路裝置
US8686570B2 (en) 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
US8698308B2 (en) 2012-01-31 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structural designs to minimize package defects
JP5994274B2 (ja) 2012-02-14 2016-09-21 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
TWI469312B (zh) 2012-03-09 2015-01-11 財團法人工業技術研究院 晶片堆疊結構及其製作方法
US20130265733A1 (en) 2012-04-04 2013-10-10 Texas Instruments Incorporated Interchip communication using an embedded dielectric waveguide
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
CN103377911B (zh) 2012-04-16 2016-09-21 中国科学院微电子研究所 提高化学机械平坦化工艺均匀性的方法
US20130277855A1 (en) 2012-04-24 2013-10-24 Terry (Teckgyu) Kang High density 3d package
US9142517B2 (en) 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US8809123B2 (en) 2012-06-05 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers
US8723309B2 (en) 2012-06-14 2014-05-13 Stats Chippac Ltd. Integrated circuit packaging system with through silicon via and method of manufacture thereof
KR20140006587A (ko) 2012-07-06 2014-01-16 삼성전자주식회사 반도체 패키지
US8759961B2 (en) 2012-07-16 2014-06-24 International Business Machines Corporation Underfill material dispensing for stacked semiconductor chips
US9006908B2 (en) 2012-08-01 2015-04-14 Marvell Israel (M.I.S.L) Ltd. Integrated circuit interposer and method of manufacturing the same
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US9136293B2 (en) 2012-09-07 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for sensor module
US8872349B2 (en) 2012-09-11 2014-10-28 Intel Corporation Bridge interconnect with air gap in package assembly
US9099475B2 (en) * 2012-09-12 2015-08-04 Freescale Semiconductor, Inc. Techniques for reducing inductance in through-die vias of an electronic assembly
US20140070405A1 (en) 2012-09-13 2014-03-13 Globalfoundries Inc. Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same
US8963335B2 (en) 2012-09-13 2015-02-24 Invensas Corporation Tunable composite interposer
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US9368404B2 (en) 2012-09-28 2016-06-14 Plasma-Therm Llc Method for dicing a substrate with back metal
US8912670B2 (en) 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9177884B2 (en) 2012-10-09 2015-11-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Two-sided-access extended wafer-level ball grid array (eWLB) package, assembly and method
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
KR20140058020A (ko) 2012-11-05 2014-05-14 삼성전자주식회사 발광 소자 및 그 제조 방법
US9252491B2 (en) * 2012-11-30 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Embedding low-k materials in antennas
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
DE102012224310A1 (de) 2012-12-21 2014-06-26 Tesa Se Gettermaterial enthaltendes Klebeband
US20140175655A1 (en) 2012-12-22 2014-06-26 Industrial Technology Research Institute Chip bonding structure and manufacturing method thereof
US8970023B2 (en) 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
TWI518991B (zh) 2013-02-08 2016-01-21 巽晨國際股份有限公司 Integrated antenna and integrated circuit components of the shielding module
US8946784B2 (en) 2013-02-18 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
US8901748B2 (en) 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US8802538B1 (en) 2013-03-15 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding
US9312198B2 (en) 2013-03-15 2016-04-12 Intel Deutschland Gmbh Chip package-in-package and method thereof
US10269619B2 (en) 2013-03-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
US9087765B2 (en) 2013-03-15 2015-07-21 Qualcomm Incorporated System-in-package with interposer pitch adapter
US9054063B2 (en) 2013-04-05 2015-06-09 Infineon Technologies Ag High power single-die semiconductor package
US9064937B2 (en) 2013-05-30 2015-06-23 International Business Machines Corporation Substrate bonding with diffusion barrier structures
FR3007403B1 (fr) 2013-06-20 2016-08-05 Commissariat Energie Atomique Procede de realisation d'un dispositif microelectronique mecaniquement autonome
KR102077153B1 (ko) 2013-06-21 2020-02-14 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
JP2015012244A (ja) 2013-07-01 2015-01-19 株式会社東芝 半導体発光素子
US9929050B2 (en) 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
US9324698B2 (en) 2013-08-13 2016-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip structure and method of forming same
US9633869B2 (en) 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
WO2015040798A1 (ja) 2013-09-20 2015-03-26 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
US9723716B2 (en) 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
US9093337B2 (en) * 2013-09-27 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for controlling warpage in packaging
FR3011679B1 (fr) 2013-10-03 2017-01-27 Commissariat Energie Atomique Procede ameliore d'assemblage par collage direct entre deux elements, chaque element comprenant des portions de metal et de materiaux dielectriques
KR102143518B1 (ko) 2013-10-16 2020-08-11 삼성전자 주식회사 칩 적층 반도체 패키지 및 그 제조 방법
US9257399B2 (en) 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
KR102149150B1 (ko) * 2013-10-21 2020-08-28 삼성전자주식회사 전자 장치
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9530730B2 (en) 2013-11-08 2016-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Configurable routing for packaging applications
JP6441025B2 (ja) 2013-11-13 2018-12-19 株式会社東芝 半導体チップの製造方法
US9570421B2 (en) 2013-11-14 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
KR102147354B1 (ko) 2013-11-14 2020-08-24 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
US9330954B2 (en) 2013-11-22 2016-05-03 Invensas Corporation Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9224697B1 (en) 2013-12-09 2015-12-29 Xilinx, Inc. Multi-die integrated circuits implemented using spacer dies
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
US9318474B2 (en) 2013-12-16 2016-04-19 Apple Inc. Thermally enhanced wafer level fan-out POP package
US9437572B2 (en) 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US10170409B2 (en) 2013-12-23 2019-01-01 Intel Corporation Package on package architecture and method for making
US9768038B2 (en) 2013-12-23 2017-09-19 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of making embedded wafer level chip scale packages
CN103730379A (zh) 2014-01-16 2014-04-16 苏州晶方半导体科技股份有限公司 芯片封装方法及结构
US9396300B2 (en) 2014-01-16 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof
US9653442B2 (en) 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9343433B2 (en) 2014-01-28 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with stacked dies and methods of forming the same
US20150287697A1 (en) 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US10971476B2 (en) 2014-02-18 2021-04-06 Qualcomm Incorporated Bottom package with metal post interconnections
US9293437B2 (en) 2014-02-20 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Functional block stacked 3DIC and method of making same
US20150255349A1 (en) 2014-03-07 2015-09-10 JAMES Matthew HOLDEN Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9418924B2 (en) 2014-03-20 2016-08-16 Invensas Corporation Stacked die integrated circuit
US9230941B2 (en) 2014-03-28 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure for stacked semiconductor devices
US9299736B2 (en) 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
US9076860B1 (en) 2014-04-04 2015-07-07 Applied Materials, Inc. Residue removal from singulated die sidewall
US8975163B1 (en) 2014-04-10 2015-03-10 Applied Materials, Inc. Laser-dominated laser scribing and plasma etch hybrid wafer dicing
US9601463B2 (en) 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
US9385110B2 (en) 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR102275705B1 (ko) 2014-07-11 2021-07-09 삼성전자주식회사 웨이퍼 대 웨이퍼 접합 구조
US9601353B2 (en) 2014-07-30 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with molding structures and methods of forming the same
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US9601437B2 (en) 2014-09-09 2017-03-21 Nxp B.V. Plasma etching and stealth dicing laser process
US10468381B2 (en) 2014-09-29 2019-11-05 Apple Inc. Wafer level integration of passive devices
US9536848B2 (en) 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
US9394161B2 (en) 2014-11-14 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. MEMS and CMOS integration with low-temperature bonding
US9673096B2 (en) 2014-11-14 2017-06-06 Infineon Technologies Ag Method for processing a semiconductor substrate and a method for processing a semiconductor wafer
KR102360381B1 (ko) 2014-12-01 2022-02-11 삼성전자주식회사 적층 구조를 갖는 반도체 소자 및 그 제조방법
US9548273B2 (en) 2014-12-04 2017-01-17 Invensas Corporation Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9899442B2 (en) 2014-12-11 2018-02-20 Invensas Corporation Image sensor device
JP2017503360A (ja) 2014-12-15 2017-01-26 インテル コーポレイション オポッサム・ダイ型パッケージ・オン・パッケージ装置
US9583462B2 (en) 2015-01-22 2017-02-28 Qualcomm Incorporated Damascene re-distribution layer (RDL) in fan out split die application
KR101672622B1 (ko) 2015-02-09 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9508660B2 (en) 2015-02-10 2016-11-29 Intel Corporation Microelectronic die having chamfered corners
US9633974B2 (en) 2015-03-04 2017-04-25 Apple Inc. System in package fan out stacking architecture and process flow
DE102015103274A1 (de) 2015-03-06 2016-09-08 HARTING Electronics GmbH Kabelabdichtung
JP6738591B2 (ja) 2015-03-13 2020-08-12 古河電気工業株式会社 半導体ウェハの処理方法、半導体チップおよび表面保護テープ
US9443824B1 (en) 2015-03-30 2016-09-13 Qualcomm Incorporated Cavity bridge connection for die split architecture
US9659907B2 (en) 2015-04-07 2017-05-23 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
US10068862B2 (en) 2015-04-09 2018-09-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a package in-fan out package
US10074630B2 (en) 2015-04-14 2018-09-11 Amkor Technology, Inc. Semiconductor package with high routing density patch
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9601471B2 (en) 2015-04-23 2017-03-21 Apple Inc. Three layer stack structure
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US9595494B2 (en) 2015-05-04 2017-03-14 Qualcomm Incorporated Semiconductor package with high density die to die connection and method of making the same
US20160343685A1 (en) 2015-05-21 2016-11-24 Mediatek Inc. Semiconductor package assembly and method for forming the same
US10032756B2 (en) 2015-05-21 2018-07-24 Mediatek Inc. Semiconductor package assembly with facing active surfaces of first and second semiconductor die and method for forming the same
JP6468071B2 (ja) 2015-05-25 2019-02-13 富士通株式会社 半導体装置及び電子装置並びに半導体装置の製造方法
US10043769B2 (en) * 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
KR101664411B1 (ko) 2015-06-04 2016-10-14 주식회사 에스에프에이반도체 웨이퍼 레벨의 팬 아웃 패키지 제조방법
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9704827B2 (en) 2015-06-25 2017-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond pad structure
US9656852B2 (en) 2015-07-06 2017-05-23 Taiwan Semiconductor Manufacturing Company Ltd. CMOS-MEMS device structure, bonding mesa structure and associated method
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10352991B2 (en) 2015-07-21 2019-07-16 Fermi Research Alliance, Llc Edgeless large area ASIC
US10075657B2 (en) 2015-07-21 2018-09-11 Fermi Research Alliance, Llc Edgeless large area camera system
US9728521B2 (en) 2015-07-23 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond using a copper alloy for yield improvement
US9559081B1 (en) 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9768145B2 (en) 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US10049953B2 (en) 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US9917072B2 (en) 2015-09-21 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process
US9754891B2 (en) 2015-09-23 2017-09-05 International Business Machines Corporation Low-temperature diffusion doping of copper interconnects independent of seed layer composition
WO2017052652A1 (en) 2015-09-25 2017-03-30 Intel Corporation Combination of semiconductor die with another die by hybrid bonding
US10032751B2 (en) 2015-09-28 2018-07-24 Invensas Corporation Ultrathin layer for forming a capacitive interface between joined integrated circuit components
KR101787832B1 (ko) 2015-10-22 2017-10-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
US10163856B2 (en) 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
US9524959B1 (en) * 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
US9711458B2 (en) 2015-11-13 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method for chip package
FR3044167B1 (fr) 2015-11-20 2018-01-05 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif optoelectronique a diodes electroluminescentes comportant au moins une diode zener
US9666560B1 (en) 2015-11-25 2017-05-30 Invensas Corporation Multi-chip microelectronic assembly with built-up fine-patterned circuit structure
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
KR20170075125A (ko) 2015-12-22 2017-07-03 에스케이하이닉스 주식회사 반도체 패키지 및 제조 방법
US9881882B2 (en) 2016-01-06 2018-01-30 Mediatek Inc. Semiconductor package with three-dimensional antenna
US20170200659A1 (en) 2016-01-08 2017-07-13 International Business Machines Corporation Porous underfill enabling rework
US9923011B2 (en) 2016-01-12 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with stacked semiconductor dies
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
JP2017130610A (ja) 2016-01-22 2017-07-27 ソニー株式会社 イメージセンサ、製造方法、及び、電子機器
US20170243845A1 (en) 2016-02-19 2017-08-24 Qualcomm Incorporated Fan-out wafer-level packages with improved topology
US10050018B2 (en) 2016-02-26 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure and methods of forming
US10636767B2 (en) 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
JP6453796B2 (ja) 2016-03-14 2019-01-16 株式会社東芝 半導体装置およびその製造方法
SG10201913140RA (en) 2016-03-21 2020-03-30 Agency Science Tech & Res Semiconductor package and method of forming the same
US10186468B2 (en) 2016-03-31 2019-01-22 Infineon Technologies Ag System and method for a transducer in an eWLB package
CN108701690B (zh) 2016-04-01 2023-10-27 英特尔公司 用于管芯堆叠的技术和关联配置
TWI606563B (zh) 2016-04-01 2017-11-21 力成科技股份有限公司 薄型晶片堆疊封裝構造及其製造方法
US10002857B2 (en) 2016-04-12 2018-06-19 Qualcomm Incorporated Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US9761559B1 (en) 2016-04-21 2017-09-12 Micron Technology, Inc. Semiconductor package and fabrication method thereof
US20170330855A1 (en) 2016-05-13 2017-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Immersion Bonding
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10032722B2 (en) 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof
US9972565B1 (en) 2016-06-07 2018-05-15 National Technology & Engineering Solutions Of Sandia, Llc Lateral vias for connections to buried microconductors
KR102505856B1 (ko) 2016-06-09 2023-03-03 삼성전자 주식회사 웨이퍼 대 웨이퍼 접합 구조체
KR102521881B1 (ko) 2016-06-15 2023-04-18 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9865566B1 (en) * 2016-06-15 2018-01-09 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9818729B1 (en) 2016-06-16 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and method
KR102538175B1 (ko) 2016-06-20 2023-06-01 삼성전자주식회사 반도체 패키지
US10431738B2 (en) 2016-06-24 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
KR102570582B1 (ko) 2016-06-30 2023-08-24 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US9941241B2 (en) 2016-06-30 2018-04-10 International Business Machines Corporation Method for wafer-wafer bonding
US11355427B2 (en) 2016-07-01 2022-06-07 Intel Corporation Device, method and system for providing recessed interconnect structures of a substrate
US10892219B2 (en) 2016-07-01 2021-01-12 Intel Corporation Molded embedded bridge for enhanced EMIB applications
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9892961B1 (en) 2016-08-09 2018-02-13 International Business Machines Corporation Air gap spacer formation for nano-scale semiconductor devices
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
EP3288076B1 (en) 2016-08-25 2021-06-23 IMEC vzw A semiconductor die package and method of producing the package
BR112019001313A2 (pt) 2016-08-26 2019-04-30 Intel Corporation estruturas de dispositivo de circuito integrado e técnicas de fabricação de frente e verso
US10535632B2 (en) 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
KR102649471B1 (ko) 2016-09-05 2024-03-21 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US9768133B1 (en) 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US11508662B2 (en) 2016-09-30 2022-11-22 Intel Corporation Device and method of very high density routing used with embedded multi-die interconnect bridge
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10748864B2 (en) 2016-10-05 2020-08-18 Semiconductor Components Industries, Llc Bonded semiconductor package and related methods
US10719762B2 (en) 2017-08-03 2020-07-21 Xcelsis Corporation Three dimensional chip structure implementing machine trained network
US10672663B2 (en) 2016-10-07 2020-06-02 Xcelsis Corporation 3D chip sharing power circuit
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US10872852B2 (en) 2016-10-12 2020-12-22 Micron Technology, Inc. Wafer level package utilizing molded interposer
US9722098B1 (en) 2016-10-18 2017-08-01 Ase Electronics (M) Sdn Bhd Semiconductor device package and method of manufacturing the same
US10304801B2 (en) 2016-10-31 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US20180130768A1 (en) 2016-11-09 2018-05-10 Unisem (M) Berhad Substrate Based Fan-Out Wafer Level Packaging
US10529690B2 (en) * 2016-11-14 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10153222B2 (en) * 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10177078B2 (en) 2016-11-28 2019-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package structure
US10163750B2 (en) 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
US10453832B2 (en) 2016-12-15 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structures and methods of forming same
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
KR102320673B1 (ko) 2016-12-28 2021-11-01 인벤사스 본딩 테크놀로지스 인코포레이티드 적층된 기판의 처리
KR20230156179A (ko) 2016-12-29 2023-11-13 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US20180190583A1 (en) 2016-12-29 2018-07-05 Invensas Bonding Technologies, Inc. Bonded structures with integrated passive component
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10431614B2 (en) 2017-02-01 2019-10-01 Semiconductor Components Industries, Llc Edge seals for semiconductor packages
US9865567B1 (en) 2017-02-02 2018-01-09 Xilinx, Inc. Heterogeneous integration of integrated circuit device and companion device
WO2018147940A1 (en) 2017-02-09 2018-08-16 Invensas Bonding Technologies, Inc. Bonded structures
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
JP6640780B2 (ja) 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10580823B2 (en) 2017-05-03 2020-03-03 United Microelectronics Corp. Wafer level packaging method
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10541228B2 (en) 2017-06-15 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages formed using RDL-last process
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10658335B2 (en) 2017-06-16 2020-05-19 Futurewei Technologies, Inc. Heterogenous 3D chip stack for a mobile processor
US10483187B2 (en) * 2017-06-30 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreading device and method
US10304805B2 (en) 2017-08-24 2019-05-28 Micron Technology, Inc. Dual sided fan-out package having low warpage across all temperatures
US10707145B2 (en) 2017-09-08 2020-07-07 Kemet Electronics Corporation High density multi-component packages
US11558029B2 (en) 2017-09-14 2023-01-17 Kyocera Corporation Acoustic wave device and communication apparatus
US10468384B2 (en) 2017-09-15 2019-11-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US10332899B2 (en) 2017-09-29 2019-06-25 Intel Corporation 3D package having edge-aligned die stack with direct inter-die wire connections
CN111052364B (zh) 2017-09-29 2025-08-19 英特尔公司 具有嵌入式互连的半导体封装
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10818624B2 (en) 2017-10-24 2020-10-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for manufacturing the same
US11251157B2 (en) 2017-11-01 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure with hybrid bonding structure and method of fabricating the same and package
US10672820B2 (en) 2017-11-23 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonded structure
US10483156B2 (en) 2017-11-29 2019-11-19 International Business Machines Corporation Non-embedded silicon bridge chip for multi-chip module
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US10312221B1 (en) * 2017-12-17 2019-06-04 Advanced Micro Devices, Inc. Stacked dies and dummy components for improved thermal performance
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
TWI643307B (zh) 2018-01-30 2018-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10559507B1 (en) 2018-02-06 2020-02-11 Facebook Technologies, Llc Direct wafer mapping and selective elastomer deposition
US11127738B2 (en) 2018-02-09 2021-09-21 Xcelsis Corporation Back biasing of FD-SOI circuit blocks
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US10847478B2 (en) 2018-02-27 2020-11-24 Amkor Technology Singapore Holding Pte. Ltd. Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US10991804B2 (en) 2018-03-29 2021-04-27 Xcelsis Corporation Transistor level interconnection methodologies utilizing 3D interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US10825772B2 (en) 2018-04-30 2020-11-03 Xilinx, Inc. Redundancy scheme for multi-chip stacked devices
US10937743B2 (en) 2018-04-30 2021-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Mixing organic materials into hybrid packages
US11398258B2 (en) 2018-04-30 2022-07-26 Invensas Llc Multi-die module with low power operation
US10403577B1 (en) 2018-05-03 2019-09-03 Invensas Corporation Dielets on flexible and stretchable packaging for microelectronics
US11469138B2 (en) 2018-05-04 2022-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via for coupling attached component upper electrode to substrate
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10510629B2 (en) 2018-05-18 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
US10923413B2 (en) 2018-05-30 2021-02-16 Xcelsis Corporation Hard IP blocks with physically bidirectional passageways
CN112514059B (zh) 2018-06-12 2024-05-24 隔热半导体粘合技术公司 堆叠微电子部件的层间连接
KR102878117B1 (ko) 2018-06-13 2025-10-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 패드로서의 ｔｓｖ
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US10685937B2 (en) 2018-06-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package having dummy structures and method of forming same
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US10333623B1 (en) 2018-06-25 2019-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Optical transceiver
US10930633B2 (en) 2018-06-29 2021-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer design for package integration
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US12406959B2 (en) 2018-07-26 2025-09-02 Adeia Semiconductor Bonding Technologies Inc. Post CMP processing for hybrid bonding
KR102560697B1 (ko) 2018-07-31 2023-07-27 삼성전자주식회사 인터포저를 가지는 반도체 패키지
US10700094B2 (en) 2018-08-08 2020-06-30 Xcelsis Corporation Device disaggregation for improved performance
US10727205B2 (en) 2018-08-15 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding technology for stacking integrated circuits
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11296044B2 (en) 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US10797031B2 (en) 2018-09-20 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
US10504824B1 (en) 2018-09-21 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US10868353B2 (en) 2018-09-27 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Electronic device and manufacturing method thereof
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
KR20200047845A (ko) 2018-10-24 2020-05-08 삼성전자주식회사 반도체 패키지
KR102596758B1 (ko) 2018-10-24 2023-11-03 삼성전자주식회사 반도체 패키지
US10861808B2 (en) * 2018-11-21 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure of dies with dangling bonds
US11158607B2 (en) 2018-11-29 2021-10-26 Apple Inc. Wafer reconstitution and die-stitching
US10867978B2 (en) 2018-12-11 2020-12-15 Advanced Micro Devices, Inc. Integrated circuit module with integrated discrete devices
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
US11476213B2 (en) 2019-01-14 2022-10-18 Invensas Bonding Technologies, Inc. Bonded structures without intervening adhesive
KR102803426B1 (ko) 2019-01-24 2025-05-07 삼성전기주식회사 브리지 내장 인터포저, 및 이를 포함하는 패키지 기판 및 반도체 패키지
US11387202B2 (en) 2019-03-01 2022-07-12 Invensas Llc Nanowire bonding interconnect for fine-pitch microelectronics
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US11552019B2 (en) 2019-03-12 2023-01-10 Intel Corporation Substrate patch reconstitution options
US10770430B1 (en) 2019-03-22 2020-09-08 Xilinx, Inc. Package integration for memory devices
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US12374641B2 (en) 2019-06-12 2025-07-29 Adeia Semiconductor Bonding Technologies Inc. Sealed bonded structures and methods for forming the same
US12341129B2 (en) 2019-06-13 2025-06-24 Intel Corporation Substrateless double-sided embedded multi-die interconnect bridge
US11145623B2 (en) 2019-06-14 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US20210020577A1 (en) 2019-07-16 2021-01-21 Dyi-chung Hu Semiconductor package and manufacturing method thereof
US11978685B2 (en) 2019-07-25 2024-05-07 Intel Corporation Glass core patch with in situ fabricated fan-out layer to enable die tiling applications
US11742301B2 (en) 2019-08-19 2023-08-29 Advanced Micro Devices, Inc. Fan-out package with reinforcing rivets
US11094613B2 (en) 2019-08-22 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US11094635B2 (en) 2019-08-22 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US11508677B2 (en) 2019-08-29 2022-11-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package for high-speed data transmission and manufacturing method thereof
US11133263B2 (en) 2019-09-17 2021-09-28 Intel Corporation High-density interconnects for integrated circuit packages
US10998272B2 (en) 2019-09-17 2021-05-04 Intel Corporation Organic interposers for integrated circuit packages
WO2021061246A1 (en) 2019-09-25 2021-04-01 Intel Corporation Molded interconnects in bridges for integrated-circuit packages
US11183477B2 (en) 2019-09-26 2021-11-23 Intel Corporation Mixed hybrid bonding structures and methods of forming the same
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US11824040B2 (en) 2019-09-27 2023-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package component, electronic device and manufacturing method thereof
TWI734455B (zh) 2019-10-09 2021-07-21 財團法人工業技術研究院 多晶片封裝件及其製造方法
US12113054B2 (en) 2019-10-21 2024-10-08 Adeia Semiconductor Technologies Llc Non-volatile dynamic random access memory
US20210125965A1 (en) 2019-10-24 2021-04-29 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11688693B2 (en) 2019-10-29 2023-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and method of manufacture
US11164817B2 (en) 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
KR20220120631A (ko) 2019-12-23 2022-08-30 인벤사스 본딩 테크놀로지스 인코포레이티드 결합형 구조체를 위한 전기적 리던던시
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US11791275B2 (en) 2019-12-27 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing
US11616026B2 (en) 2020-01-17 2023-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US20210242152A1 (en) 2020-02-05 2021-08-05 Invensas Bonding Technologies, Inc. Selective alteration of interconnect pads for direct bonding
TW202135243A (zh) 2020-03-04 2021-09-16 力成科技股份有限公司 扇出型堆疊式半導體封裝結構之多層模封方法
US20210280507A1 (en) 2020-03-05 2021-09-09 Qualcomm Incorporated Package comprising dummy interconnects
CN115943489A (zh) 2020-03-19 2023-04-07 隔热半导体粘合技术公司 用于直接键合结构的尺寸补偿控制
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11515229B2 (en) 2020-03-31 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11594498B2 (en) 2020-04-27 2023-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11508633B2 (en) 2020-05-28 2022-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having taper-shaped conductive pillar and method of forming thereof
TWI732568B (zh) 2020-05-28 2021-07-01 欣興電子股份有限公司 內埋元件的基板結構及其製造方法
US11562963B2 (en) 2020-06-05 2023-01-24 Intel Corporation Stacked semiconductor package and method of forming the same
US11955431B2 (en) 2020-06-05 2024-04-09 Intel Corporation Interposer structures and methods for 2.5D and 3D packaging
US11239184B2 (en) 2020-06-11 2022-02-01 Advanced Semicondutor Engineering, Inc. Package substrate, electronic device package and method for manufacturing the same
US11335650B2 (en) 2020-06-11 2022-05-17 Advanced Semiconductor Engineering, Inc. Package substrate, electronic device package and method for manufacturing the same
US11342272B2 (en) 2020-06-11 2022-05-24 Advanced Semiconductor Engineering, Inc. Substrate structures, and methods for forming the same and semiconductor package structures
US11450615B2 (en) 2020-06-12 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11574890B2 (en) 2020-07-01 2023-02-07 Amkor Technology Singapore Holding Pte. Lte. Semiconductor devices and methods of manufacturing semiconductor devices
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
WO2022094587A1 (en) 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
CN116635998A (zh) 2020-10-29 2023-08-22 美商艾德亚半导体接合科技有限公司 直接键合方法和结构
WO2022147430A1 (en) 2020-12-28 2022-07-07 Invensas Bonding Technologies, Inc. Structures with through-substrate vias and methods for forming the same
KR20230125309A (ko) 2020-12-28 2023-08-29 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 기판-관통 비아를 가지는 구조체 및 이를 형성하기위한 방법
JP7783896B2 (ja) 2020-12-30 2025-12-10 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 導電特徴部を備えた構造体及びその形成方法
KR20230128062A (ko) 2020-12-30 2023-09-01 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 접합 구조
CN117256047A (zh) 2021-03-03 2023-12-19 美商艾德亚半导体接合科技有限公司 用于直接接合的接触结构
EP4315398A4 (en) 2021-03-31 2025-03-05 Adeia Semiconductor Bonding Technologies Inc. DIRECT ADHESION AND REMOVING A CARRIER
US20220320035A1 (en) 2021-03-31 2022-10-06 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
WO2022212595A1 (en) 2021-03-31 2022-10-06 Invensas Bonding Technologies, Inc. Direct bonding and debonding of carrier
WO2023278605A1 (en) 2021-06-30 2023-01-05 Invensas Bonding Technologies, Inc. Element with routing structure in bonding layer
WO2023288021A1 (en) 2021-07-16 2023-01-19 Invensas Bonding Technologies, Inc. Optically obstructive protective element for bonded structures
WO2023014616A1 (en) 2021-08-02 2023-02-09 Invensas Bonding Technologies, Inc. Protective semiconductor elements for bonded structures
EP4396872A4 (en) 2021-09-01 2025-05-21 Adeia Semiconductor Technologies LLC STACKED STRUCTURE WITH INTERPOSER
US20230067677A1 (en) 2021-09-01 2023-03-02 Invensas Bonding Technologies, Inc. Sequences and equipment for direct bonding
EP4402717A4 (en) 2021-09-14 2025-10-22 Adeia Semiconductor Bonding Technologies Inc METHOD FOR BONDING THIN SUBSTRATES
JP2024535904A (ja) 2021-09-24 2024-10-02 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 能動インターポーザ付きのボンデッド構造体
KR20240093687A (ko) 2021-10-18 2024-06-24 아데이아 세미컨덕터 테크놀로지스 엘엘씨 결합 구조체 내의 감소된 기생 커패시턴스
KR20240090512A (ko) 2021-10-19 2024-06-21 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 멀티-다이 스태킹에서의 적층된 인덕터
JP2024538873A (ja) 2021-10-22 2024-10-24 アデイア セミコンダクター テクノロジーズ リミテッド ライアビリティ カンパニー 高周波デバイスパッケージ
WO2023076842A1 (en) 2021-10-25 2023-05-04 Adeia Semiconductor Bonding Technologies Inc. Power distribution for stacked electronic devices
US20230125395A1 (en) 2021-10-27 2023-04-27 Adeia Semiconductor Bonding Technologies Inc. Stacked structures with capacitive coupling connections
US20230140107A1 (en) 2021-10-28 2023-05-04 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures
CN118435345A (zh) 2021-10-28 2024-08-02 美商艾德亚半导体接合科技有限公司 扩散势垒及其形成方法
US20230142680A1 (en) 2021-10-28 2023-05-11 Adeia Semiconductor Bonding Technologies Inc. Stacked electronic devices
WO2023081273A1 (en) 2021-11-05 2023-05-11 Adeia Semiconductor Bonding Technologies Inc. Multi-channel device stacking
EP4434089A4 (en) 2021-11-17 2025-11-19 Adeia Semiconductor Bonding Technologies Inc THERMAL DETACHMENT FOR STACKED MATRICES
KR20240101651A (ko) 2021-11-18 2024-07-02 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 다이 적층체를 위한 유체 냉각
US20230187264A1 (en) 2021-12-13 2023-06-15 Adeia Semiconductor Technologies Llc Methods for bonding semiconductor elements
US20230187317A1 (en) 2021-12-13 2023-06-15 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures
KR20240118874A (ko) 2021-12-17 2024-08-05 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 접합을 위한 전도성 특징부를 갖는 구조체 및 그 형성 방법
EP4454440A4 (en) 2021-12-20 2025-11-26 Adeia Semiconductor Bonding Technologies Inc THERMOELECTRIC COOLING IN MICROELECTRONICS
CN118661254A (zh) 2021-12-20 2024-09-17 美商艾德亚半导体接合科技有限公司 用于管芯封装的热电冷却
JP2024547065A (ja) 2021-12-20 2024-12-26 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 素子の直接接合及び剥離
WO2023122559A1 (en) 2021-12-22 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Low stress direct hybrid bonding
WO2023122687A1 (en) 2021-12-23 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Apparatuses and methods for die bond control
EP4454013A4 (en) 2021-12-23 2025-07-30 Adeia Semiconductor Bonding Technologies Inc LINKED STRUCTURES COMPRISING INTERCONNECTING ASSEMBLIES
EP4454008A4 (en) 2021-12-23 2025-11-05 Adeia Semiconductor Bonding Technologies Inc DIRECT CONNECTION TO ENCLOSURE SUBSTRATES
JP2024545355A (ja) 2021-12-27 2024-12-05 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 直接結合されたフレームウェハ
KR20240144961A (ko) 2022-01-31 2024-10-04 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 전자 디바이스용 열소산 시스템
EP4483406A1 (en) 2022-02-24 2025-01-01 Adeia Semiconductor Bonding Technologies Inc. Bonded structures
EP4494184A1 (en) 2022-03-16 2025-01-22 Adeia Semiconductor Bonding Technologies Inc. Expansion control for bonding
CN119096348A (zh) 2022-04-25 2024-12-06 美商艾德亚半导体接合科技有限公司 用于直接结合的膨胀控制结构及其形成方法
US20230360950A1 (en) 2022-05-05 2023-11-09 Adeia Semiconductor Bonding Technologies Inc. Gang-flipping of dies prior to bonding
CN119110988A (zh) 2022-05-05 2024-12-10 美商艾德亚半导体接合科技有限公司 低温直接键合
US20230369136A1 (en) 2022-05-13 2023-11-16 Adeia Semiconductor Bonding Technologies Inc. Bonding surface validation on dicing tape
JP2025517291A (ja) 2022-05-23 2025-06-05 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド ボンデッド構造体のための試験用素子
US20240038702A1 (en) 2022-07-27 2024-02-01 Adeia Semiconductor Bonding Technologies Inc. High-performance hybrid bonded interconnect systems

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101901711B1 (ko) 2017-09-27 2018-09-27 삼성전기 주식회사 팬-아웃 반도체 패키지

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