KR101260632B1 - 출력 제어 메모리 - Google Patents

출력 제어 메모리 Download PDF

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Publication number
KR101260632B1
KR101260632B1 KR1020127027496A KR20127027496A KR101260632B1 KR 101260632 B1 KR101260632 B1 KR 101260632B1 KR 1020127027496 A KR1020127027496 A KR 1020127027496A KR 20127027496 A KR20127027496 A KR 20127027496A KR 101260632 B1 KR101260632 B1 KR 101260632B1
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KR
South Korea
Prior art keywords
data
memory
serial
bank
flash memory
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Application number
KR1020127027496A
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English (en)
Korean (ko)
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KR20120135327A (ko
Inventor
학준 오
홍 범 편
진기 김
Original Assignee
모사이드 테크놀로지스 인코퍼레이티드
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Priority claimed from US11/324,023 external-priority patent/US7652922B2/en
Application filed by 모사이드 테크놀로지스 인코퍼레이티드 filed Critical 모사이드 테크놀로지스 인코퍼레이티드
Publication of KR20120135327A publication Critical patent/KR20120135327A/ko
Application granted granted Critical
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
KR1020127027496A 2005-09-30 2006-09-29 출력 제어 메모리 KR101260632B1 (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US72236805P 2005-09-30 2005-09-30
US60/722,368 2005-09-30
US11/324,023 US7652922B2 (en) 2005-09-30 2005-12-30 Multiple independent serial link memory
US11/324,023 2005-12-30
US84779006P 2006-09-27 2006-09-27
US60/847,790 2006-09-27
PCT/CA2006/001609 WO2007036050A1 (en) 2005-09-30 2006-09-29 Memory with output control

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020087010560A Division KR101293365B1 (ko) 2005-09-30 2006-09-29 출력 제어 메모리

Publications (2)

Publication Number Publication Date
KR20120135327A KR20120135327A (ko) 2012-12-12
KR101260632B1 true KR101260632B1 (ko) 2013-05-03

Family

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Family Applications (2)

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KR1020087010560A KR101293365B1 (ko) 2005-09-30 2006-09-29 출력 제어 메모리
KR1020127027496A KR101260632B1 (ko) 2005-09-30 2006-09-29 출력 제어 메모리

Family Applications Before (1)

Application Number Title Priority Date Filing Date
KR1020087010560A KR101293365B1 (ko) 2005-09-30 2006-09-29 출력 제어 메모리

Country Status (6)

Country Link
US (14) US7515471B2 (zh)
EP (1) EP1932158A4 (zh)
JP (1) JP5193045B2 (zh)
KR (2) KR101293365B1 (zh)
TW (2) TWI543185B (zh)
WO (1) WO2007036050A1 (zh)

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