CN103460372B - 具有改进的沟道堆栈的半导体结构及其制备方法 - Google Patents

具有改进的沟道堆栈的半导体结构及其制备方法 Download PDF

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CN103460372B
CN103460372B CN201280017397.4A CN201280017397A CN103460372B CN 103460372 B CN103460372 B CN 103460372B CN 201280017397 A CN201280017397 A CN 201280017397A CN 103460372 B CN103460372 B CN 103460372B
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CN103460372A (zh
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P·E·格雷戈里
L·希弗伦
P·拉纳德
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Triple Fujitsu Semiconductor Co., Ltd.
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Abstract

一种用于制造具有沟道堆栈的半导体结构的方法，包括在PMOS晶体管元件（116）和NMOS晶体管元件（106）的栅极下方形成屏蔽层（120、110）；在屏蔽层上形成阈值电压控制层（122、112）；并且在阈值控制层上形成外延沟道层（124）。PMOS晶体管元件和NMOS晶体管元件的外延沟道层的至少一部分被形成为公共的均厚层。PMOS晶体管元件（116）的屏蔽层（120）可包括锑作为掺杂材料，该掺杂材料可在形成外延沟道层之前或之后被插入到该结构中。

Description

具有改进的沟道堆栈的半导体结构及其制备方法
技术领域
本公开大致涉及半导体器件及制造工艺，并且更具体地涉及一种具有改进的沟道堆栈（channel stack）的半导体结构及其制造方法。
背景技术
通常在被掺杂以包含迁移电荷载体的半导体衬底上制造场效应晶体管。当作为活化过程的结果而被合并入半导体衬底晶格时，掺杂剂原子可以是电子供体或电子受体。一种活化的供体原子向材料转移弱结合的价电子，从而产生过量的负电荷载体。这些弱结合的电子可相对自由地在半导体衬底晶格中移动，便于在存在由栅极端子施加的电场的情况下传导。类似地，活化的受体产生被称为空穴的迁移正电荷载体。掺杂有供体杂质的半导体被称为n型，而那些掺杂有受体杂质的半导体被称为p型。与硅半导体衬底结合使用的常见n型供体原子包括砷、磷和锑。
相对于重要参数（例如阈值电压或沟道迁移率），用于栅极下方掺杂层的半导体衬底掺杂的掺杂注入或原位掺杂生长参数对于FET器件的最优性能来说是关键的。然而，注入工具的限制、所要求的热处理条件和材料或工艺上的变化能够容易导致掺杂材料从初始注入位置的不期望的扩散，降低了性能或甚至妨碍可靠的晶体管操作。使用共掺杂注入工艺时尤其如此，因为不同的掺杂剂类型具有不同的固态扩散常数和对工艺条件的不同响应。
成本经济的电子制造需要在纳米尺度是可靠的晶体管结构和制造工艺，并且不需要昂贵的或不可获得的工具或工艺控制条件。尽管难以平衡控制晶体管电气性能的各种可变因素，找到产生可接受的电气特性（如电荷载体迁移率和阈电压电平）的合适的晶体管掺杂结构和制造技术是这样的商业上有用的晶体管的关键方面。
发明内容
根据前面所述，本领域技术人员可以理解，需要一种技术来制造改进的晶体管器件，该器件通过在无掺杂的（本征）沟道层下方产生若干个精确掺杂层来提供阈值电压控制和改进的操作性能，无掺杂的沟道层可以外延生长在掺杂层上。这些掺杂层和/或本征沟道层可以被形成为延伸跨过多个晶体管的均厚层（blanket layer），并且可以随后通过浅沟槽隔离等来改变该均厚层，以将晶体管分离成块或单独元件。根据以下公开，提供了一种具有改进的沟道堆栈的掺杂半导体结构及其制造方法，该掺杂半导体结构基本上消除了或大大减少了与传统晶体管器件设计相关的缺点和问题。
根据本发明的一实施例，提供了一种用于制造具有沟道堆栈的半导体结构的方法，该方法包括在晶体管元件的栅极下方形成屏蔽层（screening layer），在晶体管元件的屏蔽层上方形成阈值电压控制层，并在晶体管元件的阈值控制层上形成外延沟道层。用于PMOS晶体管元件的屏蔽层包括锑作为掺杂材料，该掺杂材料可以在形成外延沟道层之前或之后被插入到所述结构中。如在说明书中更详细地公开地那样，所选择的单掺杂或共掺杂原子的浓度和类型、掺杂注入或原位生长条件，以及特定掺杂分布、退火曲线和晶体管结构都是被选择以维持比传统晶体管更可靠的器件。
本公开的实施例可以具有这些优点中的某些或全部，或者不包括这些优点。根据下方的附图、说明书和权利要求，对本领域技术人员来说，其他技术优点可以是显而易见的。
附图说明
为了更完整地理解本发明，参照结合附图做出的以下描述，其中相同的附图标记表示相同的部件，其中：
图1A到图1K示出了具有沟道堆栈的半导体结构的制造工艺，其使用均厚沟道和浅沟槽隔离的最后方法（last approach）；
图2A至图2I示出了具有沟道堆栈的半导体结构的制造工艺，其使用均厚沟道和浅沟槽隔离的第一方法（first approach）；
图3A至3I示出了具有沟道堆栈的半导体结构的制造工艺，其使用多个均厚外延层和浅沟槽隔离的最后方法；
图4示出了用于晶体管元件的屏蔽层中的砷和锑的垂直掺杂分布；
图5示出了砷和锑的Id-off和Id-on的比较图；
图6示出了在外延沟道层的不同掺杂浓度和各种厚度下的晶体管元件屏蔽层中锑的Id-off和Id-on的比较图；
图7示出了在沟道层外延生长之后注入的不同掺杂剂浓度下的晶体管元件屏蔽层中使用的锑的Id-off和Id-on的比较图；
图8示出了模拟的掺杂分布，其中锑和砷被注入以建立屏蔽层和阈值电压控制层；
图9示出了模拟的掺杂分布，其中锑和砷在各种退火温度下在外延沟道层形成之前被注入；
图10示出了类似图9的掺杂分布，其中退火温度是恒定900℃，但采用不同的退火时间；
图11示出了具有与图9相同的条件的模拟掺杂分布，但具有在800℃的退火温度下10keV的更高能量砷注入；
图12是类似图11的掺杂分布，但具有比锑注入能量更高的砷注入能量；
图13示出了模拟的掺杂分布，其中锑在沉积外延沟道层之前被注入，接着是在沉积外延沟道层之后进行第二次锑注入；
图14示出类似图13的掺杂分布，但第二次锑注入是在较低的能量下进行。
具体实施方式
多种方法可以用来构建具有沟道堆栈的晶体管元件，该沟道堆栈具有用于屏蔽栅极上的电荷的屏蔽层、用于调节晶体管元件的阈值电压的阈值电压控制层、以及用于高迁移率和减小的随机掺杂波动性能的本征沟道。每种方法具有不同的优点和缺点。通常，当在半导体管芯上构建晶体管元件时考虑两种折衷，即工艺中步骤的数量（涉及制造成本）和沟道形成（涉及晶体管性能）。较少的掩模步骤和需要用来构建一个设计的总步骤转化为更低的构建成本。在制造工艺的热循环中较晚形成沟道有利于控制沟道掺杂分布，以及避免不希望的污染物从晶体管设计的其它部分扩散进入该沟道。
图1A至1K示出了用于形成具有晶体管元件的结构100的均厚沟道和浅沟槽隔离的最后方法，该晶体管元件具有三层沟道堆栈以优化整体晶体管性能。在图1A中，该工艺开始，其中P+衬底101和形成在其上的P-硅外延层102用于结构100。最初的图案化是通过形成光刻胶掩模104和蚀刻移除光刻胶掩模104的预期部分以暴露用于第一晶体管元件（在此实例中为NMOS晶体管）的区域106来执行的。在图1B中，进行离子注入以形成p阱区108。进行另一离子注入，以形成屏蔽层110。进行另一离子注入，以形成阈值电压控制层112。可替代地，阈值电压控制层112可以通过从屏蔽层110的扩散而形成。
在图1C中，光刻胶层104被移除，并且新的光刻胶层114被图案化，以暴露用于第二晶体管元件的区域116，在此实例中第二晶体管元件为PMOS晶体管。在图1D中，进行离子注入以形成n阱区118。进行另一离子注入，以形成屏蔽层120。进行另一离子注入，以形成阈值电压控制层122。可替代地，阈值电压控制层122可以通过从屏蔽层120的扩散而形成。
在图1E中，光刻胶层114被移除，跨越PMOS晶体管116和NMOS晶体管106生长本征硅的外延层124。外延层124成为用于PMOS晶体管116和NMOS晶体管106中的每一个的沟道。在图1F中，用于从NMOS晶体管116隔离开PMOS晶体管106的初始步骤的执行是通过在外延层124上沉积垫氧化物（pad oxide）层126、在垫氧化物层126上沉积氮化物层128、以及将光刻胶掩模130图案化，以留下暴露区域132用于浅沟槽隔离区。
在图1G中，氮化物隔离层128、氧化物垫层126、外延层124、阈值电压控制层112和122、屏蔽层110和120、n阱区118、p阱区108及硅外延层102和衬底101的部分在区域132中被刻蚀掉，以留下沟槽。在图1H中，光刻胶掩模130被除去，并且使衬里（liner）134生长在结构100上并且到该沟槽中。
在图1I中，沟槽被填充有氧化物，以建立浅沟槽隔离区136。执行回流退火，以使结构100中的空隙最小化，并且执行固化退火，以便使结构100致密化和硬化并在其中产生所需的应力。然后执行平面化工艺，以降低到氮化物隔离层128。在图1J中，氮化物隔离层128和垫氧化物层126被蚀刻掉。在图1K中，使用具有侧墙142的常规的栅叠堆栈138和140形成、源极/漏极形成（144、146、148和150）以及硅化物形成152，来完成PMOS晶体管116和NMOS晶体管106。
图2A至图2I示出了用于形成具有晶体管元件的结构200的均厚沟道和浅沟槽隔离的第一方法，该晶体管元件具有三层沟道堆栈，以优化整体晶体管性能。在图2A中，该工艺开始，其中P+衬底201和形成在其上的P-硅外延层202用于结构200。用于隔离晶体管元件的最初步骤是通过在结构200上沉积垫氧化物层226、在垫氧化物层226上沉积氮化物层228、并使光刻胶掩模230图案化，以便留下用于浅沟槽隔离区的暴露区域232来执行的。氮化物隔离层228、氧化物垫层226、硅外延层202和衬底201的部分在区域232中被蚀刻掉，以留下沟槽。在图2B中，光刻胶掩模230被除去，并且使衬里234生长在结构200上并且到该沟槽中。
在图2C中，沟槽被填充有氧化物，以建立浅沟槽隔离区236。执行回流退火，以使结构200中的空隙最小化，并且执行固化退火，以便使结构200致密化和硬化，并在其中产生所需的应力。然后执行平面化工艺，以降低到氮化物隔离层228。在图2D中，氮化物隔离层228和垫氧化物层226被蚀刻掉。最初的图案化是通过形成光刻胶掩模204和蚀刻移除光刻胶掩模204的预期部分，以暴露用于第一晶体管元件的区域206，在此实例中第一晶体管元件为NMOS晶体管。
在图2E中，执行离子注入以形成p阱区208。执行另一离子注入，以形成屏蔽层210。执行另一离子注入，以形成阈值电压控制层212。可替代地，阈值电压控制层212可以通过从屏蔽层210的扩散而形成。
在图2F中，光刻胶层204被移除，并且新的光刻胶层214被图案化，从而暴露用于第二晶体管元件的区域216，在此实例中第二晶体管元件为PMOS晶体管。在图2G中，执行离子注入以形成n阱区218。执行另一离子注入，以形成屏蔽层220。执行另一离子注入，以形成阈值电压控制层222。可替代地，阈值电压控制层222可以通过从屏蔽层220的扩散而形成。
在图2H中，光刻胶层214被移除，并且使本征硅的外延层224跨越PMOS晶体管216和NMOS晶体管206生长。接着移除形成在浅沟槽隔离区域236上的那部分外延层224。可替代地，可使单独的外延层224分别生长以用于PMOS晶体管216和NMOS晶体管206。以此方式，不同厚度的外延层224可以形成在不同的晶体管元件之间。另外，可以任选地执行跨越所有晶体管元件的具有一个厚度的均厚外延沟道生长（具有浅沟槽隔离区域236上的移除）的组合，接着执行仅针对那些被期望为具有比结构200中其它晶体管元件更厚的外延层224的晶体管元件的选择性的对外延层224的附加生长，以形成在它们的各自外延层224具有不同厚度的晶体管元件。作为一个例子，特定的晶体管元件可以使其沟道层以25nm的外延生长开始，以便在制造工艺之后以10nm厚度的沟道层结束。另一晶体管元件可以使其沟道层开始于更大厚度的外延生长，以便在制造工艺完成之后获得更大的最终厚度。
在图2I中，使用具有侧墙242的常规的栅极堆栈238和240形成、源极/漏极形成（244、246、248和250）以及硅化物形成252来完成PMOS晶体管216和NMOS晶体管206。
图3A至图3I示出了用于形成具有晶体管元件的结构300的多个均厚外延层和浅沟槽隔离的最后方法，该晶体管元件具有三层沟道堆栈，以优化整体晶体管性能。该工艺开始于图3A，其中P+衬底301和形成在其上的P-硅外延层302用于结构300。最初的图案化是通过形成光刻胶掩模304和蚀刻移除光刻胶掩模304的预期部分从而暴露用于第一晶体管元件的区域306来执行的，在此实例中第一晶体管元件为NMOS晶体管。可选地，均厚屏蔽层（未示出）可以是在光刻胶掩模304的图案化之前外延生长或沉积在结构300上。在图3B中，执行离子注入以形成p阱区308。执行另一离子注入，以在p阱区308中或在可选的均厚外延层中与NMOS晶体管元件306相关联的那部分中形成屏蔽层310。
在图3C中，光刻胶层304被移除，并且新的光刻胶层314被图案化，从而暴露用于第二晶体管元件的区域316，在此实例中第二晶体管元件为PMOS晶体管。在图3D中，执行离子注入以形成n阱区318。执行另一离子注入，以在n阱区318中或在可选的均厚外延层中与PMOS晶体管元件316相关联的那部分中形成屏蔽层320。
在图3E中，光刻胶层314被移除，使本征硅的外延层323跨越PMOS晶体管316和NMOS晶体管306生长。外延层323将变成分别用于PMOS晶体管316和NMOS晶体管306中的每个的单独的阈值电压控制层322和312。新的光刻胶层305被图案化，以暴露NMOS晶体管306。在图3F中，使外延层323的暴露部分受到离子注入，以形成用于NMOS晶体管306的阈值电压控制层312。
在图3G中，光刻胶层305被移除，并且新的光刻胶层325被图案化，从而暴露PMOS晶体管元件316。在图3H中，使外延层323的暴露部分受到离子注入，以形成用于PMOS晶体管316的阈值电压控制层322。
在图3I中，光刻胶层325被移除，使本征硅的外延层324跨越PMOS晶体管116和NMOS晶体管106生长。外延层324变成用于PMOS晶体管316和NMOS晶体管306中的每个的沟道。可以如关于图1F至1K的上文所示和描述的那样，来执行隔离和进一步处理。
尽管未示出，可以类似于关于图2A至2D的上文所示和描述的那样，来在P+衬底301和P-硅外延层302上实施浅沟槽隔离第一工艺。接着，可以如上文所述那样形成均厚外延层，以便随后建立屏蔽层、阈值电压控制层、以及用于PMOS晶体管元件116和NMOS晶体管元件106的沟道层。需要额外的步骤来除去形成于隔离区上的任何外延层。
在上述每个工艺中，可以以不同的方式来执行屏蔽层和阈值电压控制层的形成。可以通过到p阱区中的离子注入、通过掺杂材料原位沉积或生长、或通过本征硅外延生长接着进行离子注入，来形成屏蔽层。可以通过掺杂材料原位沉积或生长、或通过本征硅外延生长接着进行离子注入，来形成阈值电压控制层。通过本征硅外延生长来形成沟道层。
在各制造工艺中被用于PMOS晶体管元件的屏蔽层的材料可包括砷、磷和/或锑。当将砷用于PMOS晶体管元件时，砷的离子注入在沟道层的外延生长之前进行（并且也在执行该工艺步骤的阈值电压控制层的外延生长之前进行）。为了防止屏蔽层材料的扩散，可以使用具有较低扩散特性的材料。对于PMOS晶体管元件，在制造工艺的热循环中，锑的扩散小于砷。使用锑解决了屏蔽层中的材料扩散到外延沟道层中的问题。
图4示出了砷和锑的垂直掺杂分布700。由于锑具有比砷更低的扩散，在相同的掺杂能量和掺杂剂浓度下，与砷相比，锑的屏蔽掺杂分布更尖锐。针对相同厚度的外延沟道层，锑的这一更尖锐的掺杂分布导致比在砷作为屏蔽注入物的情况下将实现的漏电流更高的漏电流（Id-off）。图5示出了针对砷和锑的Id-off和Id-on的比较图800。砷提供了比锑更小的漏电流。针对锑的漏电流在较高注入能量下变得更差。然而，漏电流的改进是通过将砷加入锑注入物中而实现的。
能够减小针对锑的漏电流的另一种方式是减小厚度，或者与NMOS晶体管元件相比，PMOS晶体管元件的外延沟道层具有更小的厚度。图6示出了在不同掺杂浓度和不同厚度的外延沟道层下针对锑的Id-off和Id-on的比较图900。通常，当外延沟道层的厚度从最薄变到最厚，使用锑注入物的漏电流从相对较低的水平增加到相对较高水平。因此，外延沟道层厚度的减小导致使用锑屏蔽注入物的晶体管元件的漏电流的减小。
尽管外延沟道层的厚度减少是可实现的，但是实施到制造过程中是成本很高的。虽然上文已经讨论了提供得到不同外延沟道层厚度的能力的技术，这样的技术仍然导致制造过程中执行的附加步骤。一种为了针对锑屏蔽注入物来避免减小外延沟道层厚度的技术是在用于PMOS晶体管元件的外延沟道层生长之后注入锑屏蔽。与砷相比，锑的减少的蔓延和扩散，使得能够在epi技术之后使用这种注入，实现可接受的掺杂分布。通过在沟道层的外延生长之前，注入或以其它方式形成用于NMOS晶体管元件的屏蔽层，通过本征硅外延生长形成所述沟道层，然后将PMOS晶体管元件的屏蔽层注入穿过外延沟道层，能够将该技术集成到全CMOS工艺和上述的多种工艺中。图7示出了针对沟道层外延生长之后注入的不同掺杂浓度下的锑的Id-off和Id-on的比较图1000。正如可以看到的，相比于外延沟道形成之前注入的砷，漏电流的减小是通过该工艺获得的。当锑在外延沟道层形成后被注入时，在足够高的注入能量的情况下，锑的峰值可以位于外延沟道层表面下方10至30nm处。当使用2e13原子/cm2的掺杂浓度或比具有较高掺杂浓度的穿过外延沟道层注入的锑更低的掺杂浓度时，能够得到更好的结果。
另一种替代的工艺是使用利用锑和较快扩散n型掺杂物（例如砷）的双注入，这二者在外延沟道层的沉积或其它形成之前完成。相比于仅用锑，将砷扩散到阈值电压控制层中将增加阈值电压并减小漏电流。砷的注入能量通常是等于或小于锑的注入能量。砷的掺杂浓度可以被选择，以使得掺杂分布峰值浓度等于或小于锑掺杂浓度的掺杂分布峰值浓度。尽管被公开为锑屏蔽层和砷阈值电压控制层，可以期望的是具有砷屏蔽层和锑阈值电压控制层。
在锑注入之后执行退火步骤以改善锑掺杂剂的活化也可以是很有用的。该退火步骤通常为950℃至1050℃的范围，其持续时间从几毫秒到几秒钟。在形成外延沟道层之前，在砷注入之后执行退火步骤也可以是很有用的。该退火步骤通常为800℃至1000℃的范围，其持续时间从几毫秒到几秒钟。
图8示出了模拟的掺杂分布，其中锑在20keV的能量下被注入，掺杂浓度为1.5e13原子/cm2，砷在1keV的能量下被注入，掺杂浓度为5e12原子/cm2，并且在800℃的温度下执行退火，持续时间是一秒。虚线示出了组合的砷-锑注入。图9示出了模拟的掺杂分布，其中锑在10keV的能量下被注入，掺杂浓度为1.5e13原子/cm2，从而形成屏蔽层，砷在4keV的能量下被注入，掺杂浓度为5e12原子/cm2，从而形成阈值电压控制层，并且在800℃至1000℃的温度下恒定退火时间是一秒。图10示出了类似的掺杂分布，其中退火温度是恒定的900℃，但采用不同的退火时间。图11示出了除了具有在800℃的退火温度下更高能量的砷注入能量10keV之外，具有与图9相同的条件模拟的掺杂分布。图12是类似的掺杂分布，除了具有20keV的砷注入能量，高于10keV的锑注入能量。虚线示出了组合注入的分布。
锑的分布基本上不会由退火改变。砷退火具有减少了进入后续形成的外延沟道层中的砷扩散的效果。较高的退火温度和较长的退火持续时间对于抑制砷扩散到外延沟道层中是更有效的，而较低的退火温度和较短的退火持续时间允许更多的扩散。因此，通过控制砷的扩散，退火温度和时间可以用来设置阈值电压。该砷退火步骤可结合锑退火步骤来完成或作为单个退火而没有锑退火来完成。该外延沟道层可以在退火后随后被沉积。
另一种替代的工艺是在外延沟道层形成之前用锑注入或以其它方式形成屏蔽层，然后在外延沟道层形成后注入锑。执行该工艺来调整PMOS晶体管元件的阈值电压。图13示出了模拟的掺杂分布，其中在沉积外延沟道层之前，在1.5e13原子/cm2的掺杂浓度下以20keV的能量注入锑，接着在沉积20nm的外延沟道层之后，在1.0e13原子/cm2的掺杂浓度下以30keV的能量注入锑。图14示出了类似的掺杂分布，除了具有在20keV的能量下的第二次锑注入之外。也可以在外延沟道层形成后注入砷，而不是锑，尽管对于该技术，锑的尖锐掺杂分布是更好的。
图8至图14中使用的20nm的外延厚度是用于说明的目的。如在特定情况下设备性能所需要的那样，外延层的厚度可以大于或小于20nm。
尽管已经参照特定实施例详细描述了本公开，但应当理解的是，可以进行各种其他改变、替代和变更，而不脱离本发明的精神和所附权利要求的范围。例如，尽管未示出，分接到晶体管元件的阱区的主体分接头可以被形成，以提供进一步的阈值电压控制。虽然本公开包括参照特定工艺排序的描述，也可以遵循其他工艺排序，而且可执行其它附带的工艺步骤，以实现这里所讨论的最终结果。此外，一组附图中所示的工艺步骤也可以根据需要被并入到另一组附图中。
本领域技术人员可以发现许多其它改变、替代、变化、变更和修改，并且本公开旨在包括如落在所附权利要求的精神和范围内的所有这些改变、替换、变化、变更和修改。此外，本公开并不旨在以任何方式受限于说明书中的未否则被反映在所附权利要求中的任何表述。

Claims (17)

1.一种用于制造具有沟道堆栈的半导体结构的方法，包括：
在PMOS晶体管元件的栅极下方形成用于屏蔽所述栅极上的电荷的屏蔽层；
在所述PMOS晶体管元件的所述屏蔽层上方形成包含锑的阈值电压控制层；
在所述PMOS晶体管元件的所述屏蔽层上方形成所述阈值电压控制层之后，在所述PMOS晶体管元件的所述阈值电压控制层上形成外延沟道层；
在NMOS晶体管元件的栅极下方形成用于屏蔽所述栅极上的电荷的屏蔽层；
在所述NMOS晶体管元件的所述屏蔽层上形成阈值电压控制层；
在所述NMOS晶体管元件的所述屏蔽层上形成所述阈值电压控制层之后，在所述NMOS晶体管元件的所述阈值电压控制层上形成外延沟道层；并且
其中，所述PMOS晶体管元件的所述外延沟道层具有与所述NMOS晶体管元件的所述外延沟道层不同的厚度，其中所述厚度根据相应的栅极与阈值电压控制层之间的距离来测量。
2.如权利要求1所述的方法，其中，形成所述PMOS晶体管元件的所述阈值电压控制层包括从所述PMOS晶体管元件的所述屏蔽层扩散锑。
3.如权利要求1所述的方法，其中，形成所述PMOS晶体管元件的所述屏蔽层包括注入砷和锑两者。
4.如权利要求1所述的方法，其中，所述PMOS晶体管元件和所述NMOS晶体管元件的至少其中之一的所述阈值电压控制层和所述外延沟道层是在没有离子注入的情况下形成的。
5.如权利要求1所述的方法，还包括：
在形成所述PMOS晶体管元件和所述NMOS晶体管元件的所述外延沟道层之后，形成分离所述PMOS晶体管元件和所述NMOS晶体管元件的隔离区。
6.一种具有沟道堆栈的半导体结构，包括：
PMOS晶体管元件，其具有在栅极下方的用于屏蔽所述栅极上的电荷的屏蔽层、在所述屏蔽层上方的含有锑的阈值电压控制层、以及在所述阈值电压控制层上的外延沟道层；
NMOS晶体管元件，其具有在栅极下方的用于屏蔽所述栅极上的电荷的屏蔽层、在所述屏蔽层上的阈值电压控制层、以及在所述阈值电压控制层上的外延沟道层；
其中，所述PMOS晶体管元件的所述外延沟道层具有与所述NMOS晶体管元件的所述外延沟道层不同的厚度，其中所述厚度根据相应的栅极与阈值电压控制层之间的距离来测量；
其中，所述PMOS晶体管元件和所述NMOS晶体管元件的所述外延沟道层的至少一部分是公共的均厚层。
7.如权利要求6所述的半导体结构，其中，所述PMOS晶体管元件的所述阈值电压控制层是通过穿过其外延沟道层的离子注入、在所述屏蔽层上的锑注入和/或从所述屏蔽层的锑扩散中的一种或多种而形成的。
8.如权利要求6所述的半导体结构，还包括：
分离所述PMOS晶体管元件和所述NMOS晶体管元件的隔离区，所述隔离区形成于所述PMOS晶体管元件和所述NMOS晶体管元件的所述外延沟道层之后。
9.如权利要求6所述的半导体结构，其中，所述PMOS晶体管元件的所述屏蔽层和所述阈值电压控制层的至少其中之一包含砷。
10.如权利要求6所述的半导体结构，还包括：
耦接到所述PMOS晶体管元件和所述NMOS晶体管元件的至少其中之一的阱区的主体分接头以提供进一步的阈值电压控制。
11.一种具有沟道堆栈的半导体结构，包括：
PMOS晶体管元件，其具有，
高掺杂的用于屏蔽栅极上的电荷的屏蔽层，所述屏蔽层具有第一峰值掺杂浓度，所述屏蔽层被注入在衬底中、在所述栅极之下的大于10纳米的深度处；
阈值电压控制层，其包括防扩散锑掺杂剂，所述阈值电压控制层是通过从所述屏蔽层的扩散以及直接注入中的至少一种而形成的，其中，所述阈值电压控制层具有比所述高掺杂屏蔽层的所述第一峰值掺杂浓度小的第二峰值掺杂浓度；
外延沟道层，形成在所述阈值电压控制层上；以及
NMOS晶体管元件，其具有形成在栅极下方的用于屏蔽所述栅极上的电荷的高掺杂的屏蔽层、形成所述屏蔽层上的阈值电压控制层、以及形成在所述阈值电压控制层上的外延沟道层；
其中所述PMOS晶体管元件与所述NMOS晶体管元件的所述外延沟道层的一部分具有不同的厚度，其中所述厚度根据相应的栅极与阈值电压控制层之间的距离来测量。
12.如权利要求11所述的半导体结构，其中，所述PMOS晶体管元件和所述NMOS晶体管元件的所述外延沟道层的至少一部分被形成为公共的均厚层。
13.如权利要求11所述的半导体结构，其中，所述PMOS晶体管元件和所述NMOS晶体管元件的所述外延沟道层的至少一部分被形成为独立生长的单独外延层。
14.如权利要求11所述的半导体结构，其中，所述PMOS晶体管元件的所述阈值电压控制层是通过穿过其外延沟道层的离子注入而形成的。
15.如权利要求11所述的半导体结构，其中，所述PMOS晶体管元件的阈值电压控制层是通过在所述PMOS晶体管元件的屏蔽层上进行锑注入和从所述PMOS晶体管元件的屏蔽层上进行锑扩散中的一种而形成的。
16.如权利要求11所述的半导体结构，还包括：
分离所述PMOS晶体管元件和所述NMOS晶体管元件的隔离区，所述隔离区形成于所述PMOS晶体管元件和所述NMOS晶体管元件的所述外延沟道层之后。
17.如权利要求11所述的半导体结构，还包括：
耦接到所述PMOS晶体管元件和所述NMOS晶体管元件的至少其中之一的阱区的主体分接头以提供进一步的阈值电压控制。
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