CN101416278B - 简化的间距加倍工艺流程 - Google Patents

简化的间距加倍工艺流程 Download PDF

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CN101416278B
CN101416278B CN2007800125255A CN200780012525A CN101416278B CN 101416278 B CN101416278 B CN 101416278B CN 2007800125255 A CN2007800125255 A CN 2007800125255A CN 200780012525 A CN200780012525 A CN 200780012525A CN 101416278 B CN101416278 B CN 101416278B
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阿尔达万·尼鲁曼德
周葆所
拉马康斯·阿拉帕蒂
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Abstract

一种用于制造半导体装置(100)的方法包含对光致抗蚀剂材料层(111)进行图案化以形成多个心轴(124)。所述方法进一步包含通过原子层沉积(ALD)工艺在所述多个心轴(124)上沉积氧化物材料(126)。所述方法进一步包含从暴露的水平表面各向异性地蚀刻所述氧化物材料(126)。所述方法进一步包含选择性地蚀刻光致抗蚀剂材料(111)。

Description

简化的间距加倍工艺流程
技术领域
本发明一般来说涉及集成电路制造，且更具体地说，涉及用于形成双倍间距集成电路特征的简化工艺。
背景技术
随着对现代电子装置的便携性、计算能力、存储器容量和能量效率的需求的增长，集成电路正不断地变小。因此，集成电路构成特征(例如，电气装置和互连线宽度)的大小也在不断地减小。特征大小减小的趋势在例如动态随机存取存储器(dynamicrandom access memory，“DRAM”)、快闪存储器、非易失性存储器、静态随机存取存储器(“static random access memory，SRAM”)、铁电(ferroelectric，“FE”)存储器、逻辑门阵列等存储器电路或装置中是明显的。
举例来说，DRAM通常包含数百万个相同的电路元件，所述电路元件被称为存储器单元。典型的存储器单元由两个电气装置组成：存储电容器和存取场效应晶体管。每一存储器单元为可存储一个二进制数字(“位”)数据的可寻址位置。可通过晶体管将位写入到存储器单元，且通过感测存储电容器的参考电极上的电荷来读取所述位。通过减小这些构成电气装置和将其互连的导线的大小，并入有存储器单元的存储器装置的大小可同样被减小。以类似方式，可通过将更多存储器单元安装到存储器装置中来增加这些装置的存储容量。
作为另一实例，快闪存储器(例如，电可擦除可编程只读存储器或“EEPROM”)是通常以区块为单位而非一次一个字节地擦除和重新编程的一类存储器。典型的快闪存储器包含存储器阵列，所述存储器阵列包括大量存储器单元。存储器单元包括能够容纳电荷的浮栅场效应晶体管。存储器单元中的数据由浮动栅极上电荷的存在或不存在来确定。通常将所述单元分组成被称作“擦除区块”的部分。通常将快闪存储器阵列的存储器单元布置成“或非”结构(在其中，每一存储器单元直接耦合到位线)或“与非”结构(在其中，存储器单元耦合成单元“串”，使得每一单元间接地耦合到位线，且为了存取需要激活串中的其它单元)。可通过对浮动栅极进行充电来在随机基础上对擦除区块内的存储器单元进行电编程。可通过区块擦除操作将电荷从浮动栅极移除，其中在单次操作中擦除所述擦除区块中的所有浮动栅极存储器单元。
如从此处所提供的实例明显看出，存储器装置通常包括电气装置和用于使所述电气装置互连的导体的较大图案或阵列。将此图案的“间距”界定为图案中两个相邻特征中的相同点之间的距离。这些特征通常由例如绝缘体或导体的材料中的开口界定，且彼此由例如绝缘体或导体的材料间隔开。因此，间距可被理解为特征的宽度和使所述特征与相邻特征隔开的间隔的宽度的总和。
发明内容
在本发明的一个实施例中，一种用于制造半导体装置的方法包含对光致抗蚀剂材料层进行图案化以形成多个心轴。所述方法进一步包含使用原子层沉积技术来将氧化物材料沉积到所述多个心轴上。所述方法进一步包含从暴露的水平表面各向异性地蚀刻所述氧化物材料。所述方法进一步包含相对于所述氧化物材料而选择性地蚀刻光致抗蚀剂材料，从而形成多个氧化物间隔物。
在本发明的另一实施例中，一种形成存储器装置的方法包含在衬底上形成多个心轴。所述心轴由衬底的暴露部分隔开。所述方法进一步包含使用在小于约100℃的温度下进行的原子层沉积技术来在心轴上且在衬底的暴露部分上沉积间隔物材料。所述方法进一步包含从(a)所述多个心轴的暴露水平表面和(b)衬底的暴露部分各向异性地蚀刻间隔物材料。将间隔物材料保留在所述多个心轴的垂直侧壁上。
在本发明的另一实施例中，一种形成集成电路的方法包含在硬掩模层上形成多个心轴。所述心轴包含感光材料。所述方法进一步包含使用原子层沉积技术来沉积间隔物材料。间隔物材料覆盖所述多个心轴。所述方法进一步包含从水平表面各向异性地蚀刻间隔物材料，从而使感光材料暴露。所述方法进一步包含在各向异性地蚀刻间隔物材料之后移除暴露的感光材料，从而在硬掩模层上留下间隔物图案。所述方法进一步包含将所述间隔物图案转印到硬掩模层。所述方法进一步包含从硬掩模层蚀刻间隔物图案。
在本发明的另一实施例中，一种集成电路制造方法包含使用微影技术来在硬掩模层上界定多个狭长心轴。所述心轴包含光致抗蚀剂材料。所述方法进一步包含在心轴周围形成间隔物图案。所述间隔物图案的间距小于微影技术的最小可分辨间距。间隔物图案由氧化物材料形成。在小于约100℃的温度下使用原子层沉积技术来沉积所述间隔物图案。
在本发明的另一实施例中，一种用于制造半导体装置的方法包含对光致抗蚀剂材料层进行图案化以在装置阵列区域中形成多个心轴。所述方法进一步包含在所述多个心轴上且在装置外围区域上沉积氧化物材料。所述方法进一步包含在装置阵列区域中从暴露的水平表面各向异性地蚀刻氧化物材料。所述方法进一步包含在装置外围区域中在氧化物材料上形成光致抗蚀剂材料图案。所述方法进一步包含从装置阵列区域且从装置外围区域选择性地蚀刻光致抗蚀剂材料。
在本发明的另一实施例中，一种形成存储器装置的方法包含在存储器装置的阵列区域中在衬底上方形成多个心轴。所述心轴视情况包含光致抗蚀剂材料。所述心轴由衬底的暴露部分隔开。所述方法进一步包含在心轴上、在衬底的暴露部分上且在存储器装置的外围区域上沉积间隔物材料。所述方法进一步包含在存储器装置的外围区域中在间隔物材料上沉积外围掩模。所述方法进一步包含从暴露的水平表面各向异性地蚀刻间隔物材料。将间隔物材料保留在(a)阵列区域中，心轴的垂直侧壁上和(b)外围区域中，衬底与外围掩模之间。
在本发明的另一实施例中，一种形成集成电路的方法包含在阵列区域中在硬掩模层上形成多个心轴。所述心轴包含光致抗蚀剂材料。所述方法进一步包含在阵列区域上和在围绕所述阵列区域的外围区域上沉积氧化物材料。所述氧化物材料覆盖所述多个心轴。所述方法进一步包含在外围区域中在氧化物材料上形成光致抗蚀剂材料图案。所述方法进一步包含在阵列区域中从水平表面各向异性地蚀刻氧化物材料。所述方法进一步包含在各向异性地蚀刻氧化物材料之后从阵列区域和外围区域移除暴露的光致抗蚀剂材料。
在本发明的另一实施例中，一种集成电路制造方法包含使用微影技术来在集成电路阵列区域中在硬掩模层上界定多个狭长心轴。所述心轴包含光致抗蚀剂材料。所述方法进一步包含在所述多个狭长心轴周围形成间隔物图案。所述间隔物图案的间距小于微影技术的最小可分辨间距。所述间隔物是由在小于约100℃的温度下沉积的氧化物材料形成。
在本发明的另一实施例中，一种部分形成的集成电路包含衬底。所述部分形成的集成电路进一步包含位于所述衬底上的硬掩模层。所述部分形成的集成电路进一步包含多个间隔物回路，所述多个间隔物回路直接形成于硬掩模层上，且至少部分地位于所述部分形成的集成电路的阵列区域中。所述部分形成的集成电路进一步包含至少部分地界定在所述部分形成的集成电路的外围区域中的掩模，其中所述掩模也直接形成于所述硬掩模层上。
附图说明
在附图中说明本文所揭示的集成电路和集成电路制造技术的示范性实施例，附图仅用于达到说明性目的，且不必按比例绘制。附图包含以下各图，其中相同标号指示相同部分。
图1A是上面形成有多个掩模线的衬底的示意性横截面图。
图1B是在执行将掩模图案转印到临时层中的各向异性蚀刻工艺之后图1A的衬底的示意性横截面图。
图1C是在去除掩模线和执行各向同性“缩小”蚀刻之后图1B的衬底的示意性横截面图。
图1D是在留在临时层中的心轴上席状沉积(blanket depositing)间隔物材料之后图1C的衬底的示意性横截面图。
图1E是在执行定向间隔物蚀刻以留下多倍间距特征或间隔物之后图1D的衬底的示意性横截面图。
图1F是在移除心轴之后图1E的衬底的示意性横截面图。
图2A是示范性部分形成的集成电路的示意性横截面图。
图2B是图2A的部分形成的集成电路的示意性俯视图。
图3A是在光致抗蚀剂层中的阵列区域中形成线之后图2A的示范性部分形成的集成电路的示意性横截面图。
图3B是图3A的部分形成的集成电路的示意性俯视图。
图4A是在执行修整蚀刻之后图3A的示范性部分形成的集成电路的示意性横截面图。
图4B是图4A的部分形成的集成电路的示意性俯视图。
图5A是在光致抗蚀剂心轴上席状沉积低温间隔物材料之后图4A的示范性部分形成的集成电路的示意性横截面图。
图5B是图5A的部分形成的集成电路的示意性俯视图。
图6A是在外围区域中界定特征之后图5A的示范性部分形成的集成电路的示意性横截面图。
图6B是图6A的部分形成的集成电路的示意性俯视图，其中外围光致抗蚀剂层席状沉积在大体上整个外围区域上
图6C是图6A的部分形成的集成电路的示意性俯视图，其中外围光致抗蚀剂层经图案化以界定外围特征。
图6D是图6A的部分形成的集成电路的示意性俯视图，其中外围光致抗蚀剂层部分地重叠低温间隔物材料。
图7A是在对低温间隔物材料执行各向异性蚀刻之后图6A的示范性部分形成的集成电路的示意性横截面图。
图7B是图7A的部分形成的集成电路的示意性俯视图。
图8A是在移除暴露的光致抗蚀剂材料之后图7A的示范性部分形成的集成电路的示意性横截面图。
图8B是图8A的部分形成的集成电路的示意性俯视图。
图9A是在将间隔物图案转印到下伏硬掩模层中之后图8A的示范性部分形成的集成电路的示意性横截面图。
图9B是图9A的部分形成的集成电路的示意性俯视图。
具体实施方式
随着包含存储器装置的电气装置和导体的大小变得越来越小，对用于形成这些特征的技术提出了更高的要求。举例来说，通常使用光刻来在衬底上对装置特征(例如导线)进行图案化。可使用间距的概念来描述这些特征的大小。然而，由于光学因素(例如，光或辐射波长)，光刻技术具有最小间距，低于此最小间距，不能可靠地形成特征。因此，光刻技术的最小间距可限制特征大小的减小。
一种针对使光刻技术的能力扩展到其最小间距外而提出的技术是“间距加倍”技术。在图1A到图1F中说明此技术，且在第5,328,81号美国专利(1994年7月12日发布)中描述此技术，所述专利的整个揭示内容以引用的方式并入本文中。参看图1A，首先使用光刻来在上覆在临时或消耗性材料层20和衬底30上的光致抗蚀剂层中形成线10的图案。用于执行光刻的一般波长包括(但不限于)157nm、193nm、248nm或365nm。在执行随后的处理步骤之前，视情况地使用各向同性蚀刻来使线10缩小。如图1B中所示，接着通过蚀刻步骤(例如，各向异性蚀刻步骤)将所述图案转印到消耗性材料层20，从而形成占位区(placeholder)或心轴(mandrel)40。如图1C中所示，可剥离光致抗蚀剂线10，且可各向同性地蚀刻心轴40以增加相邻心轴40之间的距离。如图1D中所示，随后将间隔物材料层50沉积在心轴40上。如图1E中所示，接着通过在定向间隔物蚀刻中优先从水平表面蚀刻间隔物材料来在心轴40的侧面上形成间隔物60。如图1F中所示，接着移除其余的心轴40，仅留下间隔物60，其共同充当用于图案化的掩模。因此，在给定图案区以前界定一个特征和一个间隔(每一者具有宽度F，间距为2F)的情况下，同一图案区现在包括如由间隔物60界定的两个特征和两个间隔(每一者具有宽度1/2F，间距为F)。因此，通过使用间距加倍技术来有效地减小光刻技术可能具有的最小特征大小。
虽然实际上是使用这些技术来减小间距，但此间距减小常规上被称作“间距加倍”，或更一般来说，被称作“间距倍增”。这是因为这些技术允许衬底的给定区域中的特征数目加倍或更一般来说倍增。因此，使用所述常规术语，间距“倍增”某一因数实际上涉及使所述间距减小所述因数。本文中保留所述常规术语。通过层叠地形成多个间隔物层，可使可界定的特征大小变得更加小。因此，术语“间距倍增”和“间距加倍”大体上涉及所述工艺，不管使用间隔物形成工艺的次数是多少。
用于在存储器装置的外围和阵列中形成图案的一些所提出的方法涉及使用两个单独的碳层。举例来说，在一个此种方法中，用于界定间隔物回路的心轴形成于上部碳层中。在执行间距加倍和外围图案化工艺之后，将阵列图案转印到下部碳层。虽然此工艺确实允许在阵列区域和外围区域中形成具有不同大小的特征，但使用低温氧化物材料来界定间隔物回路允许心轴由现存光致抗蚀剂层形成。这有利地允许省略顶部碳层，从而简化生产。
根据前述内容，已开发出用于在半导体或集成电路装置中形成间距加倍特征的经简化且改进的技术。
在某些实施例中，待转印到衬底的特征图案的间距低于用于处理衬底的光刻技术的最小间距。另外，某些实施例可用于形成特征阵列，包括逻辑或栅极阵列以及易失性和非易失性存储器装置，例如，DRAM、相变存储器(phase change memory，“PCM”)、可编程导体随机存取存储器(programmable conductor random access memory，“PCRAM”)、只读存储器(read only memory，“ROM”)、快闪存储器。在此些装置中，间距倍增可用于(例如)在装置的阵列区域中形成晶体管栅极电极和导线。视情况，常规光刻可以特定序列与前述简化间距加倍技术组合，以在装置的外围区域中同时处理对逻辑电路(例如，局部互连和互补金属氧化物半导体(complementary metal oxidesemiconductor，“CMOS”)电路)有用的较大特征。举例来说，逻辑阵列可为现场可编程栅极阵列(“FPGA”)，其具有类似于存储器阵列的核心阵列和带支持逻辑电路的外围设备。在图中说明且在本文中描述制造存储器装置期间的示范性遮蔽步骤。
图2A和图2B分别说明示范性部分制造的集成电路100(例如，存储器装置)的示意性横截面图和俯视图。图2B说明集成电路100包含由外围区域104围绕的中央阵列区域102。将了解，在制造集成电路100之后，阵列区域102通常将密集地组装有导线和电气装置(例如，晶体管和电容器)。如本文中所论述，可使用间距倍增来在阵列区域102中形成特征。
另一方面，外围区域104视情况可包括比阵列区域102中的特征更复杂且/或更大的特征。通常使用常规光刻而非间距倍增来对这些更复杂且/或更大的特征进行图案化，其实例包括各种类型的逻辑电路。位于外围区域104中的逻辑电路的几何复杂性使在集成电路100的此区域中使用间距倍增较为困难。相反，阵列图案典型的规则栅格有益于间距倍增。另外，外围区域104中的一些装置可能由于电约束条件而需要较大的几何形状，从而使得针对此些装置，间距倍增的优势比常规光刻的优势小。除了相对比例、相对位置方面的可能差异之外，集成电路100中外围区域104和阵列区域102的数目在其它实施例中也可能改变。在单独使用不同处理技术来在阵列区域102和外围区域104中形成特征的实施例中，可在处理阵列区域期间遮蔽外围区域104。
图2A说明部分形成的集成电路100包括上方形成有第一硬掩模层108的衬底106。在示范性实施例中，第一硬掩模层108包含例如以下材料的材料：氮化硅、氧化硅或有机材料，例如无定形碳材料、聚合物材料或自旋介电材料(spin on dielectric material)。在优选实施例中，第一硬掩模层108包含一种形式的无定形碳，其对光高度透明且通过对用于光对准的光的波长透明来提供对光对准的进一步改进。在其它经修改的实施例中，省略第一硬掩模层108。
可选第二硬掩模层110形成于第一硬掩模层108上。第二硬掩模层110优选包含无机材料。用于第二硬掩模层110的示范性材料包括氮化硅、多晶硅，或介电抗反射涂层(dielectric antireflective coating，“DARC”)，例如富硅氧氮化硅。优选的是，可相对于随后沉积的间隔物材料来选择性地蚀刻包含第二硬掩模层110的材料。针对第二硬掩模层110使用DARC对形成具有接近于光刻技术的分辨极限的间距的图案可能尤其有利。明确地说，DARC可通过减少光反射来增强分辨率，从而增加光刻可界定图案的边缘的精确度。在可相对于随后沉积的间隔物材料来选择性地蚀刻第一硬掩模层108的实施例中，可省略第二硬掩模层110。在其它实施例中，用位于第一硬掩模层108与随后描述的上覆阵列光致抗蚀剂层之间的有机自旋抗反射涂层(“ARC”)来代替第二硬掩模层110。
阵列光致抗蚀剂层111(在本文中也被称作心轴层)形成于第二硬掩模层110上。阵列光致抗蚀剂层111优选包含感光材料，例如，与157nm、193nm、248nm或365nm波长系统、193nm波长浸渍系统(wavelength immersion system)、例如13.7nm波长系统的远紫外系统，或电子束微影系统相容的光致抗蚀剂材料。优选光致抗蚀剂材料的实例包括氟化氩敏感光致抗蚀剂(即，适合与氟化氩光源一起使用的光致抗蚀剂)和氟化氪敏感光致抗蚀剂(即，适合与氟化氪光源一起使用的光致抗蚀剂)。氟化氩光致抗蚀剂优选地与较短波长光刻系统(例如，193nm波长系统)一起使用。氟化氪光致抗蚀剂优选地与较长波长光刻系统(例如，248nm波长系统)一起使用。在经修改的实施例中，阵列光致抗蚀剂层111包含可通过纳米压印微影来图案化的光致抗蚀剂材料，例如通过使用模或机械力来对光致抗蚀剂材料进行图案化。
一般来说，基于本文中所揭示的用于各种图案形成和转印步骤的化学物和工艺条件而选择用于第一硬掩模层108、第二硬掩模层110和阵列光致抗蚀剂层111的材料。举例来说，在示范性实施例中，第一硬掩模层108、第二硬掩模层110和阵列光致抗蚀剂层111每一者可相对于彼此而被选择性地蚀刻。如本文中所使用，当某材料的蚀刻速率大于相邻材料的蚀刻速率时，认为所述材料“被选择性地蚀刻”(或“优先蚀刻”)。举例来说，在某些实施例中，“可选择性蚀刻的”材料的蚀刻速率比相邻材料的蚀刻速率大至少约2倍、大至少约10倍、大至少约20倍或大至少约40倍。在经修改的实施例中，如果使用其它合适材料、化学物和/或工艺条件，那么添加其它层。
可使用沉积工艺(例如，旋涂、溅镀、化学气相沉积(chemical vapor deposition，“CVD”)或原子层沉积)来形成第一硬掩模层108、第二硬掩模层110和阵列光致抗蚀剂层111。举例来说，低温CVD工艺(小于约550℃、小于约450℃或甚至小于约400℃)有利地减少无定形碳层的化学和/或物理分解，且因此对将材料沉积在现存无定形碳层(例如，第一硬掩模层108)上有用。在第6,573,030号美国专利(2003年6月3日发布)和第2005/0042879号美国专利申请公开案(2005年2月24日公开)中提供关于无定形碳层(包括掺杂无定形碳层)的形成的额外信息。此专利和专利申请公开案的整个揭示内容以引用的方式并入本文中。
第一硬掩模层108、第二硬掩模层110和阵列光致抗蚀剂层111的厚度也是取决于与本文中所揭示的蚀刻化学物和工艺条件的相容性来选择的。举例来说，当通过另一种材料的掩模来蚀刻某材料时，例如当通过选择性地蚀刻下伏层来将图案从上覆层转印到下伏层时，将来自这两个层的材料移除到某一程度。因此，上层优选地足够厚，使得其在图案转印期间不被完全磨损。在示范性实施例中，第二硬掩模层110的厚度优选地在约10nm与约40nm之间，且更优选地在约15nm与约30nm之间。
阵列光致抗蚀剂层111的厚度取决于用于对阵列光致抗蚀剂层111进行图案化的光的波长。在使用248nm光来执行光刻的示范性实施例中，阵列光致抗蚀剂层111的厚度优选地在约50nm与约300nm之间，且更优选地在约200nm与250nm之间。此高度可取决于用于对光致抗蚀剂层进行图案化的光的波长而改变。因为随后在阵列光致抗蚀剂层111中形成线，所以在某些实施例中，阵列光致抗蚀剂层111的高度受结构整体性和待形成的线的纵横比限制，因为较高间隔物线可能倒塌或以其它方式变形。
如图3A和图3B中所说明，在阵列光致抗蚀剂层111中界定包含由线124划界的沟槽122的图案。在一些实施例中，此图案可在衬底上的任何地方找到；在阵列区域中界定图案仅代表具有特定优势的特定实施例。沟槽122可(例如)用248nm或193nm的光通过光刻来形成，其中阵列光致抗蚀剂层111通过标线片(reticle)而暴露于辐射下，且接着被显影。在被显影后，其余的光可界定材料(其在所说明的实施例中为光致抗蚀剂)形成掩模特征，例如所说明的线124。在其它实施例中，还可使用无掩模微影或无掩模光刻来界定线124。
所得线124的间距等于线124的宽度与相邻沟槽122的宽度的总和。为了减小使用线124和沟槽122的此图案形成的特征的尺寸，所述间距可处于或接近用于对阵列光致抗蚀剂层111进行图案化的光刻技术的极限。举例来说，对于使用248nm光的光刻来说，线124的间距优选在约80nm与约150nm之间，且更优选地在约90nm与约120nm之间。因此，在示范性实施例中，所述间距是光刻技术的最小间距，且随后形成的间距倍增的间隔物图案有利地具有低于光刻技术的最小间距的间距。在替代实施例中，因为位置和特征大小的误差容限通常随着接近光刻技术的极限而增加，所以形成具有较大特征大小(例如，200nm)的线124，以减少线124的位置和大小的误差。
如图4A和图4B中所说明，优选通过对线124进行蚀刻来加宽沟槽122，以形成经修改的沟槽122′和经修改的线124′。优选使用各向同性蚀刻来对线124进行蚀刻，以使这些特征“缩小”。合适的蚀刻包括使用含氧等离子体的蚀刻，例如SO2/O2/N2/Ar等离子体、Cl2/O2/He等离子体或HBr/O2/N2等离子体。优选选择蚀刻的程度，使得经修改的线124′的宽度大体上等于随后形成的间距加倍特征之间的所需间隔。举例来说，在示范性实施例中，线124的宽度从在约80nm与约120nm之间减小到在约35nm与约70nm之间，且在另一实施例中，宽度减小到在约40nm与约50nm之间。有利地，宽度减小的蚀刻允许经修改的线124′比使用用于形成线124的光刻技术否则将可能形成的线窄。另外，所述蚀刻可向经修改的线124′提供光滑的边缘，从而改进经修改的线124′的均匀性。虽然可将经修改的线124′的临界尺寸蚀刻为低于光刻技术的分辨率极限，但此蚀刻并不更改经修改的沟槽122′和经修改的线124′的间距，因为这些特征中的相同点之间的距离保持相同。
如图5A和图5B中所说明，席状低温间隔物材料层126沉积在经修改的线124′上。在示范性实施例中，低温间隔物材料126包含使用原子层沉积(“ALD”)技术沉积的氧化物材料层。一般来说，光致抗蚀剂材料并不如无机或碳材料那样耐高温。因此，由低温氧化物材料形成间隔物有利地允许消除单独的心轴层沉积、图案化和转印，经图案化的阵列光致抗蚀剂层111提供相同的功能。在一个实施例中在小于约200℃下，在另一实施例中在小于约100℃下，在另一实施例中在小于约80℃下，且在另一实施例中在小于约75℃下，沉积低温间隔物材料。
在示范性实施例中，使用Si2Cl6、H2O和C5H5N前驱物来在ALD工艺中沉积低温间隔物材料126。在这些实施例中，将间隔物材料126沉积到某一厚度，在一个实施例中所述厚度在约20nm与约65nm之间，在另一实施例中所述厚度在约25nm与约60nm之间，且在另一实施例中所述厚度在约30nm与约55nm之间。在一个实施例中，间隔物材料的厚度在约30nm与约40nm之间，且在另一实施例中，间隔物材料的厚度在约43nm与约55nm之间。间隔物材料沉积速率在一个实施例中在约每循环1
Figure G2007800125255D0010134801QIETU
与约每循环4
Figure 2007800125255100002G2007800125255D0010134801QIETU
之间，且在另一实施例中为约每循环2
Figure 2007800125255100002G2007800125255D0010134801QIETU
。
如图6A到图6D中所说明，外围光致抗蚀剂层128视情况沉积在外围区域104中，同时使阵列区域102的至少一部分保持敞开。在图6B中所说明的优选实施例中，外围光致抗蚀剂层128大体上席状沉积在整个外围区域104上。在图6C中所说明的替代实施例中，外围光致抗蚀剂层128经图案化以界定外围特征。示范性外围特征包括着陆垫(landing pad)、晶体管、局部互连和其类似物。在图6D中所说明的另一替代实施例中，外围光致抗蚀剂层128沉积在低温间隔物材料126的回路末端和经修改的线124′的尖端124＂上，从而阻断经修改的线124′的尖端124＂。图6D中所说明的实施例对形成波形花纹结构尤其有利，因为此配置防止低温间隔物材料126上的回路末端在随后的蚀刻工艺期间可使用。
在又一个经修改的实施例中，省略图6A到图6D的第二遮蔽步骤，在较早阶段进行第二遮蔽步骤，或在稍后阶段进行第二遮蔽步骤。这使间隔物材料126在外围区域104中暴露。举例来说，在一种布置中，在与沉积阵列光致抗蚀剂层111相同的沉积步骤中沉积外围光致抗蚀剂层128。在此些实施例中，用于对阵列光致抗蚀剂层111进行图案化的掩模经配置以在外围区域104中留下光致抗蚀剂图案或席状层。此工艺导致光致抗蚀剂直接沉积在外围区域104中的第二硬掩模层110上，而无插入的间隔物材料126。
如图7A和图7B中所说明，低温间隔物材料126接着经受各向异性蚀刻，以从部分形成的集成电路100的水平表面移除间隔物材料。可使用(例如)含HBr/Cl2的等离子体来执行此蚀刻(也被称作间隔物蚀刻)。因此，间距倍增已完成以形成间隔物130。在所说明的实施例中，间隔物130的间距大约为最初通过光刻形成的光致抗蚀剂线124和沟槽122(见图3A和图3B)的间距的一半。在光致抗蚀剂线124具有约200nm的间距的情况下，可形成具有约100nm或更小(针对约50nm的宽度)的间距的间隔物130。因为间隔物130形成于经修改的线124′的侧壁上，所以间隔物130大体上遵循第一或阵列光致抗蚀剂层111中的经修改的线124′的图案的轮廓，且因此通常形成如图7B中所说明的闭合回路。然而，一般来说，间隔物130的配置取决于第二光致抗蚀剂层128的图案的不存在或存在(见上文对图6A到图6D和其变化方案的论述)。
如图8A和图8B中所说明，从部分形成的集成电路100选择性地蚀刻剩余的暴露光致抗蚀剂材料。所述其余的暴露光致抗蚀剂材料包括第一或阵列光致抗蚀剂层111，以及任何第二或外围光致抗蚀剂材料128。这导致由经修改的沟槽122′间隔的独立间隔物130的形成。现在通过任何剩余低温间隔物材料126来在外围区域104中界定外围特征。因此，将阵列光致抗蚀剂层111用作心轴，以形成间隔物130。使用有机剥离工艺来选择性地移除光致抗蚀剂材料。优选的蚀刻化学包括含氧等离子体蚀刻，例如使用SO2的蚀刻。在外围光致抗蚀剂层128直接沉积在第二硬掩模层110上的实施例中，仅从集成电路100的阵列区域102选择性地蚀刻光致抗蚀剂材料。或者，在此些实施例中，从阵列区域102和外围区域104两者蚀刻光致抗蚀剂材料，接着是外围区域104中光致抗蚀剂材料的随后沉积。在省略外围光致抗蚀剂层的实施例中，硬掩模层110在外围阵列区域104中暴露。
在形成独立间隔物130之后，可进行随后的处理步骤，例如干式显影步骤和原位蚀刻步骤。如图9A和图9B中所说明，可使用随后的处理步骤来将间隔物130和外围特征的图案转印到下伏第一硬掩模层108和/或第二硬掩模层110。具体来说，图9A和图9B说明界定在第一硬掩模层108和第二硬掩模层110中的间隔物130的图案。视情况从图9A和图9B中所说明的结构蚀刻第二硬掩模层110。接着可通过蚀刻下伏衬底106来将此图案转印到下伏衬底106中。还可通过界定在第一硬掩模层108和/或第二硬掩模层110中的图案来以其它方式处理所述结构(例如，通过掺杂、氧化、氮化或选择性地沉积)。如本文中所述，衬底106可包括先前沉积的层，例如用于波形花纹金属化的绝缘层或用于常规金属化的金属层。
本文所揭示的某些技术有利地允许形成间隔物的间距加倍的图案，而不使用额外的层来界定阵列特征，例如顶部碳层和无定形硅层。具体来说，如本文中所揭示，通过直接在阵列光致抗蚀剂层111上形成低温氧化物间隔物，可使用感光或光致抗蚀剂材料本身来界定随后的间距倍增技术中所使用的心轴。这有利地消除了对图案化额外遮蔽层以界定心轴的需要。此些技术有利地允许消除与此些额外遮蔽层相关联的工艺步骤，例如额外干式显影步骤和硬掩模蚀刻步骤。此外，此些技术还有利地允许使用与用于在阵列区域中形成间隔物的低温间隔物材料相同的低温间隔物材料来界定外围光致抗蚀剂层128。本文中所揭示的某些实施例还有利地允许硬掩模材料(与更易受影响的光致抗蚀剂材料相比)用于在外围区域104中阻断和界定特征，而不要求使用单独的硬掩模层。
本发明的范畴
虽然前述详细描述揭示本发明的若干实施例，但应理解，此揭示内容仅是说明性的且不限制本发明。应了解，所揭示的具体配置和操作可不同于上文所述的配置和操作，且本文所描述的方法可在除集成电路制造之外的环境中使用。

Claims (43)

1.一种制造半导体装置的方法，所述方法包含：
对光致抗蚀剂材料层进行图案化以在硬掩模层上形成多个心轴；
使用原子层沉积技术来将氧化物材料沉积在所述多个心轴上；
优先从暴露的水平表面各向异性地蚀刻所述氧化物材料；以及
相对于所述氧化物材料而选择性地蚀刻所述光致抗蚀剂材料，从而在所述硬掩模层上形成多个氧化物间隔物；以及
将所述间隔物图案转印到所述硬掩模层。
2.根据权利要求1所述的方法，其中使用选自由Si2Cl6、H2O和C5H5N组成的群组的前驱物来沉积所述氧化物材料。
3.根据权利要求1所述的方法，其中：
所述多个心轴形成于装置阵列区域中；以及
所述氧化物材料还沉积在装置外围区域上。
4.根据权利要求3所述的方法，其进一步包含在所述装置外围区域中所述氧化物材料上形成光致抗蚀剂材料图案。
5.根据权利要求4所述的方法，其中选择性地蚀刻所述光致抗蚀剂材料进一步包含从所述装置外围区域选择性地蚀刻光致抗蚀剂材料。
6.根据权利要求1所述的方法，其进一步包含各向同性地蚀刻所述多个心轴，以在沉积所述氧化物材料之前形成多个经修改的心轴。
7.根据权利要求6所述的方法，其中各向同性地蚀刻所述多个心轴包含使用选自由SO2/O2/N2/Ar等离子体、Cl2/O2/He等离子体和HBr/O2/N2等离子体组成的群组的含氧等离子体。
8.根据权利要求6所述的方法，其中所述经修改的心轴具有在35nm与70nm之间的宽度。
9.根据权利要求1所述的方法，其中对所述光致抗蚀剂层进行图案化包含使用纳米压印微影。
10.根据权利要求1所述的方法，其中各向异性地蚀刻所述氧化物材料包含使用含HBr/Ci2的等离子体。
11.根据权利要求1所述的方法，其中在小于100℃的温度下沉积所述氧化物材料。
12.根据权利要求1所述的方法，其中在小于80℃的温度下沉积所述氧化物材料。
13.根据权利要求1所述的方法，其中在位于碳层上的氧氮化硅层上对所述光致抗蚀剂材料层进行图案化。
14.根据权利要求1所述的方法，其中所述多个心轴具有在50nm与300nm之间的高度。
15.根据权利要求1所述的方法，其中所述光致抗蚀剂材料层包含选自由氟化氩光致抗蚀剂和氟化氪光致抗蚀剂组成的群组的材料。
16.一种形成存储器装置的方法，所述方法包含：
在硬掩模层上形成多个心轴，所述硬掩模层在衬底上，所述心轴由所述衬底的暴露部分隔开；
使用在小于100℃的温度下进行的原子层沉积技术来在所述心轴上且在所述衬底的所述暴露部分上沉积间隔物材料；以及
从(a)所述多个心轴的暴露水平表面和(b)所述衬底的所述暴露部分各向异性地蚀刻所述间隔物材料，从而使间隔物材料保留在所述多个心轴的垂直侧壁上。
17.根据权利要求16所述的方法，其进一步包含移除所述多个心轴，从而使间隔物图案位于所述衬底上。
18.根据权利要求17所述的方法，其中包含所述间隔物图案的所述间隔物具有50nm或更小的宽度
19.根据权利要求17所述的方法，其中在所述心轴上将所述间隔物材料沉积到厚度x，且其中包含所述间隔物图案包含所述间隔物图案的所述间隔物具有宽度x。
20.根据权利要求17所述的方法，其进一步包含将所述间隔物图案转印到无定形碳硬掩模中。
21.一种形成集成电路的方法，所述方法包含：
在所述集成电路的阵列区域中在硬掩模层上形成多个心轴，其中所述心轴包含感光材料；
使用原子层沉积技术来沉积间隔物材料，其中所述间隔物材料覆盖所述多个心轴，且在所述集成电路的外围区域上延伸；
在所述外围区域中在所述间隔物材料上形成感光材料图案；
随后优先从水平表面各向异性地蚀刻所述间隔物材料，从而使所述心轴暴露；
在各向异性地蚀刻所述间隔物材料之后移除所述暴露的心轴，从而在所述硬掩模层上留下间隔物图案；
将所述间隔物图案转印到所述硬掩模层；以及
从所述硬掩模层蚀刻所述间隔物图案。
22.根据权利要求21所述的方法，其中所述硬掩模层包含碳。
23.根据权利要求21所述的方法，其进一步包含：
在各向异性地蚀刻所述间隔物材料之后，从所述外围区域移除暴露的感光材料。
24.根据权利要求21所述的方法，其中所述硬掩模层包含碳，且进一步包含位于所述包含碳的硬掩模层上的第二硬掩模层，所述第二硬掩模层包含选自由硅、氮化硅和氧氮化硅组成的群组的材料。
25.根据权利要求21所述的方法，其中所述硬掩模层位于半导体衬底上。
26.根据权利要求21所述的方法，其中在小于100℃的温度下沉积所述间隔物材料。
27.根据权利要求21所述的方法，其进一步包含在沉积所述间隔物材料之前各向同性地蚀刻所述多个心轴。
28.一种集成电路制造方法，所述方法包含：
使用微影技术在硬掩模层上界定多个狭长心轴，其中所述心轴包含光致抗蚀剂材料；以及
在所述心轴周围形成间隔物图案，其中：
所述间隔物图案的间距小于所述微影技术的最小可分辨间距，
所述间隔物图案由氧化物材料形成，以及
在小于100℃的温度下使用原子层沉积技术来沉积所述间隔物图案。
29.根据权利要求28所述的方法，其中在小于80℃的温度下沉积所述间隔物图案。
30.根据权利要求28所述的方法，其中在小于30℃的温度下沉积所述间隔物图案。
31.根据权利要求28所述的方法，其进一步包含将所述间隔物图案转印到所述硬掩模层中。
32.根据权利要求31所述的方法，其中将所述间隔物图案转印到所述硬掩模层中进一步包含使衬底的下伏在所述硬掩模层下的一部分暴露。
33.根据权利要求28所述的方法，其中所述间隔物图案包含形成于所述心轴周围的间隔物回路图案。
34.根据权利要求28所述的方法，其中所述硬掩模层包含选自由硅、氮化硅和氧氮化硅组成的群组的材料。
35.根据权利要求28所述的方法，其中所述硬掩模层包含介电抗反射涂层。
36.根据权利要求28所述的方法，其中所述硬掩模层包含有机抗反射涂层。
37.根据权利要求28所述的方法，其中所述硬掩模层形成于半导体衬底上。
38.根据权利要求28所述的方法，其中所述硬掩模层形成于半导体衬底和无定形碳层上。
39.根据权利要求28所述的方法，其中所述心轴具有在50nm与300nm之间的高度。
40.根据权利要求28所述的方法，其中所述心轴具有在200nm与250nm之间的高度。
41.根据权利要求28所述的方法，其中所述心轴包含选自由无定形碳、氟化氩光致抗蚀剂和氟化氪光致抗蚀剂组成的群组的材料。
42.根据权利要求28所述的方法，其中所述间隔物图案具有在70nm与120nm之间的间距。
43.根据权利要求28所述的方法，其中所述图案具有在80nm与100nm之间的间距。
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US7732343B2 (en) 2010-06-08
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US8338959B2 (en) 2012-12-25
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US20110316114A1 (en) 2011-12-29
US20070238308A1 (en) 2007-10-11
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