WO2005034215A1 - Verfahren zum erzeugen einer hartmaske und hartmasken-anordnung - Google Patents
Verfahren zum erzeugen einer hartmaske und hartmasken-anordnung Download PDFInfo
- Publication number
- WO2005034215A1 WO2005034215A1 PCT/DE2004/002185 DE2004002185W WO2005034215A1 WO 2005034215 A1 WO2005034215 A1 WO 2005034215A1 DE 2004002185 W DE2004002185 W DE 2004002185W WO 2005034215 A1 WO2005034215 A1 WO 2005034215A1
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- WO
- WIPO (PCT)
- Prior art keywords
- hard mask
- layer
- mask layer
- photoresist layer
- structured
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Definitions
- the invention relates to a method for producing a hard mask and a hard mask arrangement.
- RET resolution enhancement techniques
- ALD processes atomic layer deposition processes
- [6] describes a method in which silicon oxide is applied to a photoresist structure by means of a plasma CVD method, the silicon layer partially is removed so that the upper region of the photoresist structure is exposed and then the photoresist structure is removed.
- a disadvantage of this procedure is, in particular, that the reliability of this method is very low, since the photoresist structure is destroyed or is temperature-treated due to the process conditions existing within the scope of the plasma CVD method, so that it is then only very difficult and with possible impairment of the remaining circuit structure formed can be removed.
- spacer structures from a layer formed by means of conformal disconnection, the structures extending over the substrate, to which the spacers adjoin, being removed after the spacer has been formed.
- [8] describes how to deposit two hard mask layers on top of one another and to apply a photoresist layer over the second hard mask layer.
- the second hard mask layer is trimmed and then the exposed areas of the first hard mask layer are etched using the remaining material of the second hard mask layer as a hard mask.
- the structured first hard mask layer is then trimmed again.
- the invention is based on the problem of using a sublithographic hard mask compared to the prior art to produce less expensive manufacturing process.
- the problem is solved by the method for producing a hard mask and by the hard mask arrangement with the
- a photoresist layer is applied to a substrate.
- the applied photoresist layer is then structured and a hard mask layer is applied to the structured photoresist layer by means of an atomic layer epitaxy process.
- a part of the hard mask layer is then removed while exposing a corresponding part of the structured photoresist layer.
- the part of the hard mask layer is removed, so that a corresponding part of the structured photoresist layer is exposed.
- the exposed structured photoresist layer is then removed.
- a hard mask arrangement has a substrate and a structured photoresist layer applied to the substrate.
- a hard mask layer is applied to the structured photoresist layer.
- the invention can clearly be seen in that a hard mask layer is applied directly to the structured photoresist layer using a low-temperature atomic layer epitaxy method.
- the horizontal regions of the hard mask layer are then etched by an anisotropic etching step.
- the hard mask layer is thus clearly "opened” so that the structured photoresist layer is at least partially exposed in order to be subsequently removed.
- What remains are the vertical portions of the hard mask layer which have not been removed and which correspond to those in the context of the atomic layer epitaxy method desired dimensioning have a very precisely adjustable layer thickness.
- the invention is characterized in particular by the fact that an inexpensive manufacturing process has been created in order to form sublithographic structures in a hard mask using conventional mask types. Furthermore, due to the use of an atomic layer epitaxy method to form the hard mask layer, the thickness of the hard mask layer can be controlled very precisely and the hard mask layer is applied to the structured photoresist layer in a perfectly conforming manner, so that the hard mask is formed precisely to an atomic layer, so that the hard mask itself is produced is critical in the critical dimension (CD).
- CD critical dimension
- the hard mask layer is applied directly to the structured photoresist layer, which can only be achieved in particular by using an atomic layer epitaxy method, since the atomic layer epitaxy method at a temperature of approximately 100 ° C. is carried out, that is at a temperature which is significantly below the baking temperature of a conventional photoresist material.
- photoresist material can be used as the photoresist material, also referred to as photoresist.
- the hard mask layer is formed from a dielectric, preferably from silicon dioxide (SiO 2) or aluminum oxide (A1 2 0 3 ).
- the hard mask layer can be formed from a suitable dielectric material, such as one of the following materials:
- hafnium oxide Hf ⁇ 2
- An oxide of a rare earth material or
- any suitable dielectric material can thus be used to form the hard mask layer, preferably any suitable dielectric material that can be applied by means of an atomic layer epitaxy method.
- Another significant advantage of the invention is that a sublithographic hard mask structure is formed using conventional lithography masks.
- the three masks of medium resolution enable the generation, that is to say the manufacture of the sublithographic hard mask structures according to the invention, for example as a basis for subsequently performing a gate etching.
- the process flow according to the invention thus replaces the complex and cost-intensive resolution-improving techniques and mask schemes, for example the use of alternating phase masks by a simple and inexpensive new process flow.
- the hard mask layer is formed from a dielectric material, preferably from silicon dioxide or aluminum oxide, alternatively from one of the materials described above.
- the part of the hard mask layer is preferably removed using an anisotropic etching process, particularly preferably using an anisotropic dry etching process, such as, for example, a reactive ion etching process (RIE).
- RIE reactive ion etching process
- the material of the photoresist layer covering the photoresist material that is to say the “cover part” of the hard mask layer, which is arranged above the photoresist layer, is removed, with which at least part of the photoresist layer, preferably the entire photoresist layer Layer that is exposed.
- the desired hard mask is formed in the form of web structures.
- a trimming mask medium resolution which for example ⁇ using a cutting or etching away (clipping) the remaining undesired portions of the hard mask layer
- the desired hard mask is formed in the form of web structures.
- the hollow cuboid structure as Sublithographic hard mask can optionally be used if this structure is sufficient to carry out the subsequent etching of the substrate desired by means of the hard mask.
- a large number of electronic circuits are integrated in the substrate.
- the hard mask is used in particular for the subsequent etching of a gate stack, which is arranged below the hard mask.
- a second hard mask layer made of a different material is applied to the structured photoresist layer, the second hard mask layer preferably again being applied by means of an atomic layer epitaxy method. This method makes it possible to simultaneously produce complex structures from hard mask material with different thicknesses, as will be described below.
- the first hard mask layer is particularly preferably formed from aluminum oxide and the second hard mask layer from silicon dioxide or vice versa.
- Other materials can also be used as hard mask layers if they can be conformally deposited at a low temperature and if they can then be selectively etched to one another.
- Hard mask layer can be used if the materials used for the hard mask layer and the second hard mask layer can be selectively etched to one another.
- first hard mask layer Due to the use of two different hard mask layer materials for the first hard mask layer and the second hard mask layer enables simple and inexpensive selective etching of the second hard mask layer without the first hard mask layer being attacked.
- a second photoresist layer made of conventional photoresist is preferably applied to the second hard mask layer and the second photoresist layer is structured, in accordance with this exemplary embodiment of the invention by means of a medium resolution mask.
- a structurally enlarged area is formed which serves, for example, as a landing pad, that is to say clearly as a connection area for contacting a connection of an electronic component in the substrate, for example as a landing pad for an electrical contact in an inverter circuit.
- Figure 1 shows a hard mask assembly according to a first embodiment of the ' invention at a first time of its manufacture
- FIG. 2 shows a hard mask arrangement according to the first exemplary embodiment of the invention at a second point in time when it was manufactured
- FIG. 3 shows a hard mask arrangement according to the first exemplary embodiment of the invention at a third point in time in its manufacture
- FIG. 4 shows a hard mask arrangement according to the first exemplary embodiment of the invention at a fourth point in time of its manufacture
- FIG. 5 shows a hard mask arrangement according to a second exemplary embodiment of the invention at a first point in time of its manufacture
- FIG. 6 shows a hard mask arrangement according to the second exemplary embodiment of the invention at a second point in time when it was manufactured.
- FIG. 7 shows a hard mask arrangement according to the second exemplary embodiment of the invention at a third point in time in its manufacture.
- FIG. 1 shows a hard mask arrangement 100 according to a first
- Embodiment of the invention at a first time of its manufacture.
- the hard mask arrangement 100 has a wafer substrate 101 made of silicon or another semiconductor material, in which a large number of electronic circuit elements or electronic circuits are integrated, for example electrical resistances, electrical capacitances, electrical inductances, (CMOS) field-effect transistors, bipolar transistors, etc. ,
- CMOS electrical inductances
- bipolar transistors bipolar transistors
- a photoresist layer 103 is applied to the upper surface 102 of the substrate 101 by means of a spin-on method.
- the structures to be formed in the photoresist layer 103 are defined using a medium resolution photoresist mask (not shown).
- a positive lithography method is used according to this exemplary embodiment
- the structuring of the photoresist layer 103 takes place, that is to say the exposed and thus developed regions of the photoresist layer 103 are Removed process, whereby openings 104 are formed in the photoresist layer 103.
- trenches 104 are formed in the photoresist layer 103, so that the upper surface 102 of the substrate 101 is partially exposed.
- the structured photoresist layer 103 is baked out by means of tempering at a temperature between, for example, 100 ° C. and 200 ° C., as is generally the case with the prior art.
- Atomic layer epitaxy layer is applied to the photoresist layer 103 and the exposed upper surface 102 of the substrate 101 by means of an atomic layer epitaxy method, so that the entire surface of the structured photoresist layer 103 and the exposed areas of the upper surface 102 of the substrate with the hard mask layer 201 made of aluminum oxide (AI 2 O 3 ) is completely covered.
- AI 2 O 3 aluminum oxide
- gate stack structures are formed (not shown) which, as will be explained in more detail below, are etched using the hard mask produced according to the invention.
- the thickness of the photoresist layer 103 can be selected to be relatively small, that is, in a range, for example, between 60 nm and 200 nm, since the photoresist layer 103 is not used as an etching mask.
- one of the methods described in [2], [3] or [4] is used for ALD deposition of aluminum oxide.
- the atomic layer epitaxy process is carried out at a process temperature of approximately 50 ° C - 100 ° C.
- the thickness of the hard mask layer 201 depends on the desired final lateral dimension, that is to say the lateral structure size of the hard mask to be produced, and can be adjusted to an atomic position. According to this
- the hard mask layer 201 is between 10 nm and 50 nm thick.
- a part of the hard mask layer 201 is removed using an anisotropic dry etching method, according to this exemplary embodiment by means of reactive ion etching.
- the areas above the substrate 101 that are no longer covered by the structured photoresist layer 103 are again removed, so that the exposed areas of the upper surface 102 of the substrate 101 already shown in FIG. 1 are exposed again.
- the photoresist is subsequently stripped, that is to say removed, for example by ashing the photoresist material of the structured photoresist layer 103.
- the height of the cavity cuboids 301 is approximately 50 nm.
- the width of the generated edge structures of the hollow cuboids 301 is equal to the layer thickness of the hard mask layer 201, according to this exemplary embodiment the hard mask layer 201 is therefore between 10 nm and 50 nm thick.
- the area of the remaining first hard mask layer that is to say the hollow cuboid 301, is removed in a subsequent step, so that webs 401 with a height of 50 nm and a width of 10 nm are produced 4 in the hard mask arrangement 400 at a fourth point in time of its manufacture.
- the bars 401 produced form the desired hard mask for etching the gate structures located below the bars 401.
- FIG. 5 shows a hard mask arrangement 500 according to a second exemplary embodiment of the invention at a first point in time of its manufacture.
- a structure is assumed which has a first sublithographic hard mask, for example generated as in the method of the first exemplary embodiment.
- the hard mask shown in FIG. Arrangement 400 is used as the basis for the method for producing the hard mask arrangement shown below in accordance with the second exemplary embodiment of the invention.
- the hard mask with two different thicknesses can be used, for example, to produce a thin hard mask, that is to say a thin sublithographic hard mask for ultrashort gate structures, plus a second mask region for etching longer gate structures or for producing so-called landing pads, that is to say larger connection regions for Contacting the electronic components in the substrate 101, for example for contacting an inverter connection of an inverter circuit, which is integrated in the substrate 101.
- a second dielectric layer conforms to the entire surface of the hard mask 401 and the exposed areas of the upper surface 102 of the substrate 101 deposited.
- the second hard mask layer 501 is formed according to this exemplary embodiment of the invention from silicon dioxide (SiO 2 ).
- the second hard mask layer 501 has a thickness of approximately 20 nm.
- a second photoresist layer 601 (compare hard mask arrangement 600 at a second point in time of its manufacture in FIG. 6) is applied to the second dielectric layer, that is to say to the second hard mask layer 501.
- the area is defined using a mask of medium resolution, or the areas are defined which require or require a thicker dielectric layer, that is to say a layer which results from the first hard mask layer and the second hard mask layer developed with it.
- the exposed areas of the second photoresist layer 601 are removed, so that a structured second photoresist layer is formed.
- Embodiment of the invention at a third point in time of the method for its production in FIG. 7).
- the exposed areas of the second hard mask layer 501 are removed by means of the selective wet etching method used, so that a structured second hard mask layer 701 is formed.
- the structured second photoresist layer 601 is then removed by ashing, and thus the hard mask arrangement 700 is formed, which on the one hand has the thin webs 401 of the hard mask with a width of 10 nm and widened regions formed by the second hard mask 701.
- a reactive ion etching method is preferably used for this.
- the desired structures are now etched, for example a landing pad below the remaining second hard mask layer 701 or the gate stacks below the webs 401 of the first gate length.
- the structured second hard mask layer 701 it is also possible to generate gate stacks with a second gate length that is larger than the first gate length in a very simple manner.
- the first hard mask layer has a thickness of approximately 10 nm and the second hard mask layer has a thickness of approximately 20 nm.
- the generated hard mask arrangement 700 using the webs 401 and the structured second hard mask layer 701
- structures of 10 nm gate length and structures of 50 nm gate length can be produced.
- the method according to the second exemplary embodiment is started with a hard mask arrangement shown in FIG.
- the second hard mask layer is applied directly to the not yet structured first hard mask layer and the subsequent structuring steps are applied to both hard mask layers in a corresponding manner, which is described above in the context of the two exemplary embodiments, so that a hard mask with two different thicknesses is also formed in this case.
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
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- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Description
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04786897A EP1668680A1 (de) | 2003-09-30 | 2004-09-30 | Verfahren zum erzeugen einer hartmaske und hartmasken-anordnung |
US11/393,017 US20060234138A1 (en) | 2003-09-30 | 2006-03-30 | Hard mask arrangement |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10345455A DE10345455A1 (de) | 2003-09-30 | 2003-09-30 | Verfahren zum Erzeugen einer Hartmaske und Hartmasken-Anordnung |
DE10345455.1 | 2003-09-30 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/393,017 Continuation US20060234138A1 (en) | 2003-09-30 | 2006-03-30 | Hard mask arrangement |
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Publication Number | Publication Date |
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WO2005034215A1 true WO2005034215A1 (de) | 2005-04-14 |
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ID=34399090
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/DE2004/002185 WO2005034215A1 (de) | 2003-09-30 | 2004-09-30 | Verfahren zum erzeugen einer hartmaske und hartmasken-anordnung |
Country Status (5)
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US (1) | US20060234138A1 (de) |
EP (1) | EP1668680A1 (de) |
CN (1) | CN100472714C (de) |
DE (1) | DE10345455A1 (de) |
WO (1) | WO2005034215A1 (de) |
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Also Published As
Publication number | Publication date |
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DE10345455A1 (de) | 2005-05-04 |
CN100472714C (zh) | 2009-03-25 |
US20060234138A1 (en) | 2006-10-19 |
CN1860586A (zh) | 2006-11-08 |
EP1668680A1 (de) | 2006-06-14 |
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