WO2010131568A1 - 炭化珪素基板、半導体装置および炭化珪素基板の製造方法 - Google Patents
炭化珪素基板、半導体装置および炭化珪素基板の製造方法 Download PDFInfo
- Publication number
- WO2010131568A1 WO2010131568A1 PCT/JP2010/057439 JP2010057439W WO2010131568A1 WO 2010131568 A1 WO2010131568 A1 WO 2010131568A1 JP 2010057439 W JP2010057439 W JP 2010057439W WO 2010131568 A1 WO2010131568 A1 WO 2010131568A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- silicon carbide
- sic
- manufacturing
- carbide substrate
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 720
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 621
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 594
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 160
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000000034 method Methods 0.000 title claims description 61
- 239000013078 crystal Substances 0.000 claims abstract description 80
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 238000010438 heat treatment Methods 0.000 claims description 30
- 238000005498 polishing Methods 0.000 claims description 12
- 238000000859 sublimation Methods 0.000 claims description 10
- 230000008022 sublimation Effects 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 224
- 230000007547 defect Effects 0.000 description 23
- 239000012535 impurity Substances 0.000 description 23
- 230000015556 catabolic process Effects 0.000 description 18
- 230000008569 process Effects 0.000 description 16
- 238000002474 experimental method Methods 0.000 description 12
- 239000011261 inert gas Substances 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000007789 gas Substances 0.000 description 9
- 238000005304 joining Methods 0.000 description 9
- 238000000137 annealing Methods 0.000 description 7
- 238000001887 electron backscatter diffraction Methods 0.000 description 7
- 230000003746 surface roughness Effects 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000009467 reduction Effects 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000002003 electron diffraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/06—Joining of crystals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Definitions
- the present invention relates to a silicon carbide substrate, a semiconductor device, and a method for manufacturing a silicon carbide substrate, and more specifically, a silicon carbide substrate capable of reducing the manufacturing cost of a semiconductor device using the silicon carbide substrate, a method for manufacturing the silicon carbide substrate, and a manufacturing method therefor.
- the present invention relates to a semiconductor device with reduced cost.
- silicon carbide has been increasingly adopted as a material constituting semiconductor devices in order to enable higher breakdown voltage, lower loss, and use in high-temperature environments.
- Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device.
- a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.
- silicon carbide does not have a liquid phase at normal pressure.
- the crystal growth temperature is as high as 2000 ° C. or higher, and it is difficult to control the growth conditions and stabilize the growth conditions. Therefore, it is difficult to increase the diameter of silicon carbide single crystal while maintaining high quality, and it is not easy to obtain a high-quality silicon carbide substrate having a large diameter.
- due to the difficulty in manufacturing a large-diameter silicon carbide substrate not only the manufacturing cost of the silicon carbide substrate increases, but also when manufacturing a semiconductor device using the silicon carbide substrate, one batch There is a problem that the number of per-manufactured products decreases and the manufacturing cost of semiconductor devices increases. Further, it is considered that the manufacturing cost of the semiconductor device can be reduced by effectively using the silicon carbide single crystal having a high manufacturing cost as the substrate.
- an object of the present invention is to provide a silicon carbide substrate capable of realizing a reduction in manufacturing cost of a semiconductor device using a silicon carbide substrate, a manufacturing method thereof, and a semiconductor device with reduced manufacturing cost.
- a silicon carbide substrate according to the present invention includes a base substrate made of silicon carbide and a SiC layer made of single crystal silicon carbide different from the base substrate and arranged in contact with the base substrate.
- a SiC layer made of single crystal silicon carbide different from the base substrate is disposed on the base substrate.
- a base substrate made of low-quality silicon carbide crystal having a high defect density is processed into the predetermined shape and size, and a high-quality but desired shape or the like is not realized on the base substrate.
- a silicon single crystal can be arranged as a SiC layer. Since such a silicon carbide substrate is unified in a predetermined shape and size, the manufacturing of the semiconductor device can be made efficient. Moreover, since it is possible to manufacture a semiconductor device using such a high quality SiC layer of a silicon carbide substrate, a silicon carbide single crystal can be used effectively.
- the state in which the SiC layer is made of single crystal silicon carbide different from the base substrate includes the case where the base substrate is made of silicon carbide other than single crystal such as polycrystalline or amorphous silicon carbide, This includes the case where the substrate is made of single crystal silicon carbide and made of a crystal different from the SiC layer.
- the state in which the base substrate and the SiC layer are made of different crystals means that there is a boundary between the base substrate and the SiC layer, for example, the defect density is different on one side and the other side of the boundary. Means. At this time, the defect density may be discontinuous at the boundary.
- the base substrate is made of single crystal silicon carbide.
- the micropipe density of the SiC layer is smaller than the micropipe density of the base substrate.
- the base substrate is made of single crystal silicon carbide.
- the dislocation density of the SiC layer is preferably smaller than the dislocation density of the base substrate. More specifically, in the silicon carbide substrate, preferably, the base substrate is made of single crystal silicon carbide.
- the threading screw dislocation density of the SiC layer is smaller than the threading screw dislocation density of the base substrate.
- the base substrate is made of single crystal silicon carbide.
- the threading edge dislocation density of the SiC layer is smaller than the threading edge dislocation density of the base substrate.
- the base substrate is made of single crystal silicon carbide.
- the basal plane dislocation density of the SiC layer is smaller than the basal plane dislocation density of the base substrate.
- the base substrate is made of single crystal silicon carbide.
- the mixed dislocation density of the SiC layer is smaller than the mixed dislocation density of the base substrate.
- the base substrate is made of single crystal silicon carbide.
- the stacking fault density of the SiC layer is smaller than the stacking fault density of the base substrate.
- the base substrate is made of single crystal silicon carbide.
- the point defect density of the SiC layer is smaller than the point defect density of the base substrate.
- the defect density such as micropipe density, dislocation density (threading screw dislocation density, threading edge dislocation density, basal plane dislocation density, mixed dislocation density, stacking fault density, point defect density) is higher than that of the base substrate.
- the base substrate is made of single crystal silicon carbide.
- the half width of the X-ray rocking curve of the SiC layer is smaller than the half width of the X-ray rocking curve of the base substrate.
- a silicon carbide substrate capable of manufacturing a high-quality semiconductor device can be obtained by disposing an SiC layer having a smaller half-value width of the X-ray rocking curve than that of the base substrate, that is, high crystallinity.
- the base substrate may include a single crystal layer made of single crystal silicon carbide so as to include a main surface on the side facing the SiC layer.
- the micropipe density of the SiC layer is preferably smaller than the micropipe density of the single crystal layer.
- the dislocation density of the SiC layer is smaller than the dislocation density of the single crystal layer. More specifically, in the silicon carbide substrate, preferably, the threading screw dislocation density of the SiC layer is smaller than the threading screw dislocation density of the single crystal layer.
- the threading edge dislocation density of the SiC layer is smaller than the threading edge dislocation density of the single crystal layer.
- the basal plane dislocation density of the SiC layer is smaller than the basal plane dislocation density of the single crystal layer.
- the mixed dislocation density of the SiC layer is smaller than the mixed dislocation density of the single crystal layer.
- the stacking fault density of the SiC layer is smaller than the stacking fault density of the single crystal layer.
- the point defect density of the SiC layer is smaller than the point defect density of the single crystal layer.
- the defect density such as micropipe density, dislocation density (threading screw dislocation density, threading edge dislocation density, basal plane dislocation density, mixed dislocation density, stacking fault density, point defect density), etc.
- the half width of the X-ray rocking curve of the SiC layer is smaller than the half width of the X-ray rocking curve of the single crystal layer.
- a silicon carbide substrate capable of manufacturing a high-quality semiconductor device is obtained by disposing a SiC layer having a smaller half width of the X-ray rocking curve than that of the single crystal layer of the base substrate, that is, high crystallinity. be able to.
- the impurity density of the base substrate can be 5 ⁇ 10 18 cm ⁇ 3 or more.
- the carrier density of the base substrate increases, for example, an electrode is formed on the main surface of the base substrate opposite to the side on which the SiC layer is formed, and the current path crosses the base substrate in the thickness direction.
- a silicon carbide substrate suitable for manufacturing the vertical semiconductor device can be obtained.
- the resistivity of the base substrate can be 1 ⁇ 10 5 ⁇ ⁇ cm or more.
- the resistance value of the base substrate is increased, and for example, a silicon carbide substrate suitable for manufacturing a semiconductor device in which a current flows in a direction along the main surface of the base substrate and a high frequency is required is obtained. be able to.
- the silicon carbide substrate a plurality of the SiC layers may be laminated. Thereby, the silicon carbide substrate provided with the SiC layer according to the structure of the target semiconductor device can be obtained.
- a plurality of SiC layers are arranged side by side in a plan view. If it demonstrates from another viewpoint, it is preferable that the SiC layer is arranged in multiple numbers along the main surface of a base substrate. As described above, it is difficult to increase the diameter of a high-quality silicon carbide single crystal. On the other hand, it is possible to handle a large-diameter substrate having a high-quality SiC layer by arranging a plurality of SiC layers collected from a high-quality silicon carbide single crystal in a plane on a large-diameter base substrate. A silicon carbide substrate can be obtained. By using this silicon carbide substrate, the manufacturing process of the semiconductor device can be made efficient.
- adjacent SiC layers among the plurality of SiC layers are arranged in contact with each other. More specifically, for example, the plurality of SiC layers are preferably laid out in a matrix when viewed in a plan view. Moreover, it is preferable that the end surface of an adjacent SiC layer is substantially perpendicular
- the angle formed by the end surface and the main surface is not less than 85 ° and not more than 95 °, it can be determined that the end surface and the main surface are substantially perpendicular.
- the main surface of the SiC layer opposite to the base substrate may have an off angle of 50 ° or more and 65 ° or less with respect to the plane orientation ⁇ 0001 ⁇ .
- a hexagonal silicon carbide single crystal can be produced in a ⁇ 0001> direction to efficiently produce a high-quality single crystal. And from the silicon carbide single crystal grown in the ⁇ 0001> direction, a silicon carbide substrate having a ⁇ 0001 ⁇ plane as a main surface can be efficiently collected.
- a high-performance semiconductor device is manufactured by using a silicon carbide substrate having a main surface with an off angle of 50 ° or more and 65 ° or less with respect to the plane orientation ⁇ 0001 ⁇ , for example, a main plane with a plane orientation ⁇ 03-38 ⁇ . There are cases where it is possible.
- the main surface of the SiC layer is not less than 50 ° and not more than 65 ° with respect to the plane orientation ⁇ 0001 ⁇ . Even when it has an off-angle, the silicon carbide single crystal can be used effectively. Further, by arranging a plurality of the SiC layers side by side in a plan view, a main surface having an off angle of 50 ° or more and 65 ° or less with respect to the surface orientation ⁇ 0001 ⁇ , which is difficult to increase in diameter, for example, the surface orientation ⁇ A large-diameter silicon carbide substrate having a main surface of 03-38 ⁇ can be easily obtained.
- an angle formed between the off orientation of the main surface and the ⁇ 1-100> direction may be 5 ° or less.
- the ⁇ 1-100> direction is a typical off orientation in a silicon carbide substrate. Then, by setting the variation in the off orientation due to the variation in the slice processing in the manufacturing process of the substrate to 5 ° or less, the formation of the epitaxial growth layer on the silicon carbide substrate can be facilitated.
- the off angle of the main surface with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction can be set to ⁇ 3 ° to 5 °.
- the channel mobility when a MOSFET or the like is manufactured using a silicon carbide substrate can be further improved.
- the off angle with respect to the plane orientation ⁇ 03-38 ⁇ is set to ⁇ 3 ° or more and + 5 ° or less.
- the channel mobility is particularly high within this range. Is based on the obtained.
- the “off angle with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction” is an orthogonal projection of the normal of the principal surface to the plane extending in the ⁇ 1-100> direction and the ⁇ 0001> direction, This is an angle formed with the normal of the ⁇ 03-38 ⁇ plane, and its sign is positive when the orthographic projection approaches parallel to the ⁇ 1-100> direction, and the orthographic projection is in the ⁇ 0001> direction. The case of approaching parallel to is negative.
- the surface orientation of the main surface is more preferably ⁇ 03-38 ⁇ , and the surface orientation of the main surface is more preferably ⁇ 03-38 ⁇ .
- the surface orientation of the main surface is substantially ⁇ 03-38 ⁇ , taking into account the processing accuracy of the substrate, etc., the substrate is within an off-angle range where the surface orientation can be substantially regarded as ⁇ 03-38 ⁇ .
- the off angle range is, for example, a range of ⁇ 2 ° with respect to ⁇ 03-38 ⁇ .
- an angle formed between the off orientation of the main surface and the ⁇ 11-20> direction may be 5 ° or less.
- the ⁇ 11-20> direction is a typical off orientation in the silicon carbide substrate, similarly to the ⁇ 1-100> direction. Then, by setting the variation in off orientation due to the variation in slicing in the manufacturing process of the substrate to ⁇ 5 °, formation of an epitaxially grown layer on the silicon carbide substrate can be facilitated.
- the main surface of the SiC layer opposite to the base substrate is polished.
- a high quality epitaxial growth layer can be formed on the main surface of the SiC layer opposite to the base substrate.
- a semiconductor device including the high-quality epitaxially grown layer as an active layer can be manufactured. That is, by adopting such a structure, a silicon carbide substrate capable of manufacturing a high-quality semiconductor device including an epitaxial layer formed on a SiC layer can be obtained.
- a semiconductor device includes a silicon carbide substrate, an epitaxial growth layer formed on the silicon carbide substrate, and an electrode formed on the epitaxial growth layer.
- the silicon carbide substrate is the silicon carbide substrate of the present invention. According to the semiconductor device of the present invention, it is possible to provide a semiconductor device with reduced manufacturing costs by including the silicon carbide substrate of the present invention.
- a method for manufacturing a silicon carbide substrate according to the present invention includes a step of preparing a base substrate made of silicon carbide and an SiC substrate made of single crystal silicon carbide, and placing the SiC substrate in contact with the main surface of the base substrate. Then, a process for producing a multilayer substrate and a process for bonding the base substrate and the SiC substrate by heating the multilayer substrate are provided. Thereby, the silicon carbide substrate of the present invention can be easily manufactured.
- a gap formed between the base substrate and the SiC substrate is 100 ⁇ m or less.
- the laminated substrate is heated to a temperature range equal to or higher than the sublimation temperature of silicon carbide.
- the “temperature range above the sublimation temperature of silicon carbide” is not necessarily a temperature range above the sublimation point temperature of silicon carbide, but a temperature range where the sublimation phenomenon of silicon carbide occurs, for example, 1800 ° C. or more. Any temperature range is acceptable.
- the method for manufacturing the silicon carbide substrate further includes a step of planarizing a main surface of the base substrate and the SiC substrate to be in contact with each other in the step of manufacturing the multilayer substrate before the step of manufacturing the multilayer substrate. Yes.
- the base substrate and the SiC substrate can be bonded more reliably.
- the step of manufacturing the multilayer substrate is performed by polishing the main surfaces of the base substrate and the SiC substrate to be contacted with each other in the step of manufacturing the multilayer substrate before the step of manufacturing the multilayer substrate. It may be implemented without doing. Thereby, the manufacturing cost of a silicon carbide substrate can be reduced.
- the laminated substrate is heated to a temperature range higher than the sublimation temperature of silicon carbide, so that the base substrate and the SiC substrate can be omitted even if the polishing of the base substrate and the SiC substrate is omitted. Can be easily joined.
- the main surfaces of the base substrate and the SiC substrate that are to be in contact with each other in the step of manufacturing the laminated substrate may not be polished as described above.
- the step of fabricating the laminated substrate is performed after the step of removing the damaged layer by, for example, etching. It is preferable.
- a plurality of SiC substrates may be laminated on the base substrate in the step of producing the laminated substrate. Thereby, the silicon carbide substrate by which the some SiC layer was laminated
- a plurality of SiC substrates may be placed side by side in a plan view. If it demonstrates from another viewpoint, a plurality of SiC substrates may be arranged side by side along the main surface of the base substrate. Thereby, a silicon carbide substrate that can be handled as a large-diameter substrate having a high-quality SiC layer can be manufactured.
- a step of bonding the multilayer substrate and the other SiC substrate may be further provided by heating the multilayer substrate.
- a plurality of the other SiC substrates may be placed side by side in a plan view. If it demonstrates from another viewpoint, the said other SiC substrate may be mounted side by side along the main surface of a base substrate. Thereby, a silicon carbide substrate that can be handled as a large-diameter substrate having a plurality of high-quality SiC layers can be manufactured.
- the step of manufacturing the second stacked substrate includes a SiC substrate to be contacted with each other in the step of manufacturing the second stacked substrate, and the step of manufacturing the second stacked substrate.
- the main surface of the SiC substrate opposite to the base substrate has an off angle of 50 ° to 65 ° with respect to the ⁇ 0001 ⁇ plane. Also good. Thereby, a silicon carbide substrate in which the main surface of the SiC layer opposite to the base substrate has an off angle of 50 ° or more and 65 ° or less with respect to the ⁇ 0001 ⁇ plane can be easily manufactured.
- the angle formed between the off orientation of the main surface opposite to the base substrate of the SiC substrate and the ⁇ 1-100> direction is 5 ° or less. It may be. Thereby, formation of the epitaxial growth layer on the produced silicon carbide substrate can be facilitated.
- the off angle of the main surface opposite to the base substrate of the SiC substrate with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction is ⁇ It may be 3 ° or more and 5 ° or less.
- the angle formed between the off orientation of the main surface of the SiC substrate opposite to the base substrate and the ⁇ 11-20> direction is 5 ° or less. It may be. Thereby, formation of the epitaxial growth layer on the produced silicon carbide substrate can be facilitated.
- the laminated substrate in the step of bonding the base substrate and the SiC substrate, the laminated substrate may be heated in an atmosphere obtained by reducing the atmospheric pressure. Thereby, the manufacturing cost of a silicon carbide substrate can be reduced.
- the laminated substrate in the step of bonding the base substrate and the SiC substrate, the laminated substrate may be heated under a pressure higher than 10 ⁇ 1 Pa and lower than 10 4 Pa.
- the method for manufacturing the silicon carbide substrate may further include a step of polishing the main surface of the SiC substrate corresponding to the main surface of the SiC substrate on the side opposite to the base substrate of the laminated substrate.
- a high quality epitaxial growth layer can be formed on the main surface of the SiC layer (SiC substrate) opposite to the base substrate.
- a semiconductor device including the high-quality epitaxially grown layer as an active layer can be manufactured. That is, by adopting such a process, a silicon carbide substrate capable of manufacturing a high-quality semiconductor device including an epitaxial layer formed on the SiC layer can be obtained.
- the main surface of the SiC substrate may be polished after the base substrate and the SiC substrate are joined, or the main surface of the SiC substrate that should be the main surface on the opposite side of the base substrate in the laminated substrate. May be performed before the step of manufacturing the laminated substrate.
- a silicon carbide substrate capable of reducing the manufacturing cost of the semiconductor device using the silicon carbide substrate and the method for manufacturing the same are provided. be able to. Further, according to the semiconductor device of the present invention, a semiconductor device with reduced manufacturing costs can be provided.
- silicon carbide substrate 1 in the present embodiment includes a base substrate 10 made of silicon carbide and single-crystal silicon carbide different from base substrate 10, and is arranged in contact with base substrate 10.
- SiC layer 20 is provided.
- silicon carbide substrate 1 has a high defect quality, for example, by processing base substrate 10 made of a low-quality silicon carbide crystal into a predetermined shape and size.
- a silicon carbide single crystal in which a desired shape or the like is not realized can be disposed as the SiC layer 20. Since this silicon carbide substrate 1 is unified in a predetermined shape and size, it is possible to increase the efficiency of manufacturing the semiconductor device. Moreover, since it is possible to manufacture a semiconductor device using the high quality SiC layer 20 of the silicon carbide substrate 1, a silicon carbide single crystal can be used effectively.
- silicon carbide substrate 1 in the present embodiment is a silicon carbide substrate capable of reducing the manufacturing cost of the semiconductor device.
- base substrate 10 is preferably made of single crystal silicon carbide.
- the difference in various physical property values from SiC layer 20 made of single crystal silicon carbide is reduced, and the silicon carbide substrate is stable in various environments, particularly in the manufacturing process of the semiconductor device.
- the micropipe density of SiC layer 20 is smaller than the micropipe density of base substrate 10.
- the threading screw dislocation density of SiC layer 20 is smaller than the threading screw dislocation density of base substrate 10.
- the threading edge dislocation density of SiC layer 20 is smaller than the threading edge dislocation density of base substrate 10.
- the basal plane dislocation density of SiC layer 20 is preferably smaller than the basal plane dislocation density of base substrate 10.
- the mixed dislocation density of SiC layer 20 is smaller than the mixed dislocation density of base substrate 10.
- the stacking fault density of SiC layer 20 is preferably smaller than the stacking fault density of base substrate 10.
- the point defect density of SiC layer 20 is preferably smaller than the point defect density of base substrate 10.
- silicon carbide substrate 1 capable of manufacturing a high-quality semiconductor device can be obtained by arranging SiC layer 20 having a defect density reduced as compared with base substrate 10.
- the half width of the X-ray rocking curve of SiC layer 20 is preferably smaller than the half width of the X-ray rocking curve of base substrate 10.
- silicon carbide substrate 1 capable of manufacturing a high-quality semiconductor device is obtained by disposing SiC layer 20 having a smaller half-value width of the X-ray rocking curve than base substrate 10, that is, high crystallinity. Can do.
- base substrate 10 includes a single crystal layer 10 ⁇ / b> B made of single crystal silicon carbide so as to include main surface 10 ⁇ / b> A on the side facing SiC layer 20. Also good.
- a semiconductor device is manufactured using silicon carbide substrate 1
- a thick and easy-to-handle state is maintained in the initial stage of the manufacturing process, and a base other than single crystal layer 10 ⁇ / b> B is maintained during the manufacturing process.
- By removing the substrate region 10C only the single crystal layer 10B of the base substrate 10 can be left inside the semiconductor device. Thereby, it is possible to manufacture a high-quality semiconductor device while facilitating handling of silicon carbide substrate 1 in the manufacturing process.
- the micropipe density of SiC layer 20 is smaller than the micropipe density of single crystal layer 10B.
- the threading screw dislocation density of SiC layer 20 is preferably smaller than the threading screw dislocation density of single crystal layer 10B.
- the threading edge dislocation density of SiC layer 20 is smaller than the threading edge dislocation density of single crystal layer 10B.
- the basal plane dislocation density of SiC layer 20 is smaller than the basal plane dislocation density of single crystal layer 10B.
- the mixed dislocation density of SiC layer 20 is preferably smaller than the mixed dislocation density of single crystal layer 10B.
- the stacking fault density of SiC layer 20 is preferably smaller than the stacking fault density of single crystal layer 10B.
- the point defect density of SiC layer 20 is smaller than the point defect density of single crystal layer 10B.
- the half width of the X-ray rocking curve of SiC layer 20 is smaller than the half width of the X-ray rocking curve of single crystal layer 10B.
- base substrate 10 can have an impurity density of 5 ⁇ 10 18 cm ⁇ 3 or more. Thereby, the carrier density of base substrate 10 increases, and silicon carbide substrate 1 suitable for manufacturing a vertical semiconductor device can be obtained. Furthermore, the impurity concentration of the base substrate 10 can be higher than 2 ⁇ 10 19 cm ⁇ 3 . The impurity concentration of the SiC layer 20 can be larger than 5 ⁇ 10 18 cm ⁇ 3 and smaller than 2 ⁇ 10 19 cm ⁇ 3 . Thereby, the resistivity in the thickness direction can be reduced while suppressing the occurrence of stacking faults due to heat treatment.
- the resistivity of base substrate 10 can be set to 1 ⁇ 10 5 ⁇ ⁇ cm or more. Thereby, the resistance value of base substrate 10 is increased, and silicon carbide substrate 1 suitable for the manufacture of a horizontal semiconductor device requiring high frequency can be obtained.
- main surface 20A of SiC layer 20 on the side opposite to base substrate 10 has an off angle of 50 ° or more and 65 ° or less with respect to the plane orientation ⁇ 0001 ⁇ . May be. Thereby, silicon carbide substrate 1 capable of manufacturing a high-performance semiconductor device can be obtained while effectively utilizing a silicon carbide single crystal.
- the angle formed between the off orientation of main surface 20A and the ⁇ 1-100> direction may be 5 ° or less.
- the ⁇ 1-100> direction is a typical off orientation in a silicon carbide substrate. Then, by setting the variation in the off orientation due to the variation in the slice processing in the manufacturing process of the silicon carbide substrate 1 to 5 ° or less, the formation of the epitaxial growth layer on the silicon carbide substrate 1 (on the main surface 20A), etc. Can be easily.
- the off angle of main surface 20A with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction can be set to ⁇ 3 ° to 5 °. Thereby, the channel mobility when a MOSFET or the like is manufactured using silicon carbide substrate 1 can be further improved.
- the angle formed by the off orientation of main surface 20A and the ⁇ 11-20> direction may be 5 ° or less.
- the ⁇ 11-20> direction is a typical off orientation in the silicon carbide substrate, similarly to the ⁇ 1-100> direction. Then, by setting the variation in the off orientation due to the variation in slicing in the manufacturing process of silicon carbide substrate 1 to ⁇ 5 °, formation of an epitaxial growth layer on SiC layer 20 can be facilitated.
- silicon carbide substrate 1 in the present embodiment it is preferable that main surface 20A of SiC layer 20 on the side opposite to base substrate 10 is polished. This makes it possible to form a high quality epitaxial growth layer on the main surface 20A. As a result, a semiconductor device including the high-quality epitaxially grown layer as an active layer can be manufactured. That is, by adopting such a structure, silicon carbide substrate 1 capable of manufacturing a high-quality semiconductor device including an epitaxial layer formed on SiC layer 20 can be obtained.
- a substrate preparation step is first performed as a step (S10).
- base substrate 10 made of silicon carbide and SiC substrate 20 made of single crystal silicon carbide are prepared.
- a substrate flattening step is performed as a step (S20).
- the main surface (bonding surface) of base substrate 10 and SiC substrate 20 to be contacted with each other in step (S30) described later is planarized by, for example, polishing.
- this process (S20) is not an essential process, since the size of the gap between the base substrate 10 and the SiC substrate 20 facing each other becomes uniform by performing this process, it will be described later.
- the uniformity of reaction (bonding) within the bonding surface is improved. As a result, base substrate 10 and SiC substrate 20 can be more reliably bonded.
- the surface roughness Ra of the joint surface is preferably less than 100 nm, and preferably less than 50 nm. Furthermore, more reliable bonding can be achieved by setting the surface roughness Ra of the bonding surface to less than 10 nm.
- the step (S20) may be performed without omitting the step (S20) and polishing the main surfaces of the base substrate 10 and the SiC substrate 20 to be in contact with each other. Thereby, the manufacturing cost of silicon carbide substrate 1 can be reduced. Further, from the viewpoint of removing the damaged layer near the surface formed by slicing or the like during the production of the base substrate 10 and the SiC substrate 20, for example, the step of removing the damaged layer by etching is replaced with the step (S20). Or after performing after the said process (S20), the process (S30) mentioned later may be implemented.
- a stacking step is performed.
- SiC substrate 20 is placed so as to be in contact with the main surface of base substrate 10 to produce a laminated substrate.
- main surface 20A of SiC substrate 20 opposite to base substrate 10 may have an off angle of 50 ° or more and 65 ° or less with respect to the ⁇ 0001 ⁇ plane.
- silicon carbide substrate 1 in which main surface 20A of SiC layer 20 has an off angle of 50 ° or more and 65 ° or less with respect to the ⁇ 0001 ⁇ plane can be easily manufactured.
- an angle formed between the off orientation of the main surface 20A and the ⁇ 1-100> direction may be 5 ° or less.
- the off angle of the main surface 20A with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction may be -3 ° or more and 5 ° or less.
- the channel mobility in the case where a MOSFET or the like is manufactured using manufactured silicon carbide substrate 1 can be further improved.
- the angle formed between the off orientation of the main surface 20A and the ⁇ 11-20> direction may be 5 ° or less.
- a joining step is performed as a step (S40).
- the base substrate 10 and the SiC substrate 20 are joined by heating the laminated substrate.
- silicon carbide substrate 1 in the first embodiment provided with bonded SiC substrate 20 as SiC layer 20 can be easily manufactured.
- the multilayer substrate may be heated in an atmosphere obtained by reducing the atmospheric pressure. Thereby, the manufacturing cost of silicon carbide substrate 1 can be reduced.
- a gap formed between the base substrate 10 and the SiC substrate 20 is 100 ⁇ m or less. Thereby, uniform joining of base substrate 10 and SiC substrate 20 can be achieved in the step (S40).
- the laminated substrate is heated to a temperature range equal to or higher than the sublimation temperature of silicon carbide.
- base substrate 10 and SiC substrate 20 can be more reliably bonded.
- the gap formed between the base substrate 10 and the SiC substrate 20 in the laminated substrate is set to 100 ⁇ m or less, uniform bonding by sublimation of SiC can be achieved.
- the heating temperature of the laminated substrate in the step (S40) is preferably 1800 ° C. or higher and 2500 ° C. or lower.
- the heating temperature is lower than 1800 ° C., it takes a long time to join base substrate 10 and SiC substrate 20, and the manufacturing efficiency of silicon carbide substrate 1 decreases.
- the heating temperature exceeds 2500 ° C., the surfaces of base substrate 10 and SiC substrate 20 are roughened, and there is a risk that the number of crystal defects in silicon carbide substrate 1 to be manufactured increases.
- the heating temperature of the laminated substrate in step (S40) is preferably 1900 ° C. or higher and 2100 ° C. or lower.
- the said joining can be implemented with a simple apparatus by the pressure of the atmosphere at the time of a heating in a process (S40) being 10 ⁇ -5 > Pa or more and 10 ⁇ 6 > Pa or less.
- the laminated substrate may be heated under a pressure higher than 10 ⁇ 1 Pa and lower than 10 4 Pa.
- the atmosphere during heating in the step (S40) may be an inert gas atmosphere.
- the step of polishing the main surface of SiC substrate 20 corresponding to main surface 20A on the opposite side of base substrate 10 of SiC substrate 20 in the laminated substrate is performed. Furthermore, you may provide. Thereby, silicon carbide substrate 1 in which main surface 20 ⁇ / b> A opposite to base substrate 10 of SiC layer 20 is polished can be manufactured.
- the step of performing the polishing may be performed before the bonding of the base substrate 10 and the SiC substrate 20 after the step (S10), or may be performed after the bonding.
- silicon carbide substrate 1 in the second embodiment has basically the same configuration as silicon carbide substrate 1 in the first embodiment, has the same effects, and is manufactured in the same manner. be able to.
- silicon carbide substrate 1 in the second embodiment is different from the first embodiment in that a plurality of SiC layers 20 are laminated.
- silicon carbide substrate 1 in the second embodiment includes a plurality of (two in this embodiment) SiC layers 20 on base substrate 10.
- silicon carbide substrate 1 in the present embodiment is a silicon carbide substrate provided with SiC layer 20 corresponding to the structure of the target semiconductor device. More specifically, for example, when silicon carbide substrate 1 is used for manufacturing a vertical power device (vertical MOSFET; Metal Oxide Semiconductor Effect Transistor, etc.), resistance in the stacking direction (thickness direction) of silicon carbide substrate 1 In order to reduce the rate as much as possible, it is preferable to increase the impurity density in the base substrate 10.
- vertical MOSFET Metal Oxide Semiconductor Effect Transistor
- the lattice constant of SiC constituting the base substrate 10 changes. Therefore, when the SiC substrate 20 having a significantly lower impurity density than the base substrate 10 is directly bonded to the base substrate 10 having a high impurity density, the base substrate 10 and the SiC substrate 20 can be obtained due to a difference in lattice constant. There is a possibility that the strain and warpage of the silicon carbide substrate 1 to be increased, and the density of crystal defects may be increased.
- a lattice constant in the thickness direction of silicon carbide substrate 1 is sandwiched between base substrate 10 having a high impurity density and SiC substrate 20 having a low impurity density, with another SiC substrate 20 having an intermediate impurity density in between.
- the occurrence of such a problem can be suppressed by gradually changing.
- Silicon carbide substrate 1 in the second embodiment is formed by stacking a plurality (two) of SiC substrates 20 on base substrate 10 in step (S30) of the method for manufacturing silicon carbide substrate 1 in the first embodiment. Therefore, it can be implemented in the same manner as in the first embodiment.
- silicon carbide substrate 1 including a plurality of layers of SiC substrates 20 bonded more firmly can be manufactured.
- steps (S10) to (S40) are performed in the same manner as in the first embodiment.
- a 2nd lamination process is implemented as process (S50).
- another SiC substrate 20 is further laminated on the SiC substrate 20 laminated on the base substrate 10 in the step (S30) and bonded to the base substrate 10 in the step (S40).
- a two-layer substrate is produced.
- a second joining step is performed.
- the second laminated substrate is heated in the same manner as in the step (S40), so that the laminated substrate and the other SiC substrate 20 are bonded.
- silicon carbide substrate 1 in which a plurality of SiC layers 20 are stacked can be easily formed. Can be manufactured.
- the main surfaces (bonding surfaces) of SiC substrates 20 that should be in contact with each other in the step (S50) may be planarized.
- the surface roughness Ra of the bonding surface is preferably less than 100 nm, and preferably less than 50 nm. Furthermore, more reliable bonding can be achieved by setting the surface roughness Ra of the bonding surface to less than 10 nm.
- the polishing (flattening) may be omitted, and the step (S50) may be performed without polishing the main surfaces of the SiC substrates 20 to be in contact with each other. Thereby, the manufacturing cost of silicon carbide substrate 1 can be reduced.
- the step of removing the damaged layer by etching is replaced with the flattening or the flattening is performed. It is carried out after being carried out, and then the step (S50) may be carried out.
- silicon carbide substrate 1 in the third embodiment basically has the same configuration as silicon carbide substrate 1 in the first embodiment, exhibits the same effects, and has the same Can be manufactured. However, silicon carbide substrate 1 in the third embodiment is different from that in the first embodiment in that a plurality of SiC layers 20 are arranged in a plan view.
- silicon carbide substrate 1 of the third embodiment a plurality of SiC layers 20 (9 in the present embodiment) are arranged side by side in a plan view. . That is, a plurality of SiC layers 20 are arranged side by side along main surface 10 ⁇ / b> A of base substrate 10. More specifically, nine SiC layers 20 are arranged in a matrix so that adjacent SiC layers 20 on base substrate 10 are in contact with each other.
- silicon carbide substrate 1 in the present embodiment is silicon carbide substrate 1 that can be handled as a large-diameter substrate having high-quality SiC layer 20. And by using this silicon carbide substrate 1, the manufacturing process of a semiconductor device can be made efficient. Referring to FIG.
- end surface 20 ⁇ / b> B of adjacent SiC layer 20 is substantially perpendicular to main surface 20 ⁇ / b> A of SiC layer 20.
- silicon carbide substrate 1 of the present embodiment can be easily manufactured.
- Silicon carbide substrate 1 in the third embodiment is formed by arranging a plurality of SiC substrates 20 whose end surface 20B is substantially perpendicular to main surface 20A in a step (S30) in a plane. It can be manufactured in the same manner as in the first embodiment.
- SiC layer 20 may be arranged on base substrate 10, and a plurality of SiC layers 20 may be arranged side by side on the SiC layer 20 as viewed in plan.
- SiC substrate 20 whose end surface 20B is substantially perpendicular to main surface 20A is flat in the manufacturing method step (S50) described with reference to FIG. 4 in the second embodiment.
- S50 manufacturing method step
- the crystal structure of silicon carbide constituting SiC layer 20 is preferably a hexagonal system, and more preferably 4H—SiC.
- Base substrate 10 and SiC layer 20 are preferably made of a silicon carbide single crystal having the same crystal structure (when there are a plurality of SiC layers 20, the adjacent SiC layers 20 are also adjacent to each other).
- the silicon carbide single crystal having the same crystal structure as the base substrate 10 and the SiC layer 20 the physical properties such as the thermal expansion coefficient are unified, and the silicon carbide substrate and the silicon carbide substrate are used.
- warpage of silicon carbide substrate 1, separation between base substrate 10 and SiC layer 20, or separation between SiC layers 20 can be suppressed.
- the angle formed by the c-axis of the silicon carbide single crystal constituting each is less than 1 °. It is preferable that the angle is less than 0.1 °. Furthermore, it is preferable that the c-plane of the silicon carbide single crystal is not rotated in the plane.
- the diameter of the base substrate 10 is preferably 2 inches or more, and more preferably 6 inches or more.
- the thickness of silicon carbide substrate 1 is preferably 200 ⁇ m or more and 1000 ⁇ m or less, and more preferably 300 ⁇ m or more and 700 ⁇ m or less.
- the resistivity of SiC layer 20 is preferably 50 m ⁇ cm or less, and more preferably 20 m ⁇ cm or less.
- a semiconductor device 101 according to the present invention is a vertical DiMOSFET (Double Implanted MOSFET), and includes a substrate 102, a buffer layer 121, a breakdown voltage holding layer 122, a p region 123, an n + region 124, and a p +.
- a region 125, an oxide film 126, a source electrode 111 and an upper source electrode 127, a gate electrode 110, and a drain electrode 112 formed on the back side of the substrate 102 are provided.
- buffer layer 121 made of silicon carbide is formed on the surface of substrate 102 made of silicon carbide of n-type conductivity.
- substrate 102 the silicon carbide substrate of the present invention including silicon carbide substrate 1 described in the first to third embodiments is employed.
- buffer layer 121 is formed on SiC layer 20 of silicon carbide substrate 1.
- Buffer layer 121 has n-type conductivity, and its thickness is, for example, 0.5 ⁇ m.
- the density of the n-type conductive impurity in the buffer layer 121 can be set to 5 ⁇ 10 17 cm ⁇ 3 , for example.
- a breakdown voltage holding layer 122 is formed on the buffer layer 121.
- the breakdown voltage holding layer 122 is made of silicon carbide of n-type conductivity, and has a thickness of 10 ⁇ m, for example. Further, as the density of the n-type conductive impurity in the breakdown voltage holding layer 122, for example, a value of 5 ⁇ 10 15 cm ⁇ 3 can be used.
- p regions 123 having a conductivity type of p type are formed at intervals. Inside the p region 123, an n + region 124 is formed in the surface layer of the p region 123. A p + region 125 is formed at a position adjacent to the n + region 124. From the n + region 124 in one p region 123 to the p region 123, the breakdown voltage holding layer 122 exposed between the two p regions 123, the other p region 123, and the n + region 124 in the other p region 123 An oxide film 126 is formed so as to extend to. A gate electrode 110 is formed on the oxide film 126.
- a source electrode 111 is formed on the n + region 124 and the p + region 125.
- An upper source electrode 127 is formed on the source electrode 111.
- a drain electrode 112 is formed on the back surface of the substrate 102 which is the surface opposite to the surface on which the buffer layer 121 is formed.
- the silicon carbide substrate of the present invention such as the silicon carbide substrate 1 described in the first to third embodiments is employed as the substrate 102. That is, semiconductor device 101 includes substrate 102 as a silicon carbide substrate, buffer layer 121 and breakdown voltage holding layer 122 as epitaxial growth formed on substrate 102, and source electrode 111 formed on breakdown voltage holding layer 122. I have.
- the substrate 102 is a silicon carbide substrate of the present invention such as the silicon carbide substrate 1.
- the silicon carbide substrate of the present invention is a silicon carbide substrate capable of reducing the manufacturing cost of the semiconductor device. Therefore, the semiconductor device 101 is a semiconductor device with reduced manufacturing costs.
- a substrate preparation step (S110) is performed.
- a substrate 102 (see FIG. 9) made of silicon carbide having a (03-38) plane as a main surface is prepared.
- the silicon carbide substrate of the present invention including silicon carbide substrate 1 manufactured by the manufacturing method described in the first to third embodiments is prepared.
- this substrate 102 for example, a substrate having an n-type conductivity and a substrate resistance of 0.02 ⁇ cm may be used.
- an epitaxial layer forming step (S120) is performed. Specifically, the buffer layer 121 is formed on the surface of the substrate 102. Buffer layer 121 is formed on SiC layer 20 of silicon carbide substrate 1 employed as substrate 102 (see FIGS. 1, 3, and 5). Buffer layer 121 is formed of an n-type silicon carbide, and an epitaxial layer having a thickness of 0.5 ⁇ m, for example, is formed. As the density of the conductive impurities in the buffer layer 121, for example, a value of 5 ⁇ 10 17 cm ⁇ 3 can be used. Then, a breakdown voltage holding layer 122 is formed on the buffer layer 121 as shown in FIG.
- breakdown voltage holding layer 122 a layer made of silicon carbide of n-type conductivity is formed by an epitaxial growth method.
- a thickness of the breakdown voltage holding layer 122 for example, a value of 10 ⁇ m can be used.
- a value of 5 ⁇ 10 15 cm ⁇ 3 can be used.
- an injection step (S130) is performed as shown in FIG. Specifically, by using an oxide film formed by photolithography and etching as a mask, an impurity having a conductivity type of p type is implanted into the breakdown voltage holding layer 122, thereby forming the p region 123 as shown in FIG. Form. Further, after removing the used oxide film, an oxide film having a new pattern is formed again by photolithography and etching. Then, by using the oxide film as a mask, an n-type conductive impurity is implanted into a predetermined region, thereby forming an n + region 124. Further, the p + region 125 is formed by injecting a p-type conductive impurity in the same manner. As a result, a structure as shown in FIG. 10 is obtained.
- activation annealing is performed.
- this activation annealing treatment for example, argon gas is used as an atmospheric gas, and conditions such as a heating temperature of 1700 ° C. and a heating time of 30 minutes can be used.
- a gate insulating film formation step (S140) is performed as shown in FIG. Specifically, as illustrated in FIG. 11, an oxide film 126 is formed so as to cover the breakdown voltage holding layer 122, the p region 123, the n + region 124, and the p + region 125.
- a condition for forming this oxide film 126 for example, dry oxidation (thermal oxidation) may be performed.
- dry oxidation thermal oxidation
- conditions for this dry oxidation conditions such as a heating temperature of 1200 ° C. and a heating time of 30 minutes can be used.
- a nitrogen annealing step (S150) is performed as shown in FIG. Specifically, the annealing process is performed using nitrogen monoxide (NO) as the atmosphere gas.
- NO nitrogen monoxide
- the heating temperature is 1100 ° C. and the heating time is 120 minutes.
- nitrogen atoms are introduced near the interface between the oxide film 126 and the underlying breakdown voltage holding layer 122, p region 123, n + region 124, and p + region 125.
- annealing using nitrogen monoxide as an atmospheric gas annealing using nitrogen monoxide as an atmospheric gas.
- argon (Ar) gas which is an inert gas may be performed.
- argon gas may be used as the atmosphere gas
- the heating temperature may be 1100 ° C. and the heating time may be 60 minutes.
- an electrode forming step (S160) is performed as shown in FIG. Specifically, a resist film having a pattern is formed on the oxide film 126 by using a photolithography method. Using the resist film as a mask, portions of the oxide film located on n + region 124 and p + region 125 are removed by etching. Thereafter, a conductor film such as a metal is formed so as to be in contact with n + region 124 and p + region 125 on the resist film and inside the opening formed in oxide film 126. Thereafter, by removing the resist film, the conductor film located on the resist film is removed (lifted off).
- nickel (Ni) can be used as the conductor.
- the source electrode 111 and the drain electrode 112 can be obtained as shown in FIG.
- an argon (Ar) gas that is an inert gas is used as the atmosphere gas, and a heat treatment (alloying treatment) is performed with a heating temperature of 950 ° C. and a heating time of 2 minutes.
- an upper source electrode 127 (see FIG. 7) is formed on the source electrode 111. Further, the gate electrode 110 (see FIG. 7) is formed on the oxide film 126. In this way, the semiconductor device 101 shown in FIG. 7 can be obtained.
- the vertical MOSFET has been described as an example of a semiconductor device that can be manufactured using the silicon carbide substrate of the present invention.
- the semiconductor device that can be manufactured is not limited thereto.
- various semiconductor devices such as JFET (Junction Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and Schottky barrier diode can be manufactured using the silicon carbide substrate of the present invention. It is.
- the semiconductor device is manufactured by forming the epitaxial layer functioning as the operation layer on the silicon carbide substrate having the (03-38) plane as the main surface has been described.
- the crystal plane that can be used as the main surface is not limited to this, and any crystal plane according to the application including the (0001) plane can be used as the main surface.
- Example 1 Embodiment 1 of the present invention will be described below.
- Various substrates made of silicon carbide single crystal were prepared, and an experiment was conducted to investigate whether or not the substrates can be bonded to each other when the heating temperature is changed.
- the experimental procedure is as follows.
- a substrate having the characteristics shown in Table 1 below was prepared, and the polished surfaces were kept in contact with each other in an inert gas atmosphere at a temperature of 1950 ° C. and a pressure of 1 Pa in a heating furnace for 3 hours. . Thereafter, the sample was taken out from the heating furnace, checked whether or not it was bonded, and the angle formed between the c-axes of the silicon carbide single crystals constituting the adjacent substrates was measured. In sample A, bonding of conductive substrates (substrates 1 and 2) having different micropipe density, threading screw dislocation density, threading edge dislocation density, basal plane dislocation density, mixed dislocation density, and stacking fault density was tried. .
- Sample B an attempt was made to join a conductive substrate (substrate 1) and a semi-insulating substrate (substrate 2) having different polytypes.
- Sample C an attempt was made to join three substrates (substrates 1 to 3).
- the surface roughness Ra represents the roughness of the joint surfaces that are in contact with each other.
- the surface roughness Ra the surface roughness in a square region having a side of 10 ⁇ m was measured.
- the off angle indicates the off angle of the main surface in the ⁇ 11-20> direction with respect to the plane orientation (0001). “-” Indicates that no measurement was performed.
- the heating temperature is important in bonding between substrates made of silicon carbide single crystal, and in order to achieve efficient bonding, the heating temperature is set to 1950 ° C. or higher, which is higher than the temperature at which SiC sublimates. It was confirmed that this was desirable.
- a substrate having the characteristics shown in Table 2 below was prepared, and held in an inert gas atmosphere at a temperature of 1950 ° C. and a pressure of 1 Pa in a heating furnace for 3 hours in a state where the main surfaces were in contact with each other. Then, the sample was taken out from the heating furnace, and it was confirmed whether it was joined.
- Example 3 An experiment was conducted to confirm the relationship between the crystal orientations of the base substrate and the SiC layer in the silicon carbide substrate obtained by the method for manufacturing a silicon carbide substrate of the present invention.
- the experimental procedure is as follows.
- two substrates (base substrate 10 and SiC substrate 20) made of SiC and having a main surface of (03-38) were prepared.
- two substrates are stacked so that the principal surfaces come into contact with each other to produce a laminated substrate, heated to 2100 ° C., which is higher than the sublimation temperature of SiC, and held in a nitrogen gas atmosphere at a pressure of 1 Pa for 30 hours.
- a silicon carbide substrate was manufactured by bonding two substrates under the following conditions. At this time, the temperature of the base substrate 10 was maintained at a slightly higher temperature than the SiC substrate 20. And the crystal orientation in the cross section perpendicular
- EBSD Back Scatter Diffraction
- Example 4 In the bonding of the multilayer substrates, an experiment was conducted to investigate the relationship between the size of the gap formed between the base substrate and the SiC substrate and the bonding state of the multilayer substrates.
- two substrates base substrate 10 and SiC substrate 20
- the two substrates were stacked so that the main surfaces thereof were in contact with each other to produce a laminated substrate.
- the size of the gap formed between the two substrates was adjusted to be 0.5 to 1000 ⁇ m.
- the laminated substrate was heated to 2100 ° C. and kept in a nitrogen gas atmosphere at a pressure of 1 Pa for 30 hours. And the joining state of the laminated substrate after the said process was confirmed.
- Table 3 The experimental results are shown in Table 3.
- the gap formed between the base substrate and the SiC substrate is preferably 100 ⁇ m or less in order to achieve uniform bonding.
- a semiconductor device can be manufactured using the silicon carbide substrate of the present invention. That is, in the semiconductor device of the present invention, an epitaxial growth layer as an operation layer is formed on the silicon carbide substrate manufactured by the method for manufacturing a silicon carbide substrate of the present invention. If it demonstrates from another viewpoint, the epitaxial growth layer as an operation
- the semiconductor device of the present invention includes a base substrate made of silicon carbide, a SiC layer made of single crystal silicon carbide, arranged in contact with the base substrate, an epitaxial growth layer formed on the SiC layer, and And an electrode formed on the epitaxial growth layer.
- the silicon carbide substrate and the method for manufacturing the same of the present invention can be applied particularly advantageously to a silicon carbide substrate used for manufacturing a semiconductor device that requires a reduction in manufacturing cost and a method for manufacturing the same.
- the semiconductor device of the present invention can be applied particularly advantageously to a semiconductor device that requires a reduction in manufacturing cost.
- SYMBOLS 1 Silicon carbide substrate, 10 base substrate, 10A main surface, 20 SiC layer (SiC substrate), 20A main surface, 20B end surface, 30 boundary, 101 semiconductor device, 102 substrate, 110 gate electrode, 111 source electrode, 112 drain electrode, 121 buffer layer, 122 breakdown voltage holding layer, 123 p region, 124 n + region, 125 p + region, 126 oxide film, 127 upper source electrode.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
まず、本発明の一実施の形態である実施の形態1における炭化珪素基板の構造について説明する。図1を参照して、本実施の形態における炭化珪素基板1は、炭化珪素からなるベース基板10と、ベース基板10とは別の単結晶炭化珪素からなり、ベース基板10上に接触して配置されたSiC層20とを備えている。
次に、本発明の他の実施の形態である実施の形態2について説明する。図3を参照して、実施の形態2における炭化珪素基板1は、基本的には実施の形態1における炭化珪素基板1と同様の構成を有し、同様の効果を奏するとともに、同様に製造することができる。しかし、実施の形態2における炭化珪素基板1は、SiC層20が複数層積層されている点において、実施の形態1とは異なっている。
次に、本発明のさらに他の実施の形態である実施の形態3について説明する。図5および図6を参照して、実施の形態3における炭化珪素基板1は、基本的には実施の形態1における炭化珪素基板1と同様の構成を有し、同様の効果を奏するとともに、同様に製造することができる。しかし、実施の形態3における炭化珪素基板1は、SiC層20が平面的に見て複数並べて配置されている点において、実施の形態1の場合とは異なっている。
次に、上記本発明の炭化珪素基板を用いて作製される半導体装置の一例を実施の形態4として説明する。図7を参照して、本発明による半導体装置101は、縦型DiMOSFET(Double Implanted MOSFET)であって、基板102、バッファ層121、耐圧保持層122、p領域123、n+領域124、p+領域125、酸化膜126、ソース電極111および上部ソース電極127、ゲート電極110および基板102の裏面側に形成されたドレイン電極112を備える。具体的には、導電型がn型の炭化珪素からなる基板102の表面上に、炭化珪素からなるバッファ層121が形成されている。基板102としては、上記実施の形態1~3において説明した炭化珪素基板1を含む本発明の炭化珪素基板が採用される。そして、上記実施の形態1~3の炭化珪素基板1が採用される場合、バッファ層121は、炭化珪素基板1のSiC層20上に形成される。バッファ層121は導電型がn型であり、その厚みはたとえば0.5μmである。また、バッファ層121におけるn型の導電性不純物の密度はたとえば5×1017cm-3とすることができる。このバッファ層121上には耐圧保持層122が形成されている。この耐圧保持層122は、導電型がn型の炭化珪素からなり、たとえばその厚みは10μmである。また、耐圧保持層122におけるn型の導電性不純物の密度としては、たとえば5×1015cm-3という値を用いることができる。
以下、本発明の実施例1について説明する。炭化珪素単結晶からなる種々の基板を準備し、加熱温度を変化させた場合の基板同士の接合の可否を調査する実験を行なった。実験の手順は以下の通りである。
以下、本発明の実施例2について説明する。主面が(0001)面から大きく傾いた基板(面方位{0001}に対するオフ角が50°以上65°以下の主面を有する基板)同士、および主面が(0001)面から大きく傾いた基板と主面が(0001)面である基板との接合の可否ついて検討する実験を行なった。実験の手順は以下の通りである。
本発明の炭化珪素基板の製造方法により得られる炭化珪素基板におけるベース基板とSiC層との結晶方位の関係を確認する実験を行なった。実験の手順は以下の通りである。
積層基板の接合において、ベース基板とSiC基板との間に形成される隙間の大きさと、積層基板の接合状態との関係を調査する実験を行なった。まず、上記実施例3の場合と同様に2枚の基板(ベース基板10およびSiC基板20)を準備し、その主面同士が接触するように2枚の基板を積み重ねて積層基板を作製した。このとき、2枚の基板の間に形成される隙間の大きさが0.5~1000μmとなるように調整した。そして、上記実施例3と同様に、上記積層基板を2100℃に加熱して、圧力1Paの窒素ガス雰囲気中に30時間保持した。そして、当該処理後の積層基板の接合状態を確認した。実験結果を表3に示す。
Claims (29)
- 炭化珪素からなるベース基板(10)と、
前記ベース基板(10)とは別の単結晶炭化珪素からなり、前記ベース基板(10)上に接触して配置されたSiC層(20)とを備える、炭化珪素基板(1)。 - 前記ベース基板(10)は単結晶炭化珪素からなり、
前記SiC層(20)のマイクロパイプ密度は、前記ベース基板(10)のマイクロパイプ密度よりも小さくなっている、請求の範囲第1項に記載の炭化珪素基板(1)。 - 前記ベース基板(10)は単結晶炭化珪素からなり、
前記SiC層(20)の転位密度は、前記ベース基板(10)の転位密度よりも小さくなっている、請求の範囲第1項に記載の炭化珪素基板(1)。 - 前記ベース基板(10)は単結晶炭化珪素からなり、
前記SiC層(20)のX線ロッキングカーブの半値幅は、前記ベース基板(10)のX線ロッキングカーブの半値幅よりも小さくなっている、請求の範囲第1項に記載の炭化珪素基板(1)。 - 前記ベース基板(10)は、前記SiC層(20)に対向する側の主面(10A)を含むように単結晶炭化珪素からなる単結晶層(10B)を含む、請求の範囲第1項に記載の炭化珪素基板(1)。
- 前記SiC層(20)のマイクロパイプ密度は、前記単結晶層(10B)のマイクロパイプ密度よりも小さくなっている、請求の範囲第5項に記載の炭化珪素基板(1)。
- 前記SiC層(20)の転位密度は、前記単結晶層(10B)の転位密度よりも小さくなっている、請求の範囲第5項に記載の炭化珪素基板(1)。
- 前記SiC層(20)のX線ロッキングカーブの半値幅は、前記単結晶層(10B)のX線ロッキングカーブの半値幅よりも小さくなっている、請求の範囲第5項に記載の炭化珪素基板(1)。
- 前記SiC層(20)は、平面的に見て複数並べて配置されている、請求の範囲第1項に記載の炭化珪素基板(1)。
- 前記SiC層(20)は、平面的に見て複数並べて配置されている、請求の範囲第5項に記載の炭化珪素基板(1)。
- 前記SiC層(20)の、前記ベース基板(10)とは反対側の主面(20A)は、面方位{0001}に対するオフ角が50°以上65°以下となっている、請求の範囲第1項に記載の炭化珪素基板(1)。
- 前記主面(20A)のオフ方位と<1-100>方向とのなす角は5°以下となっている、請求の範囲第11項に記載の炭化珪素基板(1)。
- 前記主面(20A)の、<1-100>方向における{03-38}面に対するオフ角は-3°以上5°以下である、請求の範囲第12項に記載の炭化珪素基板(1)。
- 前記主面(20A)のオフ方位と<11-20>方向とのなす角は5°以下となっている、請求の範囲第11項に記載の炭化珪素基板(1)。
- 前記SiC層(20)の、前記ベース基板(10)とは反対側の主面(20A)は研磨されている、請求の範囲第1項に記載の炭化珪素基板(1)。
- 炭化珪素基板(102)と、
前記炭化珪素基板(102)上に形成されたエピタキシャル成長層(122)と、
前記エピタキシャル成長層(122)上に形成された電極(111)とを備え、
前記炭化珪素基板(102)は、請求の範囲第1項に記載の炭化珪素基板(1)である、半導体装置(101)。 - 炭化珪素からなるベース基板(10)および単結晶炭化珪素からなるSiC基板(20)を準備する工程と、
前記ベース基板(10)の主面(10A)上に接触するように前記SiC基板(20)を載置して、積層基板を作製する工程と、
前記積層基板を加熱することにより、前記ベース基板(10)と前記SiC基板(20)とを接合する工程と備えた、炭化珪素基板(1)の製造方法。 - 前記積層基板においては、前記ベース基板(10)と前記SiC基板(20)との間に形成される隙間は100μm以下となっている、請求の範囲第17項に記載の炭化珪素基板(1)の製造方法。
- 前記ベース基板(10)と前記SiC基板(20)とを接合する工程では、炭化珪素の昇華温度以上の温度域に前記積層基板が加熱される、請求の範囲第17項に記載の炭化珪素基板(1)の製造方法。
- 前記積層基板を作製する工程よりも前に、前記積層基板を作製する工程において互いに接触すべき前記ベース基板(10)および前記SiC基板(20)の主面を平坦化する工程をさらに備えた、請求の範囲第17項に記載の炭化珪素基板(1)の製造方法。
- 前記積層基板を作製する工程は、前記積層基板を作製する工程よりも前に、前記積層基板を作製する工程において互いに接触すべき前記ベース基板(10)および前記SiC基板(20)の主面を研磨することなく実施される、請求の範囲第17項に記載の炭化珪素基板(1)の製造方法。
- 前記積層基板を作製する工程では、前記SiC基板(20)は、平面的に見て複数並べて載置される、請求の範囲第17項に記載の炭化珪素基板(1)の製造方法。
- 前記積層基板を作製する工程では、前記SiC基板(20)の前記ベース基板(10)とは反対側の主面(20A)は、{0001}面に対するオフ角が50°以上65°以下となっている、請求の範囲第17項に記載の炭化珪素基板(1)の製造方法。
- 前記積層基板を作製する工程では、前記SiC基板(20)の前記ベース基板(10)とは反対側の主面(20A)のオフ方位と<1-100>方向とのなす角は5°以下となっている、請求の範囲第23項に記載の炭化珪素基板(1)の製造方法。
- 前記積層基板を作製する工程では、前記SiC基板(20)の前記ベース基板(10)とは反対側の主面(20A)の、<1-100>方向における{03-38}面に対するオフ角は-3°以上5°以下である、請求の範囲第24項に記載の炭化珪素基板(1)の製造方法。
- 前記積層基板を作製する工程では、前記SiC基板(20)の前記ベース基板(10)とは反対側の主面(20A)のオフ方位と<11-20>方向とのなす角は5°以下となっている、請求の範囲第23項に記載の炭化珪素基板(1)の製造方法。
- 前記ベース基板(10)と前記SiC基板(20)とを接合する工程では、大気雰囲気を減圧することにより得られた雰囲気中において前記積層基板が加熱される、請求の範囲第17項に記載の炭化珪素基板(1)の製造方法。
- 前記ベース基板(10)と前記SiC基板(20)とを接合する工程では、10-1Paよりも高く104Paよりも低い圧力下において前記積層基板が加熱される、請求の範囲第17項に記載の炭化珪素基板(1)の製造方法。
- 前記積層基板における前記SiC基板(20)の、前記ベース基板(10)とは反対側の主面(20A)に対応する前記SiC基板(20)の主面を研磨する工程をさらに備えた、請求の範囲第17項に記載の炭化珪素基板(1)の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010800205181A CN102422387A (zh) | 2009-05-11 | 2010-04-27 | 碳化硅衬底、半导体器件和制造碳化硅衬底的方法 |
JP2011513299A JPWO2010131568A1 (ja) | 2009-05-11 | 2010-04-27 | 炭化珪素基板、半導体装置および炭化珪素基板の製造方法 |
EP10774826A EP2432000A4 (en) | 2009-05-11 | 2010-04-27 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SILICON CARBIDE SUBSTRATE |
KR1020117028635A KR20120014017A (ko) | 2009-05-11 | 2010-04-27 | 탄화규소 기판, 반도체 장치 및 탄화규소 기판의 제조 방법 |
CA2761428A CA2761428A1 (en) | 2009-05-11 | 2010-04-27 | Silicon carbide substrate, semiconductor device, and method of manufacturing silicon carbide substrate |
US13/319,560 US20120061686A1 (en) | 2009-05-11 | 2010-04-27 | Silicon carbide substrate, semiconductor device, and method of manufacturing silicon carbide substrate |
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009-114737 | 2009-05-11 | ||
JP2009114737 | 2009-05-11 | ||
JP2009-219065 | 2009-09-24 | ||
JP2009219065 | 2009-09-24 | ||
JP2009-229764 | 2009-10-01 | ||
JP2009229764 | 2009-10-01 | ||
JP2009248621 | 2009-10-29 | ||
JP2009-248621 | 2009-10-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010131568A1 true WO2010131568A1 (ja) | 2010-11-18 |
Family
ID=43084945
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/057441 WO2010131569A1 (ja) | 2009-05-11 | 2010-04-27 | 半導体基板の製造方法 |
PCT/JP2010/057439 WO2010131568A1 (ja) | 2009-05-11 | 2010-04-27 | 炭化珪素基板、半導体装置および炭化珪素基板の製造方法 |
PCT/JP2010/057445 WO2010131573A1 (ja) | 2009-05-11 | 2010-04-27 | 絶縁ゲート型バイポーラトランジスタ |
PCT/JP2010/057442 WO2010131570A1 (ja) | 2009-05-11 | 2010-04-27 | 炭化珪素基板および半導体装置 |
PCT/JP2010/057444 WO2010131572A1 (ja) | 2009-05-11 | 2010-04-27 | 半導体装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/057441 WO2010131569A1 (ja) | 2009-05-11 | 2010-04-27 | 半導体基板の製造方法 |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/057445 WO2010131573A1 (ja) | 2009-05-11 | 2010-04-27 | 絶縁ゲート型バイポーラトランジスタ |
PCT/JP2010/057442 WO2010131570A1 (ja) | 2009-05-11 | 2010-04-27 | 炭化珪素基板および半導体装置 |
PCT/JP2010/057444 WO2010131572A1 (ja) | 2009-05-11 | 2010-04-27 | 半導体装置 |
Country Status (8)
Country | Link |
---|---|
US (5) | US20120056201A1 (ja) |
EP (5) | EP2432022A1 (ja) |
JP (5) | JP5344037B2 (ja) |
KR (5) | KR20120014017A (ja) |
CN (5) | CN102422387A (ja) |
CA (5) | CA2761430A1 (ja) |
TW (5) | TW201104865A (ja) |
WO (5) | WO2010131569A1 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8168515B2 (en) | 2009-05-11 | 2012-05-01 | Sumitomo Electric Industries, Ltd. | Method for manufacturing semiconductor substrate |
WO2012127748A1 (ja) * | 2011-03-22 | 2012-09-27 | 住友電気工業株式会社 | 炭化珪素基板 |
WO2012132594A1 (ja) * | 2011-03-25 | 2012-10-04 | 住友電気工業株式会社 | 炭化珪素基板 |
JP2017081813A (ja) * | 2011-08-05 | 2017-05-18 | 住友電気工業株式会社 | 基板、半導体装置およびこれらの製造方法 |
JP2023501646A (ja) * | 2019-11-14 | 2023-01-18 | ファーウェイ デジタル パワー テクノロジーズ カンパニー リミテッド | 半導体基板、その製造方法、及び半導体装置 |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG10201600407SA (en) * | 2009-02-20 | 2016-02-26 | Semiconductor Energy Lab | Semiconductor device and manufacturing method of the same |
US20120015499A1 (en) * | 2009-11-13 | 2012-01-19 | Sumitomo Electric Industries, Ltd. | Method for manufacturing semiconductor substrate |
EP2532773A4 (en) * | 2010-02-05 | 2013-12-11 | Sumitomo Electric Industries | PROCESS FOR PRODUCING SILICON CARBIDE SUBSTRATE |
JP2011246315A (ja) * | 2010-05-28 | 2011-12-08 | Sumitomo Electric Ind Ltd | 炭化珪素基板およびその製造方法 |
JP5447206B2 (ja) * | 2010-06-15 | 2014-03-19 | 住友電気工業株式会社 | 炭化珪素単結晶の製造方法および炭化珪素基板 |
JP2013018693A (ja) * | 2011-06-16 | 2013-01-31 | Sumitomo Electric Ind Ltd | 炭化珪素基板およびその製造方法 |
JPWO2013073216A1 (ja) * | 2011-11-14 | 2015-04-02 | 住友電気工業株式会社 | 炭化珪素基板、半導体装置およびこれらの製造方法 |
KR101984698B1 (ko) * | 2012-01-11 | 2019-05-31 | 삼성전자주식회사 | 기판 구조체, 이로부터 제조된 반도체소자 및 그 제조방법 |
JP6119100B2 (ja) * | 2012-02-01 | 2017-04-26 | 住友電気工業株式会社 | 炭化珪素半導体装置 |
TWI456737B (zh) * | 2012-03-05 | 2014-10-11 | Richtek Technology Corp | 垂直式半導體元件及其製造方法 |
CN103325747A (zh) * | 2012-03-19 | 2013-09-25 | 立锜科技股份有限公司 | 垂直式半导体元件及其制造方法 |
JP5884585B2 (ja) * | 2012-03-21 | 2016-03-15 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
US9466552B2 (en) * | 2012-03-30 | 2016-10-11 | Richtek Technology Corporation | Vertical semiconductor device having a non-conductive substrate and a gallium nitride layer |
KR101386119B1 (ko) * | 2012-07-26 | 2014-04-21 | 한국전기연구원 | SiC MOSFET의 오믹 접합 형성방법 |
US9184229B2 (en) * | 2012-07-31 | 2015-11-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
US8860040B2 (en) * | 2012-09-11 | 2014-10-14 | Dow Corning Corporation | High voltage power semiconductor devices on SiC |
US9018639B2 (en) | 2012-10-26 | 2015-04-28 | Dow Corning Corporation | Flat SiC semiconductor substrate |
US9797064B2 (en) | 2013-02-05 | 2017-10-24 | Dow Corning Corporation | Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a support shelf which permits thermal expansion |
US9738991B2 (en) | 2013-02-05 | 2017-08-22 | Dow Corning Corporation | Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a supporting shelf which permits thermal expansion |
US9017804B2 (en) | 2013-02-05 | 2015-04-28 | Dow Corning Corporation | Method to reduce dislocations in SiC crystal growth |
JP6297783B2 (ja) | 2013-03-08 | 2018-03-20 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
US8940614B2 (en) | 2013-03-15 | 2015-01-27 | Dow Corning Corporation | SiC substrate with SiC epitaxial film |
JP6119564B2 (ja) | 2013-11-08 | 2017-04-26 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
JP6356428B2 (ja) * | 2014-02-17 | 2018-07-11 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN103855206A (zh) * | 2014-02-18 | 2014-06-11 | 宁波达新半导体有限公司 | 绝缘栅双极晶体管及其制造方法 |
JP2015176995A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP6180978B2 (ja) * | 2014-03-20 | 2017-08-16 | 株式会社東芝 | 半導体装置およびその製造方法 |
US9279192B2 (en) | 2014-07-29 | 2016-03-08 | Dow Corning Corporation | Method for manufacturing SiC wafer fit for integration with power device manufacturing technology |
WO2016059670A1 (ja) * | 2014-10-14 | 2016-04-21 | 三菱電機株式会社 | 炭化珪素エピタキシャルウエハの製造方法 |
CN104465721B (zh) * | 2014-12-05 | 2019-05-14 | 国家电网公司 | 一种碳化硅外延材料及其制备方法 |
JP2017059600A (ja) | 2015-09-14 | 2017-03-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
US10490634B2 (en) * | 2015-11-24 | 2019-11-26 | Sumitomo Electric Industries, Ltd. | Silicon carbide epitaxial substrate having a silicon carbide layer and method of manufacturing silicon carbide semiconductor device |
CN105679647B (zh) * | 2015-12-31 | 2018-06-29 | 清华大学 | 具有原子级平整表面的衬底的制备方法 |
WO2018016171A1 (ja) * | 2016-07-21 | 2018-01-25 | 三菱電機株式会社 | 炭化珪素半導体装置、および、炭化珪素半導体装置の製造方法 |
JP6703915B2 (ja) | 2016-07-29 | 2020-06-03 | 富士電機株式会社 | 炭化珪素半導体基板、炭化珪素半導体基板の製造方法、半導体装置および半導体装置の製造方法 |
KR101866869B1 (ko) | 2016-08-18 | 2018-06-14 | 주식회사 티씨케이 | SiC 소재 및 SiC 복합 소재 |
CN110214363B (zh) * | 2017-01-31 | 2023-07-28 | 住友电气工业株式会社 | 碳化硅外延衬底和制造碳化硅半导体器件的方法 |
JP6969578B2 (ja) * | 2017-01-31 | 2021-11-24 | 住友電気工業株式会社 | 炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法 |
JP6883745B2 (ja) | 2017-03-24 | 2021-06-09 | パナソニックIpマネジメント株式会社 | 半導体装置およびその製造方法 |
WO2019143733A1 (en) | 2018-01-16 | 2019-07-25 | Ipower Semiconductor | Self-aligned and robust igbt devices |
WO2019157222A1 (en) * | 2018-02-07 | 2019-08-15 | Ipower Semiconductor | Igbt devices with 3d backside structures for field stop and reverse conduction |
KR102649978B1 (ko) | 2018-05-03 | 2024-03-22 | 엘지전자 주식회사 | 정수기의 제어 방법 |
JP7239182B2 (ja) * | 2018-10-16 | 2023-03-14 | 山▲東▼天岳先▲進▼科技股▲フン▼有限公司 | 高純度炭化ケイ素単結晶基板及びその製造方法、応用 |
JP7143769B2 (ja) * | 2019-01-10 | 2022-09-29 | 三菱電機株式会社 | 炭化珪素半導体基板の製造方法及び炭化珪素半導体装置の製造方法 |
JP7410478B2 (ja) * | 2019-07-11 | 2024-01-10 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
CN113981535A (zh) * | 2020-07-27 | 2022-01-28 | 环球晶圆股份有限公司 | 碳化硅晶种及碳化硅晶体的制造方法 |
KR102442732B1 (ko) | 2021-11-05 | 2022-09-13 | 주식회사 쎄닉 | 탄화규소 웨이퍼 및 이의 제조방법 |
TWI831512B (zh) * | 2022-12-09 | 2024-02-01 | 鴻揚半導體股份有限公司 | 半導體裝置和其形成方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000277405A (ja) * | 1999-03-29 | 2000-10-06 | Meidensha Corp | 半導体素子の製造方法 |
WO2001018872A1 (fr) * | 1999-09-07 | 2001-03-15 | Sixon Inc. | TRANCHE DE SiC, DISPOSITIF A SEMI-CONDUCTEUR DE SiC, ET PROCEDE DE PRODUCTION D'UNE TRANCHE DE SiC |
JP2002280531A (ja) * | 2001-03-19 | 2002-09-27 | Denso Corp | 半導体基板及びその製造方法 |
JP2003224042A (ja) * | 2001-12-21 | 2003-08-08 | Soi Tec Silicon On Insulator Technologies | 半導体薄層の移し換え方法とそれに使用するドナーウエハの製造方法 |
WO2006114999A1 (ja) * | 2005-04-18 | 2006-11-02 | Kyoto University | 化合物半導体装置及び化合物半導体製造方法 |
JP2008235776A (ja) * | 2007-03-23 | 2008-10-02 | Sumco Corp | 貼り合わせウェーハの製造方法 |
JP2009117533A (ja) * | 2007-11-05 | 2009-05-28 | Shin Etsu Chem Co Ltd | 炭化珪素基板の製造方法 |
Family Cites Families (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0637276B2 (ja) * | 1988-01-18 | 1994-05-18 | 株式会社豊田自動織機製作所 | 上下移動機構付プッシャー装置 |
JP2846986B2 (ja) | 1991-10-30 | 1999-01-13 | 三菱マテリアル株式会社 | 半導体ウェーハの製造方法 |
JPH0748198A (ja) * | 1993-08-05 | 1995-02-21 | Sumitomo Electric Ind Ltd | ダイヤモンドの合成法 |
JPH10223835A (ja) * | 1997-02-05 | 1998-08-21 | Hitachi Ltd | 半導体装置とその製造方法 |
JP2961522B2 (ja) * | 1997-06-11 | 1999-10-12 | 日本ピラー工業株式会社 | 半導体電子素子用基板およびその製造方法 |
JP3254559B2 (ja) * | 1997-07-04 | 2002-02-12 | 日本ピラー工業株式会社 | 単結晶SiCおよびその製造方法 |
US6153166A (en) * | 1997-06-27 | 2000-11-28 | Nippon Pillar Packing Co., Ltd. | Single crystal SIC and a method of producing the same |
JPH1187200A (ja) * | 1997-09-05 | 1999-03-30 | Toshiba Corp | 半導体基板及び半導体装置の製造方法 |
JP2939615B2 (ja) * | 1998-02-04 | 1999-08-25 | 日本ピラー工業株式会社 | 単結晶SiC及びその製造方法 |
US6246076B1 (en) * | 1998-08-28 | 2001-06-12 | Cree, Inc. | Layered dielectric on silicon carbide semiconductor structures |
JP2002015619A (ja) | 2000-06-29 | 2002-01-18 | Kyocera Corp | 導電性材及びそれを用いた耐プラズマ部材及び半導体製造用装置 |
JP4843854B2 (ja) * | 2001-03-05 | 2011-12-21 | 住友電気工業株式会社 | Mosデバイス |
US6909119B2 (en) * | 2001-03-15 | 2005-06-21 | Cree, Inc. | Low temperature formation of backside ohmic contacts for vertical devices |
DE10247017B4 (de) * | 2001-10-12 | 2009-06-10 | Denso Corp., Kariya-shi | SiC-Einkristall, Verfahren zur Herstellung eines SiC-Einkristalls, SiC-Wafer mit einem Epitaxiefilm und Verfahren zur Herstellung eines SiC-Wafers, der einen Epitaxiefilm aufweist |
JP3559971B2 (ja) * | 2001-12-11 | 2004-09-02 | 日産自動車株式会社 | 炭化珪素半導体装置およびその製造方法 |
US6562127B1 (en) * | 2002-01-16 | 2003-05-13 | The United States Of America As Represented By The Secretary Of The Navy | Method of making mosaic array of thin semiconductor material of large substrates |
US8080826B1 (en) * | 2002-02-14 | 2011-12-20 | Rf Micro Devices, Inc. | High performance active and passive structures based on silicon material bonded to silicon carbide |
US20040144301A1 (en) * | 2003-01-24 | 2004-07-29 | Neudeck Philip G. | Method for growth of bulk crystals by vapor phase epitaxy |
EP2135977B1 (en) * | 2003-01-28 | 2012-03-07 | Sumitomo Electric Industries, Ltd. | Diamond composite substrate and a method for manufacturing same |
JP4730097B2 (ja) | 2003-06-13 | 2011-07-20 | 住友電気工業株式会社 | 電界効果トランジスタ |
JP4238357B2 (ja) * | 2003-08-19 | 2009-03-18 | 独立行政法人産業技術総合研究所 | 炭化珪素エピタキシャルウエハ、同ウエハの製造方法及び同ウエハ上に作製された半導体装置 |
JP4219800B2 (ja) | 2003-12-22 | 2009-02-04 | 株式会社豊田中央研究所 | SiC単結晶の製造方法 |
CN100433256C (zh) * | 2004-03-18 | 2008-11-12 | 克里公司 | 减少堆垛层错成核位置的顺序光刻方法和具有减少的堆垛层错成核位置的结构 |
JP4874527B2 (ja) | 2004-04-01 | 2012-02-15 | トヨタ自動車株式会社 | 炭化珪素半導体基板及びその製造方法 |
JP4442366B2 (ja) | 2004-08-27 | 2010-03-31 | 住友電気工業株式会社 | エピタキシャルSiC膜とその製造方法およびSiC半導体デバイス |
JP4733485B2 (ja) * | 2004-09-24 | 2011-07-27 | 昭和電工株式会社 | 炭化珪素単結晶成長用種結晶の製造方法、炭化珪素単結晶成長用種結晶、炭化珪素単結晶の製造方法、および炭化珪素単結晶 |
US7314520B2 (en) | 2004-10-04 | 2008-01-01 | Cree, Inc. | Low 1c screw dislocation 3 inch silicon carbide wafer |
JP2006228961A (ja) * | 2005-02-17 | 2006-08-31 | Toyota Central Res & Dev Lab Inc | 半導体装置 |
JP4775102B2 (ja) * | 2005-05-09 | 2011-09-21 | 住友電気工業株式会社 | 半導体装置の製造方法 |
US7391058B2 (en) * | 2005-06-27 | 2008-06-24 | General Electric Company | Semiconductor devices and methods of making same |
JP2008004726A (ja) * | 2006-06-22 | 2008-01-10 | Matsushita Electric Ind Co Ltd | 半導体素子およびその製造方法 |
JP4916247B2 (ja) * | 2006-08-08 | 2012-04-11 | トヨタ自動車株式会社 | 炭化珪素半導体装置及びその製造方法 |
CN100438083C (zh) * | 2006-12-23 | 2008-11-26 | 厦门大学 | δ掺杂4H-SiC PIN结构紫外光电探测器及其制备方法 |
JP4748067B2 (ja) | 2007-01-15 | 2011-08-17 | 株式会社デンソー | 炭化珪素単結晶の製造方法および製造装置 |
JP2008226997A (ja) * | 2007-03-09 | 2008-09-25 | Sumitomo Electric Ind Ltd | 半導体装置およびその製造方法 |
JP4348408B2 (ja) * | 2007-03-29 | 2009-10-21 | パナソニック株式会社 | 半導体装置の製造方法 |
JP4971340B2 (ja) * | 2007-03-29 | 2012-07-11 | パナソニック株式会社 | 炭化珪素半導体素子の製造方法 |
FR2914488B1 (fr) * | 2007-03-30 | 2010-08-27 | Soitec Silicon On Insulator | Substrat chauffage dope |
JP2008280207A (ja) | 2007-05-10 | 2008-11-20 | Matsushita Electric Ind Co Ltd | SiC単結晶基板の製造方法 |
JP5157843B2 (ja) * | 2007-12-04 | 2013-03-06 | 住友電気工業株式会社 | 炭化ケイ素半導体装置およびその製造方法 |
JP5504597B2 (ja) * | 2007-12-11 | 2014-05-28 | 住友電気工業株式会社 | 炭化ケイ素半導体装置およびその製造方法 |
JP2010184833A (ja) * | 2009-02-12 | 2010-08-26 | Denso Corp | 炭化珪素単結晶基板および炭化珪素単結晶エピタキシャルウェハ |
TW201104865A (en) | 2009-05-11 | 2011-02-01 | Sumitomo Electric Industries | Insulating gate type bipolar transistor |
JPWO2010131571A1 (ja) | 2009-05-11 | 2012-11-01 | 住友電気工業株式会社 | 半導体装置 |
CA2763055A1 (en) | 2009-09-24 | 2011-03-31 | Sumitomo Electric Industries, Ltd. | Silicon carbide ingot, silicon carbide substrate, manufacturing method thereof, crucible, and semiconductor substrate |
US20110221039A1 (en) * | 2010-03-12 | 2011-09-15 | Sinmat, Inc. | Defect capping for reduced defect density epitaxial articles |
JP2011233638A (ja) * | 2010-04-26 | 2011-11-17 | Sumitomo Electric Ind Ltd | 炭化珪素基板およびその製造方法 |
JP2011243848A (ja) * | 2010-05-20 | 2011-12-01 | Sumitomo Electric Ind Ltd | 炭化珪素基板の製造方法 |
JP2011256053A (ja) * | 2010-06-04 | 2011-12-22 | Sumitomo Electric Ind Ltd | 複合基板およびその製造方法 |
-
2010
- 2010-04-27 TW TW099113377A patent/TW201104865A/zh unknown
- 2010-04-27 JP JP2011513301A patent/JP5344037B2/ja not_active Expired - Fee Related
- 2010-04-27 CA CA2761430A patent/CA2761430A1/en not_active Abandoned
- 2010-04-27 WO PCT/JP2010/057441 patent/WO2010131569A1/ja active Application Filing
- 2010-04-27 US US13/320,243 patent/US20120056201A1/en not_active Abandoned
- 2010-04-27 TW TW099113383A patent/TW201101482A/zh unknown
- 2010-04-27 EP EP10774831A patent/EP2432022A1/en not_active Withdrawn
- 2010-04-27 TW TW099113381A patent/TW201101484A/zh unknown
- 2010-04-27 JP JP2011513304A patent/JPWO2010131573A1/ja not_active Withdrawn
- 2010-04-27 CN CN2010800205181A patent/CN102422387A/zh active Pending
- 2010-04-27 US US13/320,247 patent/US20120056202A1/en not_active Abandoned
- 2010-04-27 KR KR1020117028635A patent/KR20120014017A/ko not_active Application Discontinuation
- 2010-04-27 US US13/062,057 patent/US8168515B2/en not_active Expired - Fee Related
- 2010-04-27 WO PCT/JP2010/057439 patent/WO2010131568A1/ja active Application Filing
- 2010-04-27 CA CA2735975A patent/CA2735975A1/en not_active Abandoned
- 2010-04-27 JP JP2011513303A patent/JPWO2010131572A1/ja not_active Withdrawn
- 2010-04-27 TW TW099113380A patent/TW201120939A/zh unknown
- 2010-04-27 EP EP10774827A patent/EP2432001A4/en not_active Ceased
- 2010-04-27 JP JP2011513299A patent/JPWO2010131568A1/ja active Pending
- 2010-04-27 KR KR1020117028915A patent/KR20120014024A/ko not_active Application Discontinuation
- 2010-04-27 EP EP10774828A patent/EP2432002A4/en not_active Withdrawn
- 2010-04-27 CA CA2761246A patent/CA2761246A1/en not_active Abandoned
- 2010-04-27 KR KR1020117028517A patent/KR20120011059A/ko not_active Application Discontinuation
- 2010-04-27 CN CN2010800205196A patent/CN102422388A/zh active Pending
- 2010-04-27 KR KR1020117028245A patent/KR20120023710A/ko not_active Application Discontinuation
- 2010-04-27 CN CN2010800205020A patent/CN102422424A/zh active Pending
- 2010-04-27 EP EP10774826A patent/EP2432000A4/en not_active Withdrawn
- 2010-04-27 WO PCT/JP2010/057445 patent/WO2010131573A1/ja active Application Filing
- 2010-04-27 TW TW099113382A patent/TW201104861A/zh unknown
- 2010-04-27 US US13/319,560 patent/US20120061686A1/en not_active Abandoned
- 2010-04-27 CA CA2761428A patent/CA2761428A1/en not_active Abandoned
- 2010-04-27 JP JP2011513300A patent/JP5477380B2/ja not_active Expired - Fee Related
- 2010-04-27 CN CN2010800026675A patent/CN102160143B/zh not_active Expired - Fee Related
- 2010-04-27 KR KR1020117005798A patent/KR20120024526A/ko not_active Application Discontinuation
- 2010-04-27 CN CN2010800206964A patent/CN102422425A/zh active Pending
- 2010-04-27 WO PCT/JP2010/057442 patent/WO2010131570A1/ja active Application Filing
- 2010-04-27 US US13/319,599 patent/US20120061687A1/en not_active Abandoned
- 2010-04-27 CA CA2761245A patent/CA2761245A1/en not_active Abandoned
- 2010-04-27 WO PCT/JP2010/057444 patent/WO2010131572A1/ja active Application Filing
- 2010-04-27 EP EP10774830.3A patent/EP2432020A4/en not_active Withdrawn
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000277405A (ja) * | 1999-03-29 | 2000-10-06 | Meidensha Corp | 半導体素子の製造方法 |
WO2001018872A1 (fr) * | 1999-09-07 | 2001-03-15 | Sixon Inc. | TRANCHE DE SiC, DISPOSITIF A SEMI-CONDUCTEUR DE SiC, ET PROCEDE DE PRODUCTION D'UNE TRANCHE DE SiC |
JP2002280531A (ja) * | 2001-03-19 | 2002-09-27 | Denso Corp | 半導体基板及びその製造方法 |
JP2003224042A (ja) * | 2001-12-21 | 2003-08-08 | Soi Tec Silicon On Insulator Technologies | 半導体薄層の移し換え方法とそれに使用するドナーウエハの製造方法 |
WO2006114999A1 (ja) * | 2005-04-18 | 2006-11-02 | Kyoto University | 化合物半導体装置及び化合物半導体製造方法 |
JP2008235776A (ja) * | 2007-03-23 | 2008-10-02 | Sumco Corp | 貼り合わせウェーハの製造方法 |
JP2009117533A (ja) * | 2007-11-05 | 2009-05-28 | Shin Etsu Chem Co Ltd | 炭化珪素基板の製造方法 |
Non-Patent Citations (2)
Title |
---|
M. NAKABAYASHI ET AL.: "Growth of Crack-free 100 mm-diameter 4H-SiC Crystals with Low Micropipe Densities", MATER. SCI. FORUM, vol. 600-603, 2009, pages 3 - 6 |
See also references of EP2432000A4 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8168515B2 (en) | 2009-05-11 | 2012-05-01 | Sumitomo Electric Industries, Ltd. | Method for manufacturing semiconductor substrate |
WO2012127748A1 (ja) * | 2011-03-22 | 2012-09-27 | 住友電気工業株式会社 | 炭化珪素基板 |
CN102869816A (zh) * | 2011-03-22 | 2013-01-09 | 住友电气工业株式会社 | 碳化硅衬底 |
WO2012132594A1 (ja) * | 2011-03-25 | 2012-10-04 | 住友電気工業株式会社 | 炭化珪素基板 |
JP2017081813A (ja) * | 2011-08-05 | 2017-05-18 | 住友電気工業株式会社 | 基板、半導体装置およびこれらの製造方法 |
JP2023501646A (ja) * | 2019-11-14 | 2023-01-18 | ファーウェイ デジタル パワー テクノロジーズ カンパニー リミテッド | 半導体基板、その製造方法、及び半導体装置 |
JP7416935B2 (ja) | 2019-11-14 | 2024-01-17 | ファーウェイ デジタル パワー テクノロジーズ カンパニー リミテッド | 半導体基板、その製造方法、及び半導体装置 |
Also Published As
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2010131568A1 (ja) | 炭化珪素基板、半導体装置および炭化珪素基板の製造方法 | |
WO2011046021A1 (ja) | 炭化珪素基板の製造方法および炭化珪素基板 | |
JP2011243770A (ja) | 炭化珪素基板、半導体装置、炭化珪素基板の製造方法 | |
WO2011142158A1 (ja) | 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置 | |
WO2011096109A1 (ja) | 炭化珪素基板の製造方法 | |
JP5928335B2 (ja) | 炭化珪素基板の製造方法および半導体装置の製造方法 | |
JPWO2011052320A1 (ja) | 炭化珪素基板の製造方法および炭化珪素基板 | |
WO2010131571A1 (ja) | 半導体装置 | |
WO2011092893A1 (ja) | 炭化珪素基板の製造方法 | |
WO2011077797A1 (ja) | 炭化珪素基板 | |
JP2011243618A (ja) | 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置 | |
WO2011152089A1 (ja) | 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置 | |
JP2011243617A (ja) | 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置 | |
WO2011086734A1 (ja) | 炭化珪素基板の製造方法 | |
JP2011086660A (ja) | 炭化珪素基板の製造方法および炭化珪素基板 | |
JP2011243640A (ja) | 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201080020518.1 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10774826 Country of ref document: EP Kind code of ref document: A1 |
|
DPE1 | Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101) | ||
ENP | Entry into the national phase |
Ref document number: 2011513299 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2761428 Country of ref document: CA |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13319560 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 20117028635 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2010774826 Country of ref document: EP |