JP6883745B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6883745B2 JP6883745B2 JP2017058779A JP2017058779A JP6883745B2 JP 6883745 B2 JP6883745 B2 JP 6883745B2 JP 2017058779 A JP2017058779 A JP 2017058779A JP 2017058779 A JP2017058779 A JP 2017058779A JP 6883745 B2 JP6883745 B2 JP 6883745B2
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- 239000004065 semiconductor Substances 0.000 title claims description 183
- 238000004519 manufacturing process Methods 0.000 title claims description 41
- 230000007547 defect Effects 0.000 claims description 130
- 230000001629 suppression Effects 0.000 claims description 78
- 238000000034 method Methods 0.000 claims description 72
- 239000000758 substrate Substances 0.000 claims description 57
- 239000013078 crystal Substances 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 212
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 16
- 229910010271 silicon carbide Inorganic materials 0.000 description 16
- 238000007689 inspection Methods 0.000 description 11
- 230000005856 abnormality Effects 0.000 description 7
- 230000007423 decrease Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000005424 photoluminescence Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 244000000626 Daucus carota Species 0.000 description 2
- 235000002767 Daucus carota Nutrition 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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Description
本開示の実施形態を説明する前に、本開示の基礎となった知見を説明する。パワーデバイスにおいて数百A級の大電流を実現するために、エピタキシャル成長に用いられる半導体ウエハ(エピウエハ)から取り出される半導体チップは、数cm角の面積を有することが望まれる。しかし、大面積のパワーデバイスの歩留まりを確保することは容易ではない。
[項目1]
半導体基板と、
前記半導体の表面に位置するドリフト層と、
前記ドリフト層の表面の、空乏抑制領域を除く領域において位置しており、前記ドリフト層とオーミック接合またはショットキー接合している第1電極と、
前記半導体基板の裏面とオーミック接合している第2電極と、
を備え、
前記ドリフト層の厚さはtであり、前記空乏抑制領域は、半径がt以上の円または扇形の領域を含む、半導体装置。
[項目2]
前記ドリフト層の前記表面に平行な平面視において、前記空乏抑制領域内の前記ドリフト層および前記基板の少なくとも一方に結晶欠陥および/またはプロセス欠陥を有し、
前記平面視において、前記結晶欠陥および/または前記プロセス欠陥から、前記空乏抑制領域の外縁までの距離はt以上である、項目1に記載の半導体装置。
[項目3]
前記結晶欠陥はマイクロパイプまたはエピタキシャル欠陥である項目1に記載の半導体装置。
[項目4]
前記第1電極は前記ドリフト層とショットキー接合しており、前記半導体装置はショットキーバリアダイオードである、項目1から3のいずれかに記載の半導体装置。
[項目5]
前記ドリフト層は、前記第1主面を含む表面部分に複数のウェル領域を有し、前記複数のウェル領域のそれぞれは、ソース領域を含み、
前記ドリフト層の前記第2主面上に位置し、前記複数のウェル領域のソース領域の少なくとも一部を露出するゲート絶縁層と、
前記空乏抑制領域外において、前記ゲート絶縁層の上に形成され、前記空乏抑制領域内において、前記ゲート絶縁層の上に形成されないゲート電極と、
前記空乏抑制領域外において、前記ゲート電極を覆い、前記空乏抑制領域内において、前記ゲート絶縁層の少なくとも一部を覆う絶縁層と、
を備え、前記第1電極は、前記空乏抑制領域外において前記絶縁層を覆う、項目1から3のいずれかに記載の半導体装置。
[項目6]
ドリフト層を有する半導体基板を用意する工程(a)と、
前記ドリフト層および前記半導体基板の結晶欠陥および/またはプロセス欠陥の少なくとも一方を検査し、前記結晶欠陥および/またはプロセス欠陥の座標を取得し、前記座標に基づいて、空乏抑制領域を決定する工程(b)と、
前記ドリフト層の表面の前記空乏抑制領域を除く領域において、前記ドリフト層とオーミック接合またはショットキー接合する第1電極を形成する工程(c)と、
を包含し、
前記ドリフト層の厚さはtであり、前記空乏抑制領域は、半径がt以上の円または扇形の領域を含む、半導体装置の製造方法。
[項目7]
平面視において、前記結晶欠陥または前記プロセス欠陥の座標位置から、前記空乏抑制領域の外縁までの距離はt以上である、項目6に記載の半導体装置の製造方法。
[項目8]
前記結晶欠陥はマイクロパイプまたはエピタキシャル欠陥である項目7に記載の半導体装置の製造方法。
[項目9]
前記第1電極は前記ドリフト層とショットキー接合しており、前記半導体装置はショットキーバリアダイオードである、項目7から9のいずれかに記載の半導体装置の製造方法。
[項目10]
前記工程(a)において、前記ドリフト層は、前記第1主面を含む表面部分に複数のウェル領域を有し、前記複数のウェル領域のそれぞれは、ソース領域を含み、
前記工程(b)と前記工程(c)との間に、
前記ドリフト層の前記表面に位置し、前記複数のウェル領域のソース領域の少なくとも一部を露出するゲート絶縁層を形成する工程と、
前記空乏抑制領域外において、前記ゲート絶縁層の上に位置し、前記空乏抑制領域内において、前記ゲート絶縁層の上に位置しないゲート電極を形成する工程と、
前記空乏抑制領域域外において、前記ゲート電極を覆い、前記空乏抑制領域内において、前記ゲート絶縁層の少なくとも一部を覆う絶縁層を形成する工程と、
を備え、
前記工程(c)は、前記空乏抑制領域において前記絶縁層を覆わず、前記空乏抑制領域外で前記絶縁層を覆う、項目7から9のいずれかに記載の半導体装置の製造方法。
図1Aは本実施形態の半導体装置101の平面図であり、図1Bは、半導体装置101の断面図である。本実施形態では、半導体装置101は、ショットキーバリアダイオードである。半導体装置101は、半導体基板10と、ドリフト層20と、第1電極50と、第2電極60とを備えている。
図5Aは本実施形態の半導体装置102の平面図であり、図5Bは、半導体装置102の空乏抑制領域20c近傍の拡大断面図である。本実施形態では、半導体装置102は、パワーMOSFET(Metal Oxide Semiconductor Field Effect Transistor)である。半導体装置102は、半導体基板10と、ドリフト層20と、第1電極50と、第2電極60とを備えている。半導体装置102と第1の実施形態の半導体装置101とは半導体装置の機能が異なっているが、半導体基板10およびドリフト層20の欠陥30によるリーク電流を抑制する構成は類似している。このため、第1の実施形態と同様の構造については説明を省略する場合がある。
10a 上面
10b 下面
20 ドリフト層
20a 上面
20c 空乏抑制領域
20d 空乏層
21 ガードリング
23 ウェル領域
23c 空乏抑制領域
24 ソース領域
25 コンタクト領域
30 欠陥
31 ゲート絶縁層
32 ゲート電極
32’ ゲート電極
40、40’ 絶縁層
40c コンタクトホール
42 マスク層
42c 開口パターン
43 レジストパターン
50、50’ 第1電極
51 レジスト層
51c 開口
55 ゲート配線
60 第2電極
71 レジスト層
71c、72c、74c 開口
72、73、74 レジスト層
101、102 半導体装置
102u ユニットセル
Claims (8)
- 半導体基板と、
前記半導体基板の上面に位置するドリフト層と、
前記ドリフト層の上面の、空乏抑制領域を除く領域において位置しており、前記ドリフト層とオーミック接合またはショットキー接合している第1電極と、
前記半導体基板の裏面とオーミック接合している第2電極と、
を備え、
前記ドリフト層の前記上面に平行な平面視において、前記空乏抑制領域内の前記ドリフト層および前記半導体基板の少なくとも一方に結晶欠陥および/またはプロセス欠陥が存在し、
前記ドリフト層の厚さはtであり、前記空乏抑制領域は、半径がt以上の円または扇形の領域を含み、
前記平面視において、前記結晶欠陥および/または前記プロセス欠陥から、前記空乏抑制領域の外縁までの距離はt以上である、半導体装置。 - 前記結晶欠陥はマイクロパイプまたはエピタキシャル欠陥である請求項1に記載の半導体装置。
- 前記第1電極は前記ドリフト層とショットキー接合しており、前記半導体装置はショットキーバリアダイオードである、請求項1または2に記載の半導体装置。
- 前記ドリフト層は、前記ドリフト層の前記上面を含む表面部分に複数のウェル領域を有し、前記複数のウェル領域のそれぞれは、ソース領域を含み、
前記ドリフト層の前記上面上に位置し、前記複数のウェル領域のソース領域の少なくとも一部を露出するゲート絶縁層と、
前記空乏抑制領域外において、前記ゲート絶縁層の上に形成され、前記空乏抑制領域内において、前記ゲート絶縁層の上に形成されないゲート電極と、
前記空乏抑制領域外において、前記ゲート電極を覆い、前記空乏抑制領域内において、前記ゲート絶縁層の少なくとも一部を覆う絶縁層と、
を備え、前記第1電極は、前記空乏抑制領域外において前記絶縁層を覆う、請求項1または2に記載の半導体装置。 - 厚さがtのドリフト層を有する半導体基板を用意する工程(a)と、
前記ドリフト層および前記半導体基板の結晶欠陥および/またはプロセス欠陥の少なくとも一方を検査し、前記結晶欠陥および/またはプロセス欠陥の座標を取得し、前記結晶欠陥および/またはプロセス欠陥の座標の位置から前記t以上の距離に外縁を有する空乏抑制領域であって、半径が前記t以上の円または扇形の領域を含む空乏抑制領域を決定する工程(b)と、
前記ドリフト層の上面の前記空乏抑制領域を除く領域において、前記ドリフト層とオーミック接合またはショットキー接合する第1電極を形成する工程(c)と、
を包含する、半導体装置の製造方法。 - 前記結晶欠陥はマイクロパイプまたはエピタキシャル欠陥である請求項5に記載の半導体装置の製造方法。
- 前記第1電極は前記ドリフト層とショットキー接合しており、前記半導体装置はショットキーバリアダイオードである、請求項5または6に記載の半導体装置の製造方法。
- 前記工程(a)において、前記ドリフト層は、前記ドリフト層の前記上面を含む表面部分に複数のウェル領域を有し、前記複数のウェル領域のそれぞれは、ソース領域を含み、
前記工程(b)と前記工程(c)との間に、
前記ドリフト層の前記上面に位置し、前記複数のウェル領域のソース領域の少なくとも一部を露出するゲート絶縁層を形成する工程と、
前記空乏抑制領域外において、前記ゲート絶縁層の上に位置し、前記空乏抑制領域内において、前記ゲート絶縁層の上に位置しないゲート電極を形成する工程と、
前記空乏抑制領域域外において、前記ゲート電極を覆い、前記空乏抑制領域内において、前記ゲート絶縁層の少なくとも一部を覆う絶縁層を形成する工程と、
を備え、
前記工程(c)において、前記第1電極は、前記空乏抑制領域において前記絶縁層を覆わず、前記第1電極は、前記空乏抑制領域外で前記絶縁層を覆う、請求項5から7のいずれかに記載の半導体装置の製造方法。
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