TWI398903B - 線路元件製程及其結構 - Google Patents

線路元件製程及其結構 Download PDF

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Publication number
TWI398903B
TWI398903B TW097146146A TW97146146A TWI398903B TW I398903 B TWI398903 B TW I398903B TW 097146146 A TW097146146 A TW 097146146A TW 97146146 A TW97146146 A TW 97146146A TW I398903 B TWI398903 B TW I398903B
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Taiwan
Prior art keywords
layer
metal
circuit component
circuit
pillar
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TW097146146A
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English (en)
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TW200947509A (en
Inventor
Mou Shiung Lin
Chien Kang Chou
Ke Hung Chen
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Megica Corp
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Publication of TW200947509A publication Critical patent/TW200947509A/zh
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Publication of TWI398903B publication Critical patent/TWI398903B/zh

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Description

線路元件製程及其結構
本發明係有關一種線路元件結構製程及其結構，特別是有關一種能有效改善積體電路的性能的線路元件之製程及其結構。
半導體晶圓片係可用以製造出持續增加密度且縮小幾何特徵圖案的積體電路，藉由多層的導電層與絕緣層的結構可分別提供位於不同層上的半導體元件之間的內部連接與隔絕的效果，例如：主動與被動元件，像是薄膜電晶體、互補金氧半導體、電容、電感器、電阻...等等的大型積體電路中，在不同層狀結構與半導體元件之間係需要增加多個電性連接部，且同時，對於組合式的積體電路晶片而言，亦需要增加大量的導線，這些導線係穿越出積體電路晶片中的保護層並裸露在外，而最後則是終止在輸入輸出接墊上，此導線係用來與晶片封裝的外部接觸結構進行連接。
晶圓級封裝，即為所謂的以晶圓級的方式封裝一積體電路晶片的技術，而非傳統的在將晶圓片先切割後而在進行單一單元的封裝製程，因此，在將晶圓片切割為單一單元以供組裝為最終的晶片承載封裝之前，例如：在進行球柵陣列封裝之前，晶圓級封裝即可將晶圓片製造、封裝、測試與晶圓級預燒進行整合，其優點包含：藉由縮小所佔 之體積與厚度以獲得較小的尺寸、較輕的重量、相對簡化的組裝製程、較低的整體生產成本以及在電性上可獲得有較佳的表現，且晶圓級封裝係簡化了一個元件自矽材料開始至運送到客戶的手中的流程，可使積體電路晶片封裝的產量提昇且成本降低，惟，其係導致在製造能力與結構可靠度方面，面臨到相當大的挑戰。
晶圓級封裝基本上係可擴張涵蓋到晶圓製程中的元件連接製程與元件保護製程，在晶圓級封裝的第一步驟中，其係藉由半導體積體電路中的重配置線路技術後護層，以加大標準的接墊間距，因此，較低成本的模板印刷銲錫或是定位式的銲錫係可實現。針對重配置線路技術的揭露，舉例來說，在美國專利案號第6,645,136號、第6,784,087號與第6,818,545號中的申請人，皆與本發明之申請人相同，而正如本專利所揭露的，一重配置線路層係與半導體結構中的輸入輸出接墊連接，此重配置線路層係形成在後護層上的聚合物層或彈性材質層上，而一柱狀的接觸窗係利用光罩製程以形成在此重配置線路層上，此反應後形成的柱狀接觸窗的側面方向上係為獨立而未有任支撐的，並且藉由覆晶組裝技術，上述之反應後所形成的結構體則更可進一步組裝至一晶片承載封裝結構上。縱使當此後護層結構與其所對應之製程係可在積體電路封裝中提供解決改善間距的方法，然而，在持續增加集成規模要求下的積體電路中，勢必將面對到更為嚴苛的細間隙標準要求，而針對此點，則必定會遭遇到相當的限制，且對於因應力誘導 而產生的損壞而言，係亦為一種潛在的風險。
美國專利案號第6,103,552係揭露另一種包含有重配置線路層的後護結構的晶圓級封裝製程，此重配置線路層係形成在後護層上的聚合物層上，而在重配置線路層上則是覆蓋有另一聚合物層，且此聚合物層係經過蝕刻或是鑽孔以形成微通孔，並填充金屬以穿透微通孔的孔隙而形成內連接，也就是所謂的導電柱體，而上聚合物層與下聚合物層係藉由一鉻－銅層以隔離而不與重配置線路層接觸，一貼附在上述之導電柱體突出尾端的錫鉛凸塊係由無電鍍、網板印刷或是模板印刷；由於導電柱體係延伸至聚合物層外，除此之外，上述結構的頂表面並不平滑，因此，在高解析度的微影成像無法達成前提下，導電柱體形成微通孔、以電鍍形成錫鉛凸塊皆無法達成，最終，積體電路封裝中的接觸窗間距係將受到限制，且此限制係隨著聚合物層厚度的增加而變得更為顯著，然而，隨遮聚合物層厚度的增加係可以提供較令人滿意的應力釋放，關於此將於以下詳述。再者，承上所述，下聚合物層係與上聚合物層隔離，因此，下聚合物層將無法單獨提供較佳的應力釋放，且，若當下聚合物層之厚度係製作得較為薄以降低重配置線路層的側向位移，則會導致應力釋放變得較差，所引起的問題將於以下進行討論。
結構可靠度中的其中一種挑戰係為提供足夠的應力釋放，以供給上述晶圓級封裝製程後形成的多層結構，其係包含半導體積體電路晶粒與額外的後護結構，舉例說明， 結合在保護層上的薄膜係受到雙軸向應力所影響，且此應力係為由熱所誘導而產生的。在式(1)中係表示出在後護層的薄膜中之雙軸向熱應力的數學理論模擬方程式，其係提供接合在積體電路晶片中矽基材上的結構的多種物理參數： 其中，σ ppt ＝σ x ＝σ y ，後護層薄膜中之雙軸應力；R＝矽基板受熱彎曲的曲率半徑；Ys＝矽基板的楊氏係數(Young’s modulus)；vsi＝矽基板的蒲松比(Poisson’s ratio)；xSi＝矽基板的厚度；以及xppt＝後護層薄膜的厚度。
基於上述的方程式可知，除了增加矽基板的蒲松比外，係有兩種方式可用以降低雙軸向應力，(a)降低xSi，其係表示必須將矽基板置在得更薄，或是(b)提高xppt，其係表示必須增加後護薄膜結構的厚度。
第一圖係揭示出一習知的後護層結構10，其係包含一重配置線路層12與一應力釋放聚合物層14，此應力釋放聚合物層14亦可稱為應力緩衝層，且係形成在半導體積體電路晶片18頂表面的一保護層16上，其中，聚合物層14係可由彈性材料、環氧樹脂、低介電係數材料或是其他聚 合物材料以構成，具有彈性的材料主要是用以提供此接合結構可具備足夠的機械彈性，且誠如上述的式(1)中所推論的結果，當積體電路晶片18上覆蓋有聚合物層14時，此積體電路積片18與形成於其上的結構所產生的應力皆可被吸收或是緩衝，以降低積體電路晶片18發生局部的損壞，而尤其是對於精細繁複的積體電路晶片18的電路而言，後護結構10的可靠度可因此獲得提昇。再，依據式(1)中所提出的關係式可知，緩衝效應的表現將隨著聚合物層14厚度的增加而變得更好。
然而在應用厚聚合物層14時，通常會面臨到一個問題。如第一圖中所示的重配置線路層12係通常由銅所構成，且其係用以將位在積體電路晶片18上的輸入輸出接墊20連接至外部電路。當接墊20的最頂端上同時或分別形成有錫鉛凸塊或銅導電柱體時，重配置線路層12係可與下一層的封裝結構連結得相當緊密，其中的封裝結構係可為一晶片承載，因此，重配置線路層12係藉由聚合物層14所定義出的具有一定斜度的斜坡22，以將此重配置線路層12自像是形成有輸入輸出接墊20的一個較低的積體電路平面，逐漸上升至一較高的積體電路平面，例如：聚合物層14的頂部，此斜坡22的斜度係由金屬化步驟以覆蓋在厚聚合物層14的開口上所決定。在實際的應用上，斜坡22的斜度係會隨著每一個聚合物層14開口的不同而改變，而每一個開口則是決定於實際的製程條件與聚合物本身根本的物理性質與特性，例如：與材料表面能量有關的 濕潤接觸角；舉例說明，在許多的狀況下，在積體電路保護層16上聚合物層14的斜坡22係具有約為45度的斜度，因此，重配置線路層12必須藉由一定量的側向位移以延伸自積體電路中的接墊20至厚聚合物層14的頂端，故，此側向位移迫使得在重配置線路層12的佈局上必需允許一定量的容許值，最終，由於此允許的容許值必須要能夠提供具有不同開口的聚合物層14所形成各種的斜坡22斜率、各個重配置線路層所具有不同的側向位移，使得相鄰的接觸窗結構之間的間距將受到限制，其中，接觸窗可共同或分別由錫鉛凸塊、銅柱所定義，且接觸窗結構與保護層上的開口之間的間距亦隨之增加，因此，此結果係造成後護結構與下一層的封裝結構之間，無法具有微小的結構間距；相反地，如果厚聚合物層並未被採用時，將造成應力緩衝不足而導致精細的積體電路晶片中的電路因受到應力誘導而發生損壞，且對於大的導電柱體而言，由於其側向支撐力不足而使得輸入輸出結構間距將受到限制，然而，大的導電柱體結構係為必須的，因為其係可以提供充足的距離以降低輸入輸出接墊20與積體電路晶片18中的電性電路之間所產生的耦合電容。
上述所提出的議題係針對可實現於後護層結構上的接觸窗結構之間的間距縮減而導致的問題，也因為如此，亦使得積體電路中的集成規模的提昇受到阻礙。
有鑑於此，欲提出一種晶圓級封裝結構及其相對應之製程方法，以同時改善應力釋放、達到接觸窗結構間距的 微小化。
本發明之主要目的係提供一種線路元件結構製程及其結構，其係可提供應力的釋放與微小化的接觸窗結構之間之間距，依據本發明，其間距係小於250微米，且可達成針孔數目少於400個的目標。
本發明之另一目的係提供一種線路元件結構製程及其結構，其係包含一重配置線路(RDL)支撐的後護層結構，其係在保護層上形成一相對厚度較為薄的支撐層，如：聚合物層，以用來支撐重配置線路結構之間的細間隙，且亦具有一相對厚度較為厚的支撐層，如：聚合物層，以使得位在相鄰層狀封裝結構之間的重配置線路結構之間的細間隙可獲得支撐。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底、位在該半導體基底上之一金屬層、及位在該半導體基底上及該金屬層上之一第一聚合物層；研磨該第一聚合物層；形成一第二聚合物層在該第一聚合物層上，位在該第二聚合物層內之一開口暴露出該金屬層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底及位在該半導體基底上之一金屬柱，其中該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20 微米至300微米之間；形成一第一絕緣層在該半導體基底上，且包覆該金屬柱；形成一第二絕緣層在該第一絕緣層上，位在該第二絕緣層內之一開口暴露出該第一金屬柱。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體晶圓、位在該半導體晶圓上之一第一金屬層、及位在該半導體晶圓上及該第一金屬層上之一聚合物層，其中該半導體晶圓包括多數電晶體，形成該些多數電晶體包括摻雜三架或五架離子至該半導體晶圓；研磨該聚合物層；形成一第二金屬層在該聚合物層上及該第一金屬層上；形成一圖案定義層在該第二金屬層上，位在該圖案定義層內之一開口暴露出該第二金屬層；形成一第三金屬層在該口所暴露出的該第二金屬層上；去除該圖案定義層；去除未在該第三金屬層下的該第二金屬層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體晶圓及位在該半導體晶圓上之一金屬柱，其中該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間，其中該半導體晶圓包括多數電晶體，其中該半導體晶圓包括多數電晶體，形成該些多數電晶體包括摻雜三架或五架離子至該半導體晶圓；形成一絕緣層在該半導體晶圓上，且包覆該金屬柱；形成一第一金屬層在該絕緣層上及該金屬柱上；形成一圖案定義層在該第一金屬層上，位在該圖案定義層內之一開口暴露出該第 一金屬層；形成一第二金屬層在該口所暴露出的該第一金屬層上；去除該圖案定義層；去除未在該第二金屬層下的該第一金屬層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底、位在該半導體基底上之一第一金屬層、及位在該半導體基底上及該第一金屬層上之一聚合物層；研磨該聚合物層；形成一凸塊在該第一金屬層上，其中該形成該凸塊包括：形成一第二金屬層在該聚合物層上及該第一金屬層上；形成一圖案定義層在該第二金屬層上，位在該圖案定義層內之一開口暴露出該第二金屬層；形成一第三金屬層在該口所暴露出的該第二金屬層上；去除該圖案定義層；去除未在該第三金屬層下的該第二金屬層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底及位在該半導體基底上之一金屬柱，其中該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；形成一絕緣層在該半導體基底上，且包覆該金屬柱；形成一開口在該絕緣層內，暴露出該金屬柱。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底、位在該半導體基底上之一金屬層、及位在該半導體基底上及該金屬層上之一聚合物層；磨該聚合物層；形成一開口在該聚合物層內， 暴露出該金屬層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底及位在該半導體基底上之一金屬柱，其中該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；形成一絕緣層在該半導體基底上，且包覆該金屬柱；蝕刻該絕緣層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底、位在該半導體基底上之一金屬柱、及位在該半導體基底上及該金屬柱上之一聚合物層；去除該聚合物層使暴露出該金屬柱的一頂面，且該頂面到該聚合物層之間的高度差介於10微米到150微米。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底、位在該半導體基底上之一金屬層、及位在該半導體基底上及該金屬層上之一聚合物層；研磨該聚合物層；蝕刻該聚合物層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供提供一半導體基底；形成一聚合物層在該半導體基底上，在該聚合物層內之一開口的深度係介於10微米到300微米之間；形成一金屬層在該聚合物層上及該開口內；去除位在該開口外的該金屬層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底及位在該半導體基 底上之一金屬柱，其中該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；形成一絕緣層在該半導體基底上，且包覆該金屬柱；形成一凸塊在該金屬柱上；連接該凸塊至一外界電路；形成一第二絕緣層在該半導體基底與該外界電路之間。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底、位在該半導體基底上之一金屬層、及位在該半導體基底上及該金屬層上之一第一聚合物層；研磨該第一聚合物層；形成一凸塊在該金屬層；連接該凸塊至一外界電路；形成一第二聚合物層在該半導體基底與該外界電路之間。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底、位在該半導體基底上之一金屬層、及位在該半導體基底上及該金屬層上之一聚合物層；研磨該聚合物層；形成一凸塊在該金屬層上，其中該形成該凸塊包括一電鍍製程。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底及位在該半導體基底上之一金屬柱，其中該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；形成一絕緣層在該半導體基底上，且包覆該金屬柱；形成一凸塊在該金屬柱上，其中該形成該凸塊包括一電鍍製程。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底、位在該半導體基底上之一金屬層、及位在該半導體基底上及該金屬層上之一聚合物層；研磨該聚合物層；利用一打線製程形成一導線連接在該金屬層上。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其製程係提供一半導體基底及位在該半導體基底上之一金屬柱，其中該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；形成一絕緣層在該半導體基底上，且包覆該金屬柱；利用一打線製程形成一導線連接在該金屬柱上。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一基板；一第一金屬柱，位在該基板上，該第一金屬柱的最大橫向尺寸除以該第一金屬柱的高度之比值係小於4，且該第一金屬柱的高度係介於20微米至300微米之間；一第二金屬柱，位在該基板上，該第二金屬柱的最大橫向尺寸除以該第二金屬柱的高度之比值係小於4，且該第二金屬柱的高度係介於20微米至300微米之間，該第一金屬柱之中心點至該第二金屬柱之中心點之間的距離係介於10微米至250微米之間。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一第一金屬柱，位在該半導體基底上，該第一金屬柱的最大橫向尺寸除以 該第一金屬柱的高度之比值係小於4，且該第一金屬柱的高度係介於20微米至300微米之間；一第二金屬柱，位在該半導體基底上，該第二金屬柱的最大橫向尺寸除以該第二金屬柱的高度之比值係小於4，且該第二金屬柱的高度係介於20微米至300微米之間；一絕緣層，位在該半導體基底上且包覆該第一及第二金屬柱；一第一凸塊，位在該第一金屬柱上；一第二凸塊，位在該第二金屬柱上，其中該第一凸塊之中心點至該第二凸塊之中心點之間的距離係介於10微米至250微米之間。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一種一半導體基底；一第一金屬柱，位在該半導體基底上，該第一金屬柱的最大橫向尺寸除以該第一金屬柱的高度之比值係小於4，且該第一金屬柱的高度係介於20微米至300微米之間；一第二金屬柱，位在該半導體基底上，該第二金屬柱的最大橫向尺寸除以該第二金屬柱的高度之比值係小於4，且該第二金屬柱的高度係介於20微米至300微米之間；一金屬線路，連接該第一金屬柱的頂面及該第二金屬柱的頂面，其中該金屬線路的材質包括金。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一第一金屬柱，位在該半導體基底上，該第一金屬柱的最大橫向尺寸除以該第一金屬柱的高度之比值係小於4，且該第一金屬柱的高度係介於20微米至300微米之間；一第二金屬柱，位在 該半導體基底上，該第二金屬柱的最大橫向尺寸除以該第二金屬柱的高度之比值係小於4，且該第二金屬柱的高度係介於20微米至300微米之間；一金屬線路，連接該第一金屬柱的頂面及該第二金屬柱的頂面；一聚合物層，位在該金屬線路上。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一金屬柱，位在該半導體基底上，該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間，其中利用打線製程適於形成一導線連接在該金屬柱上。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一金屬柱，位在該半導體基底上，該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；一聚合物層，位在該半導體基底上，且包覆該金屬柱，其中高度介於10微米至150微米之一凸塊適於形成在該金屬柱上。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一金屬柱，位在該半導體基底上，該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；一聚合物層，位該半導體基底上，且包覆該金屬柱；一金屬線圈，位在該聚合物層上，該金屬線 圈的厚度係介於1微米至15微米之間。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一金屬柱，位在該半導體基底上，該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；一凸塊，位在該金屬柱上，其中該凸塊包括厚度介於10微米到30微米之一金層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一金屬柱，位在該半導體基底上，該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；一凸塊，位在該金屬柱上，其中該凸塊包括含鈦之一金屬層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一金屬柱，位在該半導體基底上，該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；一凸塊，位在該金屬柱上，其中該凸塊包括含鉻之一金屬層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一金屬柱，位在該半導體基底上，該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；一凸塊，位在該金屬柱上，其中該凸塊 包括含鉭之一金屬層。
為了本發明上述之目的，提出一種線路元件結構製程及其結構，其係包括提供一半導體基底；一金屬柱，位在該半導體基底上，該金屬柱的最大橫向尺寸除以該金屬柱的高度之比值係小於4，且該金屬柱的高度係介於20微米至300微米之間；一第一聚合物層，位在該半導體基底上，且包覆該金屬柱；一基板；一凸塊，位在該金屬柱與該基板之間；一第二聚合物層，位在該基板與該半導體基底之間，且包覆該凸塊。
底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
本發明係為線路元件結構製程及其結構，藉由在半導體基底上形成多數金屬柱(Post)結構，並且使相鄰金屬柱之間距縮小至250微米以下，以下就數種不同實施例予以說明：
第一實施例：
第一種實施例的線路元件結構製程，請參閱第二圖所 示，首先提供一半導體基底30，此半導體基底30之形式比如是矽基底、砷化鎵基底(GAAS)、矽化鍺基底、具有磊晶矽在絕緣層上(silicon－on－insulator，SOI)之基底，半導體基底30在此實施例中係為圓形之一半導體晶圓，且此半導體基底30具有一主動表面，在半導體基底30的主動表面透過摻雜五價或三價的離子(例如硼離子或磷離子等)形成多個電子元件32，此電子元件32例如是金屬氧化物半導體或電晶體，金氧半導體元件(MOS devices)，P通道金氧半導體元件(p－channel MOS devices)，n通道金氧半導體元件(n－channel MOS devices)，雙載子互補式金氧半導體元件(BiCMOS devices)，雙載子連接電晶體(Bipolar Junction Transistor,BJT)，擴散區(Diffusion area)，電阻元件(resistor)，電容元件(capacitor)及互補金屬氧化半導體(CMOS)等。
請參閱第三圖所示，在半導體基底30的主動表面上形成一細連線結構34，此細連線結構34係由複數厚度小於3微米之薄膜絕緣層36及厚度小於3微米之細線路層38所構成，其中細線路層38係選自銅金屬材質或鋁金屬材質，而薄膜絕緣層36又稱為介電層，一般是利用化學氣相沉積的方式所形成。此薄膜絕緣層36比如為氧化矽、化學氣相沈積之四乙氧基矽烷(TEOS)氧化物、SiwCxOyHz、氮矽化合物或氮氧矽化合物，或是以旋塗方式形成之玻璃(SOG)、氟化玻璃(FSG)、絲印層(SiLK)、黑鑽石薄膜(Black Diamond)、聚芳基酯(polyarylene ether)、聚苯噁唑 (polybenzoxazole,PBO)、多孔性氧化矽(porous silicon oxide)，或者薄膜絕緣層36係為其他介電常數值(FPI)小於3之材質。
在形成複數細線路層38在半導體基底30上的過程中，就金屬鑲嵌製程而言，係先濺鍍一擴散阻絶層在一薄膜絕緣層36之開口內的底部及側壁上及薄膜絕緣層36之上表面上，接著再濺鍍一層例如是銅材質之種子層在擴散阻絶層上，接著再電鍍一銅層在此種子層上，接著再利用化學機械研磨(chemical mechanical polishing，CMP)的方式去除位在該薄膜絕緣層36之開口外的銅層、種子層及擴散阻絶層，直到暴露出薄膜絕緣層36的上表面為止。而另一種方式亦可以先濺鍍一鋁層或鋁合金層在一薄膜絕緣層36上，接著再利用微影蝕刻的方式圖案化鋁層或鋁合金層。此細線路層38可透過薄膜絕緣層36內的導通孔40相互連接，或連接至電子元件32上，其中細線路層38一般的厚度是在0.1微米到0.5微米之間。在進行微影製程時，細線路層38之細金屬線路是使用五倍(5X)之曝光機(steppers)或掃描機(scanners)或是使用更佳之儀器來製作。
接著在半導體基底30的表面利用化學氣相沉積(CVD)方式設置一保護層42，此保護層42具有複數缺口暴露出多數接墊44，可以保護半導體基底30內的電子元件32免於濕氣與外來離子污染物(foreign ion contamination)的破壞，也就是說保護層42可以防止移動離子(mobile ions)(比如是鈉離子)、水氣(moisture)、過渡金屬(transition metal) (比如是金、銀、銅)及其他雜質(impurity)穿透，而損壞保護層42下方之電晶體、多晶矽電阻元件或多晶矽－多晶矽電容元件之電子元件32或細金屬線路。為了達到保護的目的，保護層42通常是由氧化矽(silicon oxide)、氧矽化合物、磷矽玻璃、氮化矽(silicon nitride)、及氧氮化矽(silicon oxy－nitride)等所組成。
而保護層42的第一種製作方式可以是先利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氧化矽層，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氮化矽層在該氧化矽層上。
第二種保護層42製作方式可以是先利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氧化矽層，接著再利用電漿加強型化學氣相沉積之步驟形成厚度介於0.05至0.15微米之間的一氮氧化矽層在該氧化矽層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氮化矽層在該氮氧化矽層上。
第三種保護層42製作方式可以是先利用化學氣相沉積之步驟形成厚度介於0.05至0.15微米之間的一氮氧化矽層，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氧化矽層在該氮氧化矽層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氮化矽層在該氧化矽層上。
第四種保護層42製作方式可以是先利用化學氣相沉積之步驟形成厚度介於0.2至0.5微米之間的一第一氧化矽層，接著再利用旋塗法(spin－coating)形成厚度介於0.5至1微米之間的一第二氧化矽層在該第一氧化矽層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至0.5微米之間的一第三氧化矽層在該第二氧化矽層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氮化矽層在該第三氧化矽層上。
第五種保護層42製作方式可以是先利用高密度電漿化學氣相沉積(HDP－CVD)之步驟形成厚度介於0.5至2微米之間的一氧化矽層，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氮化矽層在該氧化矽層上。
第六種保護層42製作方式可以是先形成厚度介於0.2至3微米之間的一未摻雜矽玻璃層(undoped silicate glass，USG)，接著形成比如是四乙氧基矽烷(TEOS)、硼磷矽玻璃(borophosphosilicate glass，BPSG)或磷矽玻璃(phosphosilicate glass，PSG)等之厚度介於0.5至3微米之間的一絕緣層在該未摻雜矽玻璃層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氮化矽層在該絕緣層上。
第七種保護層42製作方式可以是選擇性地 先利用化學氣相沉積之步驟形成厚度介於0.05至0.15微米之間的一第一氮氧化矽層，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氧化矽層在該第一氮氧化矽層上，接著可以選擇性地利用化學氣相沉積之步驟形成厚度介於0.05至0.15微米之間的一第二氮氧化矽層在該氧化矽層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氮化矽層在該第二氮氧化矽層上或在該氧化矽層上，接著可以選擇性地利用化學氣相沉積之步驟形成厚度介於0.05至0.15微米之間的一第三氮氧化矽層在該氮化矽層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氧化矽層在該第三氮氧化矽層上或在該氮化矽層上。
第八種保護層42製作方式可以是先利用化學氣相沉積(PECVD)之步驟形成厚度介於0.2至1.2微米之間的一第一氧化矽層，接著再利用旋塗法(spin－coating)形成厚度介於0.5至1微米之間的一第二氧化矽層在該第一氧化矽層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一第三氧化矽層在該第二氧化矽層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氮化矽層在該第三氧化矽層上，接著再利用化學氣相沉積之步驟形成厚度介 於0.2至1.2微米之間的一第四氧化矽層在該氮化矽層上。
第九種保護層42製作方式可以是先利用高密度電漿化學氣相沉積(HDP－CVD)之步驟形成厚度介於0.5至2微米之間的一第一氧化矽層，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氮化矽層在該第一氧化矽層上，接著再利用高密度電漿化學氣相沉積(HDP－CVD)之步驟形成厚度介於0.5至2微米之間的一第二氧化矽層在該氮化矽層上。
第十種保護層42製作方式可以是先利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一第一氮化矽層，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一氧化矽層在該第一氮化矽層上，接著再利用化學氣相沉積之步驟形成厚度介於0.2至1.2微米之間的一第二氮化矽層在該氧化矽層上。
保護層42的厚度一般係大於0.35微米，在較佳的情況下，氮化矽層之厚度通常大於0.3微米。
完成此保護層42後，請參閱第四a圖所示，接著形成厚度介於3微米至50微米之間的一第一聚合物層46在此保護層42上，此第一聚合物層46具有絶緣功能，且此第一聚合物層46之材質比如為熱塑性塑膠、熱固性塑膠、聚醯亞胺(polyimide，PI)、苯基環丁烯(benzo－cyclo－butene， BCB)、聚氨脂(polyurethane)、環氧樹脂、聚對二甲苯類高分子、焊罩材料、彈性材料或多孔性介電材料。而此第一聚合物層46主要係利用旋塗方式設置，另外也可利用熱壓合乾膜方式、網版印刷方式進行，接著如第四b圖所示，利用蝕刻方式對此第一聚合物層46進行圖案化，而形多數開口48暴露出半導體基底30上的接墊44。其中值得注意的是，當第一聚合物層46為感光材質時，則可以利用微影製程(photolithography process)將第一聚合物層46圖案化；當第一聚合物層46為非感光材質時，則可以利用微影蝕刻製程(photolithography process and etching process)將第一聚合物層46圖案化。
將第一聚合物層46圖案化之後，可利用烘烤加熱、微波加熱或紅外線加熱其中之一方式對第一聚合物層46加熱至介於攝氏200度與攝氏320度之間的溫度或加熱至介於攝氏320度與攝氏450度之間的溫度，以硬化(curing)第一聚合物層46，硬化後的第一聚合物層46在體積上會呈現縮小的情形，且第一聚合物層46含水率小於1%，此含水率係將第一聚合物層46置放在溫度介於攝氏425度至450度之間時，其重量變化率小於1%。
如第五圖所示，以濺鍍方式形成厚度介於400埃至7000埃之間的一第一黏著/阻障層50(Adhesion/Barrier/seed layer)在第一聚合物層46及接墊44上，其中此第一黏著/阻障層50之材質係選自鈦金屬、氮化鈦、鈦鎢合金、鉭金屬層、鉻、鉻銅合金及氮化鉭其 中之一或所組成之群組的至少其中之一者，且第一黏著/阻障層50上另形成有一種子層(圖中未示)，此種子層有利於後續金屬線路的設置，因此種子層之材質也隨後續的金屬線路材質有所變化，此外在本文後續實例中所有黏著/阻障層上皆形成有一種子層，在此特以說明。
當種子層上是電鍍形成銅材質之金屬線路時，種子層之材料係以銅為佳；當要電鍍形成銀材質之金屬線路時，種子層之材料係以銀為佳；當要電鍍形成鈀材質之金屬線路時，種子層之材料係以鈀為佳；當要電鍍形成鉑材質之金屬線路時，種子層之材料係以鉑為佳；當要電鍍形成銠材質之金屬線路時，種子層之材料係以銠為佳；當要電鍍形成釕材質之金屬線路時，種子層之材料係以釕為佳；當要電鍍形成錸材質之金屬線路時，種子層之材料係以錸為佳；當要電鍍形成鎳材質之金屬線路時，種子層之材料係以鎳為佳。
接著如第六a圖所示，形成一第一圖案化光阻層54在位於此第一黏著/阻障層50上之種子層上，此第一圖案化光阻層54具有多數開口56暴露出部分的位在第一黏著/阻障層50上的種子層，在形成開口56的過程中比如是利用一倍(1X)之曝光機(steppers)或掃描機(scanners)，且此第一圖案化光阻層54係為正光阻型式。接著電鍍形成厚度介於1微米至50微米之間的一第一金屬層58在開口56所暴露出且位在第一黏著/阻障層50上的種子層上，此第一金屬層58較佳的厚度係介於2微米至30微米之間，使第一 金屬層58電連接至細連線結構34，此第一金屬層58比如是金、銅、銀、鈀、鉑、銠、釕、錸或鎳之單層金屬層結構，或是由上述金屬材質所組成的複合層，並在去除此第一圖案化光阻層54之後，即形成一第一重配置線路層60，值得注意的特點在於此第一重配置線路60主要係將第一金屬層58形成在開口48上及延伸至部分的第一聚合物層46上，並不是單純形成在開口48上，而所延伸的第一金屬層58上則有利於後續的線路的設置。
如第六b圖所示，接著形成一第二圖案化光阻層62在此第一重配置線路60上及位在第一黏著/阻障層50上之種子層上，此第二圖案化光阻層62之多數開口64暴露出此第一重配置線路60的第一金屬層58，接著如第六c圖所示，電鍍形成厚度介於20微米至300微米之間的一第二金屬層66在此開口64內，且此第二金屬層66之最大橫向寛度係介於3微米至50微米之間，此第二金屬層66之材質選自金、銅、銀、鈀、鉑、銠、釕、錸或鎳其中之一或所組成之群組的至少其中之一者，此第二金屬層66較佳的厚度係介於30微米至100微米之間。
其中值得注意的是第二金屬層66之材質若是銅金屬時，則第一重配置線路60較佳的頂層金屬材質係為銅金屬；第二金屬層66之材質若是銀金屬時，則第一重配置線路60較佳的頂層金屬材質係為銀金屬；第二金屬層66之材質若是鈀金屬時，則第一重配置線路60較佳的頂層金屬材質係為鈀金屬；第二金屬層66之材質若是鉑金屬時，則 第一重配置線路60較佳的頂層金屬材質係為鉑金屬；第二金屬層66之材質若是銠金屬時，則第一重配置線路60較佳的頂層金屬材質係為銠金屬；第二金屬層66之材質若是釕金屬時，則第一重配置線路60較佳的頂層金屬材質係為釕金屬；第二金屬層66之材質若是錸金屬時，則第一重配置線路60較佳的頂層金屬材質係為錸金屬；第二金屬層66之材質若是鎳金屬時，則第一重配置線路60較佳的頂層金屬材質係為鎳金屬。
如第六d圖所示，接著去除第二圖案化光阻層62，並利用雙氧水蝕刻去除未在第一金屬層58下的第一黏著/阻障層50，其中除了利用雙氧水去除第一黏著/阻障層50外，並利用含有碘之蝕刻液去除第一黏著/阻障層50上的種子層，例如碘化鉀等蝕刻液。此外，去除未在第一金屬層58下的種子層及第一黏著/阻障層50之步驟除了在去除第二圖案化光阻層62之後進行，也可在去除此第一圖案化光阻層54後進行，如第六e圖所示。
如第七a圖及第七b圖所示，在去除第一金屬層58下的第一黏著/阻障層50之後，每一第二金屬層66即定義成本發明之金屬柱體68，此金屬柱體68的最大橫向尺寸Hw除以高度Ht之比值係小於4，甚至此比值可小於3或2或1等，此金屬柱體68的最大橫向寬度係介於3微米至50微米之間，因此金屬柱體68為細小的柱體並不同於先前技術中的金屬層或線路層，而且相鄰金屬柱體68之中心至中心的間距Hb係介於10微米至250微米之間，並且較 佳之間距可縮至10微米至200微米之間、10微米至175微米之間、10微米至150微米之間。此金屬柱體68設置在此第二金屬層66的俯視圖如第七b圖所示，由此圖示中可明顯看出此金屬柱體68係形成在重配置線路60所延伸出的區域上，而非形成在開口48上的重配置線路60上。
如第八a圖所示，形成一第二聚合物層70在此半導體基底30之上，並將金屬柱體68覆蓋。此第二聚合物層70之材質比如為熱塑性塑膠、熱固性塑膠、聚醯亞胺(polyimide，PI)、苯基環丁烯(benzo－cyclo－butene，BCB)、聚氨脂(polyurethane)、環氧樹脂、聚對二甲苯類高分子、焊罩材料、彈性材料或多孔性介電材料。而此第二聚合物層70的設置方式可以是利用網版印刷方式或旋塗方式；請參閱第八b圖所示，若是以網版印刷方式設置此第二聚合物層70，則可直接在第二聚合物層70內形成多數開口72而暴露出金屬柱體68頂端。若是以旋塗方式設置此第二聚合物層70，則必須再經由一圖案化步驟形成多數開口72，進而暴露出金屬柱體68頂端。此第二聚合物層70若是以旋塗方式設置，則形成開口72之方式則係以微影或微影蝕刻方式形成。如第八c圖所示，暴露此金屬柱體68的方式除了形成開口72之外，也可採用研磨方式使金屬柱體68暴露出，但是進行研磨步驟前則必須將此第二聚合物層70進行硬化(Curing)，等硬化後利用一化學機械研磨(CMP)將第二聚合物層70進行研磨，使金屬柱體68頂端暴露出。除了可利用化學機械研磨(CMP)之外，也可直接以機械研 磨方式進行研磨，而硬化的步驟同樣是利用烘烤加熱、微波加熱或紅外線加熱其中之一方式進行。
另外在此預先說明後續許多實施例大多是由第八b圖及第八c圖中的結構所延伸，所以對於本發明而言此二圖示中揭示在半導體基底30上形成多數金屬柱體68，相鄰金屬柱體68之間具有細間距(fine pitch)特徵，其間距係介於10微米至250微米之間，且金屬柱體68之最大橫向尺寸Hw除以高度Ht之比值係小於4，因此後續許多實施例皆是在此金屬柱體68上進行變化，而在此第一實施例中則係以第八c圖之結構為基礎。
如第九圖所示，利用旋塗方式形成一第三聚合物層74在第二聚合物層70上，對此第三聚合物層74進行圖案化步驟形成多數開口76，此第三聚合物層74之圖案化步驟係利用微影或微影蝕刻方式進行；另外也可將乾膜型式且己圖案化之第三聚合物層74熱壓合在此第二聚合物層70上，或者是利用網版印刷方式將第三聚合物層74形成在第二聚合物層70上，此第三聚合物層74之材質比如為熱塑性塑膠、熱固性塑膠、聚醯亞胺(polyimide，PI)、苯基環丁烯(benzo－cyclo－butene，BCB)、聚氨脂(polyurethane)、環氧樹脂、聚對二甲苯類高分子、焊罩材料、彈性材料或多孔性介電材料。
如第十a圖所示，以濺鍍方式形成厚度介於400埃至7000埃之間的一第二黏著/阻障層78在第三聚合物層74上及金屬柱體68頂端表面上，此第二黏著/阻障層78之材 質係選自鈦金屬、氮化鈦、鈦鎢合金、鉭金屬層、鉻、鉻銅合金及氮化鉭其中之一或所組成之群組的至少其中之一者，並且同樣在此第二黏著/阻障層78上形成一種子層，接著如第十b圖所示，形成一第三圖案化光阻層82在第二黏著/阻障層78上之種子層上，此第三圖案化光阻層82係為正光阻型式，在此第三圖案化光阻層82之多數開口83暴露出位在開口76上及開口76周圍上的第二黏著/阻障層78上之種子層。
接著如第十c圖所示，利用電鍍方式形成一第三金屬層84在開口83所暴露出且在第二黏著/阻障層78上之種子層上，此第三金屬層84之材質選自金、銅、銀、鈀、鉑、銠、釕、錸、鎳、銲料、錫鉛合金、錫銀合金、錫銀銅合金或無鉛銲料等其中之一或所組成之群組的至少其中之一者，如第十d圖所示，接著同樣利用雙氧水蝕刻去除未在第三金屬層84下的第二黏著/阻障層78，其中也可利用含有碘之蝕刻液去除種子層，比如碘化鉀等蝕刻液；在此值得注意的地方於此第三金屬層84電鍍所形成的厚度的差異、第三金屬層84材質差異及位置差異則會使此半導體基底30接合至外界電路產生各種不同型式及應用，也就是根據不同的應用，第三圖案化光阻層82之厚度、開口83寛度及開口82形成位置也會隨之變化，進而電鍍形成不同厚度、位置及材質的第三金屬層84，其中上述之外界電路係為軟版、半導體晶片、印刷電路板、陶瓷基板或玻璃基板等。
在本實施例中，此第三金屬層84所形成之型式包括凸塊(bump)、接墊(pad)、重配置線路層(RDL)或錫球(solder)。如上述第十d圖所示，當第三金屬層84之材質為金(Au)、銅、銀、鈀、鉑、銠、釕或錸時，並且所形成的第三金屬層84之厚度(Ha)介於5微米至30微米之間時，較佳厚度則是介於10微米至25微米之間，此第三金屬層84定義成一凸塊86，且相鄰凸塊86中心至中心之間距係小於250微米，較佳者甚至可小於200微米或150微米。接著如第十一圖所示，將此半導體基底30進行切割，使半導體基底30形成複數半導體單元88，而每一半導體單元88上的凸塊86可藉由形成一異方性導電膠(ACF)電連接至一外界電路上。
如第十二a圖及第十二b圖所示，第三金屬層84之材質係為銲料、錫鉛合金、錫銀合金、錫銀銅合金或無鉛銲料其中之一，且第三金屬層84之厚度(Hs)係介於20微米至150微米之間，較佳厚度則是介於30微米至100微米之間。接著如第十二c圖所示，將此半導體基底30進行一加熱步驟，此第三金屬層84在加熱時會熔融形成球狀，此形成球狀之第三金屬層84定義成一錫球92，且相鄰錫球92中心至中心之間距係小於250微米，較佳者甚至可小於200微米或150微米。此第三金屬層84的型式除了上述二種之外，也可以利用電鍍方式形成厚度介於1微米至100微米之間的銅層在第三圖案化光阻層82之開口83內，接著再電鍍形成厚度介於1微米至10微米之間的鎳層在銅層上， 最後電鍍形成厚度介於20微米至150微米之間的一錫層、一錫銀層或一錫銀銅合金層在此鎳層上。
接著將此半導體基底30進行切割步驟，如第十二d圖所示，使半導體基底30形成複數半導體單元88，而每一半導體單元88上的錫球92可接合在外界之基板94上，此基板94係為半導體晶片、印刷電路板、陶瓷基板或玻璃基板。
如第十二e圖所示，此半導體單元88上的錫球92接合在基板94上時，其中半導體單元88接合至基板94前可預先再形成一第四聚合物層96在基板94上，此第四聚合物層96之材質可選自熱塑性塑膠、熱固性塑膠、聚醯亞胺(polyimide，PI)、苯基環丁烯(benzo－cyclo－butene，BCB)、聚氨脂(polyurethane)、環氧樹脂、聚對二甲苯類高分子、焊罩材料、彈性材料或多孔性介電材料。而形成此第四聚合物層96方式包括熱壓合一己圖案化之乾膜(dry film)在該基板94上、或熱壓合一感光性乾膜在基板94上，並利用微影方式圖案化感光性乾膜、或熱壓合一非感光性乾膜在基板94上，並利用微影蝕刻方式圖案化非感光性乾膜、或利用一網版印刷步驟形成第四聚合物層96在基板94上、或以旋塗方式形成一感光性薄膜在基板94上，並利用微影方式圖案化感光性薄膜或以旋塗方式形成一非感光性薄膜在基板94上，並利用微影蝕刻方式圖案化非感光性薄膜。待半導體單元88上的錫球92接合在基板94上後進行加熱步驟，使第四聚合物層96硬化，此加熱步驟可藉由烘 烤加熱、微波加熱或紅外線加熱等方式達成。
如第十三a圖及第十三b圖所示，當第三金屬層84之材質為金(Au)、銅、銀、鈀、鉑、銠、釕或錸時，並且所形成的第三金屬層84之厚度(Hp)介於1微米至15微米之間時，較佳厚度則是介於2微米至10微米之間，此第三金屬層84定義成一接墊(pad)98，且相鄰接墊98中心至中心之間距係小於250微米，較佳者甚至可小於200微米或150微米，此接墊98可利用打線製程形成一導線(wire)連接至外界電路上。
如第十四a圖及第十四b圖所示，當第三金屬層84之材質為金(Au)、銅、銀、鈀、鉑、銠、釕或錸時，並且所形成的第三金屬層84之厚度(Hr)介於5微米至30微米之間時，較佳厚度則是介於10微米至25微米之間，且此第三金屬層84形成的位置除了在第三聚合物層74之開口76上，還形成在開口76一側邊的第二黏著/阻障層78上，此第三金屬層84定義為一重配置線路層(RDL)100，此重配置線路層100可利用打線製程形成導線(wire)連接至外界電路上，其中在此加強說明形成在開口76一側邊之第三金屬層84係類似接墊98之功能，此種偏邊(心)之設計是為了防止上述接墊98之尺寸過小時，在打線製程所需之打線面積不足，造成打線製程之困難度增加。
此外本實施例中第九圖至第十四b圖中的凸塊(bump)、接墊(pad)、重配置線路層(RDL)或錫球(solder)等應用皆是由第八c圖結構所延伸，但這些應用同樣也可直 接由第八b圖中結構所延伸，原因在於第九圖之結構係由形成第三聚合物層74在第八c圖結構上，並且圖案化此第三聚合物層74形成多數開口，然而第八b圖之結構並非是經由研磨直到暴露出金屬柱體68，而是以圖案化方式形成多數開口72暴露出金屬柱體68，並且不需再設置第三聚合物層74，也就是說此第八b圖之結構相似於第八c圖之結構加上第三聚合物層74，因此關於第九圖後續延伸的如第十a圖至第十d圖、第十一圖、第十二a圖至第十二e圖、第十三a圖至第十三b圖及第十四a圖至第十四b圖所示之凸塊(bump)、接墊(pad)、重配置線路層(RDL)或錫球(solder)等應用可以推及到第八b圖所示的結構中，在此就不加以重複敍述說明。
第二實施例：
此實施例為第一實施例中的第八c圖之延伸，請參閱第十五a圖所示，此實施例中金屬柱體68之頂部係為一金層102，此金層的厚度係介於1微米至30微米之間，而在此金屬柱體68之金層102上利用打線製程形成一導線104電連接至外界電路上，其中值得注意在於金層102以下之金屬包括銅層104、鎳層106(銅/鎳/金結構)，此銅層104的厚度係介於10微米至100微米之間，而鎳層106的厚度則是介於1微米至10微米之間，或是如第十五b圖所示，金層102以下係為銅層104(銅/金結構)，此金層102的厚度係介於1微米至30微米之間，或是如第十五c圖所示， 整個金屬柱體68之材質為金材質，此金材質之金屬柱體68的厚度係介於10微米至100微米之間。
第三實施例：
此實施例係為第一實施例中的第八c圖之延伸，請參閱第十六a圖所示，形成一第三黏著/阻障層105在第二聚合物層70上，同樣在此第三黏著/阻障層105上形成有一種子層，此種子層之材質隨後續設置之金屬材質而改變。如第十六b圖所示，形成一第四圖案化光阻層110在第三黏著/阻障層105上，此第四圖案化光阻層110內具有多數開口112，其中至少一開口112位置係位在金屬柱體68上方，且此開口112係呈現線圈形狀。如第十六c圖所示，電鍍形成一第四金屬層114在第四圖案化光阻層110之開口112內，此第四金屬層114之材質係為金(Au)、銅、銀、鈀、鉑、銠、釕、錸其中之一，且此第四金屬層114之厚度係介於1微米至30微米之間，此外此第四金屬層114也可由多層複合金屬層所構成，例如電鍍厚度介於1微米至30微米之間的一銅層，並再電鍍形成厚度介於1微米至10微米之間的一鎳層在此銅層上，最後再形成厚度介於1微米至10微米之間的一金層在此鎳層上。
如第十六d圖所示，移除第四圖案化光阻層110，並且同樣利用雙氧水去除第三黏著/阻障層105，並利用含有碘之蝕刻液蝕刻去除未在第四金屬層114下的種子層。如第十六e圖所示，此第四金屬層114呈現線圈形狀，因此 將此第四金屬層114定義為一第一線圈金屬層116，其中第一線圈金屬層116透過金屬柱體68電連接至半導體基底30。如第十六f圖所示，除了可電連接至半導體基底30之外，也可透過打線製程電連接至外界電路(圖中未示)，並且可形成厚度介於5微米至25微米之間一保護層117在此第一線圈金屬層116上，以保護第一線圈金屬層116不受損壞及水氣入侵，此保護層117之材質係為有機化合物或無機化合物等，比如為熱塑性塑膠、熱固性塑膠、聚醯亞胺(polyimide，PI)、苯基環丁烯(benzo－cyclo－butene，BCB)、聚氨脂(polyurethane)、環氧樹脂、聚對二甲苯類高分子、焊罩材料、彈性材料、多孔性介電材料、氧化矽(silicon oxide)、氧矽化合物、磷矽玻璃、氮化矽(silicon nitride)及氧氮化矽(silicon oxy－nitride)等所組成，此第一線圈金屬層116可應用在電感、電容及電阻等被動元件的領域之中。
在此列舉出此第一線圈金屬層116在電感被動元件之應用，請參閱第十六g圖所示，在此第一線圈金屬層116覆蓋一第五聚合物層118，此第五聚合物層118之厚度係介於20微米至300微米之間，此第五聚合物層118之材質比如是聚醯亞胺(polyimide，PI)，且此第五聚合物層118係利用旋塗方式形成；接著藉由形成第一線圈金屬層116方式在第五聚合物層118上形成一第二線圈金屬層120，此第二線圈金屬層120可電連接至外界電路，當外界電路電流有所變化時，經由第二線圈金屬層120產生感應電動勢使第一線圈金屬層116感應，並產生訊號傳入半導體基 底30內，如此即解說完成此電感被動元件的製作。
此外利用上述選擇性電鍍方式，也可在第二聚合物層70上形成一電容元件121(capacitor)，如第十六h圖所示，圖中在第二聚合物層70設有厚度500埃至5000埃之間的一低介電層121a，此低介電層121a材質係選自鈦、鈦鎢合金、鉭或鉭氮化合物等，且此低介電層121a電連接至一金屬柱體68，接著在低介電層121a上包覆一高介電層121b，此高介電層121b之材質係為氮氧矽化合物、氧矽化合物(silicon oxide)或聚醯亞胺(polyimide，PI)，在相鄰之金屬柱體68上電鍍形成一低電阻金屬層121c，此低電阻金屬層121c之形成方式共有2種，首先第1種方式係先濺鍍形成厚度介於400埃至7500埃之間的一黏著/阻障層在第二聚合物層70及高介電層121b上，此黏著/阻障層之材質係為鈦、鈦鎢合金、鉻、鉭或氮化鉭等，接著再濺鍍形成厚度介於500埃至5000埃之間的種子層在此黏著/阻障層上，接著再電鍍厚度介於1微米至30微米之間的一銅層在此種子層上，接著電鍍厚度介於1微米至10微米之間的一鎳層在此銅層上。
而第2種方式則是先濺鍍形成厚度介於400埃至7500埃之間的一黏著/阻障層在第二聚合物層70及高介電層121b上，接著再濺鍍厚度介於500微米至5000微米之間且材質為金之一種子層在此黏著/阻障層上，最後電鍍厚度介於1微米至30微米之間的一金層在材質為金的種子層上。如此對此相鄰金屬柱體68施加電壓時，在高介電層 121b上下二側形成大電壓差，此結構可作為具有電容功能。最後可在此低電阻金屬層121c及第二聚合物層70上覆蓋一保護層121d，防止此電容元件121受到損壞。
第四實施例：
此實施例係為第一實施例中的第八b圖的延伸，請參閱第十七a圖所示，形成一第四黏著/阻障層122在第二聚合物層70上，此第四黏著/阻障層122之材質係為鈦、鈦鎢合金、鉻、鉭或氮化鉭其中之一，且同樣在此第四黏著/阻障層122上形成有一種子層，此種子層之材質包括有金、銅、銀、鉑、錸、釕、鈀或銠其中之一。如第十七b圖所示，形成一第五圖案化光阻層126在第四黏著/阻障層122上，此第五圖案化光阻層126內具有多數開口128，其中二開口128位置係位在金屬柱體68上方。如第十七c圖所示，電鍍形成厚度介於5微米至30微米之間的一第五金屬層130在第五圖案化光阻層126之開口128內的第四黏著/阻障層122上，且此第五金屬層130係為低電阻，比如金、銀、鉑、錸、釕、鈀、銠或銅等，且此第五金屬層130的厚度係介於1微米至30微米之間；或者此第五金屬層130可由多層複合金屬層所構成，例如電鍍厚度介於1微米至30微米之間的一銅層，並再電鍍形成厚度介於1微米至10微米之間的一鎳層在此銅層上，最後再形成厚度介於1微米至10微米之間的一金層在此鎳層上
接著如第十七d圖所示，移除第五圖案化光阻層126， 並且同樣利用雙氧水及含有碘之蝕刻液蝕刻去除未在第五金屬層130下的第四黏著/阻障層122及種子層，此第五金屬層130電連接至二金屬柱體68，此第五金屬層130係為二金屬柱體68之間的金屬連接線路，此金屬連接線路可提供電流快速流動之通道，另外可形成一保護層132覆蓋在第二聚合物層70及第五金屬層130上，防止此第五金屬層130受到損壞及水氣入侵。
除了形成第五金屬層130作為金屬連接線路之外，也可延伸為多層線路結構，如第十七e圖所示，形成一第六聚合層134在第二聚合物層70及第五金屬層130上，接著如第十七f圖所示，圖案化此第六聚合層134形成多數開口暴露出第五金屬層130。如第十七g圖所示，依序濺鍍形成一第五黏著/阻障層136，此第五黏著/阻障層136之材質係選自鈦、鈦鎢合金、鉭、氮化鉭及鉻其中之一，並同樣在此第五黏著/阻障層136上形成一種子層(圖中未示)，此種子層之材質比如是金、銅、銀、鉑、錸、釕、鈀或銠其中之一。如第十七h圖所示，形成一第六圖案化光阻層140在第五黏著/阻障層136上的種子層上，此第六圖案化光阻層140之多數開口暴露出位在第六聚合層134之開口上之第五黏著/阻障層136上的種子層上。如第十七i圖所示，形成一第六金屬層142在第六圖案化光阻層140之開口內，此第六金屬層142之材質係為金(Au)、銅、銀、鈀、鉑、銠、釕或錸其中之一，且此第六金屬層142之厚度係介於1微米至30微米之間，此外此第六金屬層142 也可由多層複合金屬層所構成，例如電鍍厚度介於1微米至30微米之間的一銅層，並再電鍍形成厚度介於1微米至10微米之間的一鎳層在此銅層上，最後再形成厚度介於1微米至10微米之間的一金層在此鎳層上。
如第十七j圖所示，移除第六圖案化光阻層140以及移除未在第六金屬層142下方的第五黏著/阻障層136及種子層。如第十七k圖所示，接著再形成厚度介於10微米至25微米之間的一第七聚合物層144在第六聚合層134及第六金屬層142上，此第七聚合物層144之材質比如是聚醯亞胺(polyimide，PI)，且此第七聚合物層144係利用旋塗方式形成。如第十七l圖所示，藉由圖案化此第七聚合物層144來形成多數開口暴露出此第六金屬層142。如第十七m圖所示，藉由打線製程形成一導線在暴露出的第六金屬層142上，藉此電連接至外界電路上。
第五實施例：
此實施例係為第一實施例中的第八b圖之延伸，且此實施例與第四實施例相似，請參閱第十八圖所示，其中此實施例形成之方式與第四實施例相同，差異點在於第四實施例中的第五金屬層130係為低電阻的材質，因此第五金屬層130可供電流快速流通，然而第五實施例中(由第十八圖觀之)的第七金屬層146係為高電阻材質，比如是鉻/鎳合金(Cr/Ni)、鈦或鎢等，且此第七金屬層146之厚度係介於1微米至3微米之間，因此第七金屬層146在此實施例 中係做為電阻元件之用。
第六實施例：
上述第一實施例至第五實施例是第八b圖及第八c圖結構的延伸，然而本實施例則是由第八a圖結構所延伸。請參閱第十九a圖及第十九b圖所示，此實施例係利用蝕刻方式將部分的第二聚合物層70去除，其中在蝕刻此第二聚合物層70之前可預先利用化學機械研磨或機械研磨方式將此第二聚合物層70平坦化，如此可使進行蝕刻步驟時能均勻去除第二聚合物層70，直到暴露出高度介於1微米至150微米之間的金屬柱體68，此暴露出的高度是金屬柱體68頂面至第二聚合物層70頂面之間的距離。若金屬柱體68之材質為金(Au)、銅、銀、鈀、鉑、銠、釕或錸時，則金屬柱體68較佳暴露出的高度係介於15微米至30微米之間，此暴露出的金屬柱體68可作為凸塊使用，接著如第十九c圖所示，同樣進行切割步驟將此半導體基底30切割形成複數半導體單元88，同樣每一半導體單元88上的凸塊可藉由形成一異方性導電膠(ACF)電連接至外界電路上。
若金屬柱體68之材質為銲料、錫鉛合金、錫銀合金、錫銀銅合金或無鉛銲料時，則金屬柱體68較佳暴露出的高度係介於50微米至100微米之間，如第十九d圖所示，且同樣經過一加熱步驟使暴露在外之金屬柱體68熔融成球狀(銲料錫球)，接著如第十九e圖所示，同樣進行切割步 驟將此半導體基底30切割形成複數半導體單元，每一半導體單元上的球形凸塊接合至外界之基板上，並且在半導體單元與基板之間形成一第八聚合物層148包覆每一球形凸塊。
請參閱第十九f圖所示，若金屬柱體68之材質為金(Au)、銅、銀、鈀、鉑、銠、釕或錸時，則金屬柱體68較佳暴露出的高度係介於1微米至15微米之間，此暴露出的金屬柱體68可作為接墊使用，此接墊可利用打線製程形成一導線(wire)連接至外界電路上。
請參閱第十九g圖所示，若暴露之金屬柱體68之材質為金(Au)、銅、銀、鈀、鉑、銠、釕或錸時，且所暴露之高度介於5000埃至10微米之間時，形成一第六黏著/阻障層150在第二聚合物層70及金屬柱體68暴露之表面上，此第六黏著/阻障層150之材質係選自鈦、鈦鎢合金、鉭、氮化鉭及鉻其中之一，並同樣在此第六黏著/阻障層150上形成一種子層(圖中未示)，此種子層之材質比如是金、銅、銀、鉑、錸、釕、鈀或銠其中之一，且此第六黏著/阻障層150之厚度係介於1000埃至7500埃之間。
如第十九h圖所示，形成一第七圖案化光阻層152在第六黏著/阻障層150上的種子層上，第七圖案化光阻層152之多數開口暴露出第六黏著/阻障層150上的種子層。如第十九i圖所示，形成一第八金屬層154在第七圖案化光阻層152之開口內。如第十九j圖所示，去除第七圖案化光阻層152，並去除未在第八金屬層154下之第六黏著/ 阻障層150及種子層，其中此第八金屬層154連接二金屬柱體68以作為金屬連接線路，此第八金屬層154之材質係為金(Au)、銅、銀、鈀、鉑、銠、釕或錸其中之一，且此第八金屬層154之厚度係介於1微米至30微米之間，此外此第八金屬層154也可由多層複合金屬層所構成，例如電鍍厚度介於1微米至30微米之間的一銅層，並再電鍍形成厚度介於1微米至10微米之間的一鎳層在此銅層上，最後再形成厚度介於1微米至10微米之間的一金層在此鎳層上。
如第十九k圖所示，最後形成一保護層156覆蓋在第八金屬層154及第二聚合物層70上，用以保護此第八金屬層154受到損傷，此保護層156之材質係為熱塑性塑膠、熱固性塑膠、聚醯亞胺(polyimide，PI)、苯基環丁烯(benzo－cyclo－butene，BCB)、聚氨脂(polyurethane)、環氧樹脂、聚對二甲苯類高分子、焊罩材料、彈性材料、多孔性介電材料、氧化矽(silicon oxide)、氧矽化合物、磷矽玻璃、氮化矽(silicon nitride)及氧氮化矽(silicon oxy－nitride)等所組成。
此種利用蝕刻暴露出金屬柱體68除了可應用在上述凸塊、接墊及金屬連接線路之結構外，也可藉由此結構應用在線圈結構、電容結構及電阻結構等，因製作步驟與上述各別實施例相似，在此就不加以重覆解說。
第七實施例：
此實施例之結構與第八c圖結構相似，差異點在於形成金屬柱體68及形成第二聚合物層70之製程不同，請參閱第二十a圖所示，在形成此第一重配置線路60在半導體基底30之上後，去除未在第一重配置線路60下的黏著/阻障層50及種子層(如第六e圖所示)，接著形成一第九圖案化聚合物層158在此第一重配置線路60上及第一聚合物層46上，此第九圖案化聚合物層158之多數開口暴露出第一重配置線路60，且第九圖案化聚合物層158之開口深度係介於20微米至300微米之間。
此第九圖案化聚合物層158之材質可選自熱塑性塑膠、熱固性塑膠、聚醯亞胺(polyimide，PI)、苯基環丁烯(benzo－cyclo－butene，BCB)、聚氨脂(polyurethane)、環氧樹脂、聚對二甲苯類高分子、焊罩材料、彈性材料或多孔性介電材料，且此第九圖案化聚合物層158的形成方式包括熱壓合一己圖案化之乾膜(dry film)在第一重配置線路60上及第一聚合物層46上、或熱壓合一感光性乾膜在第一重配置線路60上及第一聚合物層46上，並利用微影方式圖案化感光性乾膜、或熱壓合一非感光性乾膜在第一重配置線路60上及第一聚合物層46上，並利用微影蝕刻方式圖案化非感光性乾膜、或利用一網版印刷步驟形成第九圖案化聚合物層158在第一重配置線路60上及第一聚合物層46上、或以旋塗方式形成一感光性薄膜在第一重配置線路60上及第一聚合物層46上，並利用微影方式圖案化感光性薄膜或以旋塗方式形成一非感光性薄膜在第一重配置 線路60上及第一聚合物層46上，並利用微影蝕刻方式圖案化非感光性薄膜。
如第二十b圖所示，形成厚度介於400埃至7000埃之間的一第七黏著/阻障層160在第九圖案化聚合物層158上以及在第九圖案化聚合物層158之開口所暴露出的第一重配置線路60上，此第七黏著/阻障層160之材質係選自鈦、鈦鎢合金、鉭、氮化鉭及鉻其中之一，並同樣在此第七黏著/阻障層160上形成一種子層(圖中未示)，此種子層之材質比如是金、銅、銀、鉑、錸、釕、鈀或銠其中之一，且此第七黏著/阻障層160之厚度係介於1000埃至7500埃之間。
如第二十c圖所示，以鑲嵌(Damascene)方式形成一第九金屬層162在第七黏著/阻障層160上，並填滿第九圖案化聚合物層158之開口，此第九金屬層162之材質係為金(Au)、銅、銀、鈀、鉑、銠、釕或錸其中之一，且此第九金屬層162之厚度係介於1微米至30微米之間，此外此第九金屬層162也可由多層複合金屬層所構成，例如電鍍厚度介於1微米至30微米之間的一銅層，並再電鍍形成厚度介於1微米至10微米之間的一鎳層在此銅層上，最後再形成厚度介於1微米至10微米之間的一金層在此鎳層上。
如第二十d圖所示，進行一研磨步驟將第九圖案化聚合物層158之開口以外的第九金屬層162及第七黏著/阻障層160去除，此研磨步驟係利用化學機械研磨(CMP)或機械研磨方式進行，以完成金屬柱體68的設置，而此金屬柱 體68的最大橫向尺寸Hw除以高度Ht之比值係小於4，此金屬柱體68的最大橫向寬度係介於3微米至50微米之間，且相鄰金屬柱體68之間距Hb係介於10微米至250微米之間。
由於鑲嵌(Damascene)方式所形成的金屬柱體68結構與上述第八c圖中所揭示的結構十分相似，因此後續在第九圖案化聚合物層158及金屬柱體68上製作其它元件之方式係為相同之步驟。
例如第二十一a圖至第二十一d圖所示，此圖係揭示在第九圖案化聚合物層158及金屬柱體68上製作凸塊、接墊、錫球、重配置線路層，其中製程部分己在上述實施例中說明，所以在此只揭示最終完成之結構，其製程部分就不重覆說明。
如第二十二圖至第二十五圖所示，此圖係揭示在第九圖案化聚合物層158及金屬柱體68上製作金屬連接線路(interconnetion)、線圈、電容元件、電阻元件，其中製程部分己在上述實施例中說明，所以在此只揭示最終完成之結構，其製程部分就不重覆說明。
本發明可提供應力的釋放與微小化的接觸窗結構之間之間距，依據本發明，其間距係小於250微米，且可達成針孔數目少於400個的目標。並能有效改善積體電路的性能，且可大幅降低低電源IC元件之IC金屬連接線路之阻抗及荷載。
以上所述係藉由實施例說明本發明之特點，其目的在 使熟習該技術者能暸解本發明之內容並據以實施，而非限定本發明之專利範圍，故，凡其他未脫離本發明所揭示之精神所完成之等效修飾或修改，仍應包含在以下所述之申請專利範圍中。
10‧‧‧後護層結構
12‧‧‧重配置線路層
14‧‧‧聚合物層
18‧‧‧半導體積體電路晶片
16‧‧‧保護層
20‧‧‧接墊
22‧‧‧斜坡
30‧‧‧半導體基底
32‧‧‧電子元件
34‧‧‧細連線結構
36‧‧‧薄膜絕緣層
38‧‧‧細線路層
40‧‧‧導通孔
42‧‧‧保護層
44‧‧‧接墊
46‧‧‧第一聚合物層
48‧‧‧開口
50‧‧‧第一黏著/阻障層
54‧‧‧第一圖案化光阻層
56‧‧‧開口
58‧‧‧第一金屬層
60‧‧‧第一重配置線路層
62‧‧‧第二圖案化光阻層
64‧‧‧開口
66‧‧‧第二金屬層
68‧‧‧金屬柱體
70‧‧‧第二聚合物層
72‧‧‧開口
74‧‧‧第三聚合物層
76‧‧‧開口
78‧‧‧第二黏著/阻障層
82‧‧‧第三圖案化光阻層
83‧‧‧開口
84‧‧‧第三金屬層
86‧‧‧凸塊
88‧‧‧半導體單元
92‧‧‧錫球
94‧‧‧基板
96‧‧‧第四聚合物層
98‧‧‧接墊
100‧‧‧重配置線路層
102‧‧‧金層
104‧‧‧銅層
106‧‧‧鎳層
105‧‧‧第三黏著/阻障層
110‧‧‧第四圖案化光阻層
112‧‧‧開口
114‧‧‧第四金屬層
116‧‧‧第一線圈金屬層
117‧‧‧保護層
118‧‧‧第五聚合物層
120‧‧‧第二線圈金屬層
121‧‧‧電容元件
121a‧‧‧低介電層
121b‧‧‧絶緣層
121c‧‧‧低電阻金屬層
121d‧‧‧保護層
122‧‧‧第四黏著/阻障層
126‧‧‧第五圖案化光阻層
128‧‧‧開口
130‧‧‧第五金屬層
132‧‧‧保護層
134‧‧‧第六聚合層
136‧‧‧第五黏著/阻障層
140‧‧‧第六圖案化光阻層
142‧‧‧第六金屬層
144‧‧‧第七聚合物層
146‧‧‧第七金屬層
148‧‧‧第八聚合物層
150‧‧‧第六黏著/阻障層
152‧‧‧第七圖案化光阻層
154‧‧‧第八金屬層
156‧‧‧保護層
158‧‧‧第九圖案化聚合物層
160‧‧‧第七黏著/阻障層
162‧‧‧第九金屬層
圖式說明：
第一圖為習知技術之剖面示意圖。
第二圖為本發明半導體基底之剖面示意圖。
第三圖為本發明半導體基底上設置細連線結構及保護層之剖面示意圖。
第四a圖及第四b圖為本發明形成第一聚合物層之剖面示意圖。
第五圖為本發明形成第一黏著/阻障層之剖面示意圖。
第六a圖至第六e圖為本發明形成第一重配置線路層及金屬柱體之剖面示意圖。
第七a圖及第七b圖為本發明金屬柱體物性示意圖及俯視圖。
第八a圖為本發明形成第二聚合物層之剖面示意圖。
第八b圖為本發明形成第二聚合物層開口之剖面示意圖。
第八c圖為本發明研磨第二聚合物層之剖面示意圖。
第九圖為本發明形成第三聚合物層之剖面示意圖。
第十a圖至第十d圖為本發明形成第三金屬層之剖面示意圖。
第十一圖為本發明半導體基底進行切割之剖面示意圖。
第十二a圖至第十二c圖為本發明形成錫球之剖面示意圖。
第十二d圖至第十二e圖為本發明半導體基底進行切割及接合至基板之剖面示意圖。
第十三a圖及第十三b圖為本發明金屬柱體進行打線製程之剖面示意圖。
第十四a圖及第十四b圖為本發明形成重配置線路層在金屬柱體上之剖面示意圖。
第十五a圖至第十五c圖為本發明銅/鎳/金或銅/金之金屬柱體打線之剖面示意圖。
第十六a圖至第十六d圖為本發明形成第一線圈金屬層在金屬柱體上之剖面示意圖。
第十六e圖為本發明之第一線圈金屬層的俯視圖。
第十六f圖為本發明形成保護層在第一線圈金屬層上之剖面示意圖。
第十六g圖為本發明形成第二線圈金屬層之剖面示意圖。
第十六h圖為本發明形成電容元件在金屬柱體上之剖面示意圖。
第十七a圖至第十七d圖為本發明形成連接二金屬柱體之金屬層之剖面示意圖。
第十七e圖至第十七m圖為本發明形成多層線路層在金屬柱體上之剖面示意圖。
第十八圖為本發明形成電阻元件在金屬柱體上之剖面示意圖。
第十九a圖及第十九b圖為本發明利用蝕刻方式去除部分第二聚合物層之剖面示意圖。
第十九c圖為本發明半導體基底進行切割之剖面示意圖。
第十九d圖及第十九e圖為本發明形成錫球並進行切割步驟之剖面示意圖。
第十九f圖為本發明形成接墊之剖面示意圖。
第十九g圖至第十九k圖為本發明形成連接二金屬柱體之金屬層之剖面示意圖。
第二十a圖為本發明形成第九圖案化聚合物層在半導體基底上之剖面示意圖。
第二十b圖至第二十d圖為本發明以鑲嵌方式形成金屬柱體之剖面示意圖。
第二十一a圖至第二十一d圖為本發明形成凸塊、接墊、錫球、重配置線路層之結構剖示圖。
第二十二圖至第二十五圖為本發明形成快速電流通道(freeway)、線圈、電容元件、電阻元件之結構剖示圖。
30‧‧‧半導體基底
32‧‧‧電子元件
34‧‧‧細連線結構
36‧‧‧薄膜絕緣層
38‧‧‧細線路層
40‧‧‧導通孔
42‧‧‧保護層
46‧‧‧第一聚合物層
50‧‧‧第一黏著/阻障/種子層
60‧‧‧第一重配置線路層
68‧‧‧金屬柱體
70‧‧‧第二聚合物層
74‧‧‧第三聚合物層
76‧‧‧開口

Claims (99)

  1. 一種線路元件，包括：一矽基底；一第一介電層，位在該矽基底之上，且該第一介電層包括一第一上表面；一第一金屬線路層，位在該第一介電層內，該第一金屬線路層的材質包括電鍍銅，且該第一金屬線路層包括一第二上表面與該第一上表面共平面；一第二介電層，位在該第一介電層上以及位在該第一金屬線路層上；一第二金屬線路層，位在該第二介電層之上；一保護層，位在該第二金屬線路層之上，且該保護層包括一含氮化合物層；一第一聚合物層，位在該保護層之上；一第一金屬柱體，位在該第一聚合物層內，且該第一聚合物層接觸該第一金屬柱體的側壁；一第二金屬柱體，位在該第一聚合物層內，該第一聚合物層接觸該第二金屬柱體的側壁，該第一金屬柱體之中心點至該第二金屬柱體之中心點的距離係介於10微米至250微米之間，且該第一聚合物層的一第三上表面、該第一金屬柱體的一第四上表面與該第二金屬柱體的一第五上表面為共平面；以及一金屬層，位在該第一聚合物層之上以及直接位在該 第四上表面上。
  2. 如申請專利範圍第1項所述之線路元件，更包括複數電晶體位在該矽基底上。
  3. 如申請專利範圍第1項所述之線路元件，其中該第一介電層包括介電常數值小於3的材質。
  4. 如申請專利範圍第1項所述之線路元件，其中該含氮化合物層的厚度介於0.2微米至1.2微米之間。
  5. 如申請專利範圍第1項所述之線路元件，其中該含氮化合物層包括一氮化矽(silicon nitride)層。
  6. 如申請專利範圍第1項所述之線路元件，其中該保護層更包括一氧化矽(silicon oxide)層，且該氧化矽層位在該含氮化合物層之下。
  7. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體包括一金層。
  8. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體包括一銅層。
  9. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體包括一鎳層。
  10. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體包括一銅層與一鎳層，且該鎳層直接位在該銅層上。
  11. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體包括一銅層、一鎳層與一金層，且該鎳層直接位在該銅層上，該金層直接位在該鎳層上。
  12. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體包括一銅層與一金層，且該金層位在該銅層之上。
  13. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體的最大橫向寬度係介於3微米至50微米之間。
  14. 如申請專利範圍第1項所述之線路元件，其中該第二金屬柱體之最大橫向尺寸除以該第二金屬柱體之高度的比值小於4。
  15. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體之中心點至該第二金屬柱體之中心點的距離係介於10微米至200微米之間。
  16. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體之中心點至該第二金屬柱體之中心點的距離係介於10微米至175微米之間。
  17. 如申請專利範圍第1項所述之線路元件，其中該第一金屬柱體之中心點至該第二金屬柱體之中心點的距離係介於10微米至150微米之間。
  18. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括厚度介於400埃至7000埃之間的一濺鍍金屬層。
  19. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括一含鈦金屬層，且該含鈦金屬層位在該第一聚合物層之上以及直接位在該第四上表面上。
  20. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括一鈦鎢合金層，且該鈦鎢合金層位在該第一聚合物層之上以及直接位在該第四上表面上。
  21. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括一含鉭金屬層，且該含鉭金屬層位在該第一聚合物層之上以及直接位在該第四上表面上。
  22. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括厚度介於5微米至30微米之間的一電鍍金屬層。
  23. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括一金層。
  24. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括一銅層。
  25. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括一鎳層。
  26. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括一含錫金屬層。
  27. 如申請專利範圍第1項所述之線路元件，其中該金屬層包括一銅層、一鎳層與一含錫金屬層，其中該鎳層直接位在該銅層上，且該含錫金屬層直接位在該鎳層上。
  28. 如申請專利範圍第1項所述之線路元件，更包括一第二聚合物層直接位在該保護層上，且該第一聚合物層直接位在該第二聚合物層上。
  29. 如申請專利範圍第1項所述之線路元件，更包括一第二聚合物層直接位在該第一聚合物層上，且該金屬層直接位在該第二聚合物層上以及直接位在該第四上表面上。
  30. 如申請專利範圍第1項所述之線路元件，更包括一打線導線連接該金屬層。
  31. 如申請專利範圍第1項所述之線路元件，更包括一半導體晶片連接該金屬層。
  32. 如申請專利範圍第1項所述之線路元件，更包括一玻璃基板連接該金屬層。
  33. 一種線路元件，包括：一矽基底；一第一介電層，位在該矽基底之上，且該第一介電層包括一第一上表面；複數電晶體，位在該第一介電層之下；一第一金屬線路層，位在該第一介電層內，該第一金屬線路層的材質包括電鍍銅，且該第一金屬線路層包括一第二上表面與該第一上表面共平面；一第二介電層，位在該第一介電層上以及位在該第一金屬線路層上；一第二金屬線路層，位在該第二介電層之上；一第一接點，位在該第二金屬線路層之上，且該第一接點連接該第二金屬線路層；一第二接點，位在該第二金屬線路層之上，且該第二接點連接該第二金屬線路層；一含氮化合物層，位在該第二金屬線路層之上；一第一金屬層，位在該含氮化合物層之上以及位在該第一接點之上，該第一金屬層藉由通過該含氮化合物層內的一第一開口連接該第一接點，且該第一金屬層包括厚度介於2微米至30微米之間的一電鍍銅層； 一第二金屬層，位在該含氮化合物層之上以及位在該第二接點之上，該第二金屬層藉由通過該含氮化合物層內的一第二開口連接該第二接點，且該第一金屬層的一第三上表面與該第二金屬層的一第四上表面大致上為同一水平；一第一聚合物層，位在該第一金屬層之上、位在該第二金屬層之上以及位在該第一金屬層與該第二金屬層之間；一第一金屬柱體，位在該第一金屬層之上，該第一金屬柱體接觸該第一金屬層，該第一金屬柱體透過該第一金屬層連接該第一接點，該第一金屬柱體之最大橫向尺寸除以該第一金屬柱體之高度的比值小於3，該第一金屬柱體包括厚度介於10微米至100微米之間的一銅層、位在該銅層上的一鎳層以及位在該鎳層上的一金層；以及一第二金屬柱體，位在該第二金屬層之上，該第二金屬柱體接觸該第二金屬層，該第二金屬柱體透過該第二金屬層連接該第二接點，且該第一金屬柱體之中心點至該第二金屬柱體之中心點的距離係介於10微米至200微米之間。
  34. 如申請專利範圍第33項所述之線路元件，其中該第一介電層包括介電常數值小於3的材質。
  35. 如申請專利範圍第33項所述之線路元件，其中該第一介電層的材質包括矽與碳。
  36. 如申請專利範圍第33項所述之線路元件，其中該第一金屬層更包括位在該電鍍銅層之下的一含鈦金屬層。
  37. 如申請專利範圍第33項所述之線路元件，其中該第一金屬層更包括位在該電鍍銅層之下的一含鉭金屬層。
  38. 如申請專利範圍第33項所述之線路元件，其中該第一金屬層更包括位在該電鍍銅層之下的一氮化鈦層。
  39. 如申請專利範圍第33項所述之線路元件，其中該第一金屬層更包括位在該電鍍銅層之下的一鈦鎢合金層。
  40. 如申請專利範圍第33項所述之線路元件，更包括一第二聚合物層位在該含氮化合物層與該第一金屬層之間以及位在該含氮化合物層與該第二金屬層之間。
  41. 如申請專利範圍第33項所述之線路元件，其中該含氮化合物層包括厚度介於0.2微米至1.2微米之間的一氮化矽層。
  42. 如申請專利範圍第33項所述之線路元件，其中該鎳層的厚度介於1微米至10微米之間。
  43. 如申請專利範圍第33項所述之線路元件，其中該金層的厚度介於1微米至10微米之間。
  44. 一種線路元件，包括：一矽基底；一第一介電層，位在該矽基底之上，且該第一介電層包括一第一上表面；一第一金屬線路層，位在該第一介電層內，該第一金屬線路層的材質包括電鍍銅，且該第一金屬線路層包括 一第二上表面與該第一上表面共平面；一第二介電層，位在該第一介電層上以及位在該第一金屬線路層上；一第二金屬線路層，位在該第二介電層之上，且該第二金屬線路層連接該第一金屬線路層；一保護層，位在該第二金屬線路層之上，且該保護層包括一含氮化合物層；一第一聚合物層，位在該保護層之上；一第一金屬柱體，位在該第一聚合物層內，且該第一聚合物層接觸該第一金屬柱體的側壁；一第二金屬柱體，位在該第一聚合物層內，該第一聚合物層接觸該第二金屬柱體的側壁，該第一金屬柱體之中心點至該第二金屬柱體之中心點的距離係介於10微米至250微米之間，且該第一聚合物層的一第三上表面、該第一金屬柱體的一第四上表面與該第二金屬柱體的一第五上表面為共平面；一金屬層，位在該第一聚合物層之上以及直接位在該第四上表面上；以及一電路元件，連接該金屬層。
  45. 如申請專利範圍第44項所述之線路元件，其中該第一介電層包括介電常數值小於3的材質。
  46. 如申請專利範圍第44項所述之線路元件，其中該保護層更包括一氧化矽層，且該氧化矽層位在該含氮化合物層之下。
  47. 如申請專利範圍第44項所述之線路元件，其中該第一金屬柱體包括一金層。
  48. 如申請專利範圍第44項所述之線路元件，其中該第一金屬柱體包括一銅層。
  49. 如申請專利範圍第44項所述之線路元件，其中該第一金屬柱體包括一鎳層。
  50. 如申請專利範圍第44項所述之線路元件，其中該第一金屬柱體包括一銅層與一鎳層，且該鎳層直接位在該銅層上。
  51. 如申請專利範圍第44項所述之線路元件，其中該第一金屬柱體包括一銅層、一鎳層與一金層，且該鎳層直接位在該銅層上，該金層直接位在該鎳層上。
  52. 如申請專利範圍第44項所述之線路元件，其中該第一金屬柱體包括一銅層與一金層，且該金層位在該銅層之上。
  53. 如申請專利範圍第44項所述之線路元件，其中該第一金屬柱體的最大橫向寬度係介於3微米至50微米之間。
  54. 如申請專利範圍第44項所述之線路元件，其中該第二金屬柱體之最大橫向尺寸除以該第二金屬柱體之高度的比值小於4。
  55. 如申請專利範圍第44項所述之線路元件，其中該第一金屬柱體之中心點至該第二金屬柱體之中心點的距離係介於10微米至175微米之間。
  56. 如申請專利範圍第44項所述之線路元件，其中該金屬層包括一含鈦金屬層，且該含鈦金屬層位在該第一聚合物 層之上以及直接位在該第四上表面上。
  57. 如申請專利範圍第44項所述之線路元件，其中該金屬層包括一鈦鎢合金層，且該鈦鎢合金層位在該第一聚合物層之上以及直接位在該第四上表面上。
  58. 如申請專利範圍第44項所述之線路元件，其中該金屬層包括一含鉭金屬層，且該含鉭金屬層位在該第一聚合物層之上以及直接位在該第四上表面上。
  59. 如申請專利範圍第44項所述之線路元件，其中該金屬層包括厚度介於5微米至30微米之間的一電鍍金屬層。
  60. 如申請專利範圍第44項所述之線路元件，其中該金屬層包括一金層。
  61. 如申請專利範圍第44項所述之線路元件，其中該金屬層包括一銅層。
  62. 如申請專利範圍第44項所述之線路元件，其中該金屬層包括一鎳層。
  63. 如申請專利範圍第44項所述之線路元件，其中該金屬層包括一含錫金屬層。
  64. 如申請專利範圍第44項所述之線路元件，其中該金屬層包括一銅層、一鎳層與一含錫金屬層，其中該鎳層直接位在該銅層上，且該含錫金屬層直接位在該鎳層上。
  65. 如申請專利範圍第44項所述之線路元件，更包括一第二聚合物層直接位在該保護層上，且該第一聚合物層直接位在該第二聚合物層上。
  66. 如申請專利範圍第44項所述之線路元件，更包括一第 二聚合物層直接位在該第一聚合物層上，且該金屬層直接位在該第二聚合物層上以及直接位在該第四上表面上。
  67. 如申請專利範圍第44項所述之線路元件，其中該電路元件為一印刷電路板。
  68. 如申請專利範圍第44項所述之線路元件，其中該電路元件為一陶瓷基板。
  69. 一種線路元件，包括：一矽基底；一第一介電層，位在該矽基底之上，且該第一介電層包括一第一上表面；一第一金屬線路層，位在該第一介電層內，該第一金屬線路層的材質包括電鍍銅，且該第一金屬線路層包括一第二上表面與該第一上表面共平面；一第二介電層，位在該第一介電層上以及位在該第一金屬線路層上；一第二金屬線路層，位在該第二介電層之上，且該第二金屬線路層連接該第一金屬線路層；一保護層，位在該第二金屬線路層之上，且該保護層包括一含氮化合物層；一第一聚合物層，位在該保護層之上；一第一金屬柱體，位在該第一聚合物層內，且該第一聚合物層接觸該第一金屬柱體的側壁；一第二金屬柱體，位在該第一聚合物層內，該第一聚合物層接觸該第二金屬柱體的側壁，該第一金屬柱體之 中心點至該第二金屬柱體之中心點的距離係介於10微米至250微米之間，且該第一聚合物層的一第三上表面、該第一金屬柱體的一第四上表面與該第二金屬柱體的一第五上表面為共平面；一第一含錫金屬層，位在該第四上表面之上；以及一第二含錫金屬層，位在該第五上表面之上。
  70. 如申請專利範圍第69項所述之線路元件，其中該第一介電層包括介電常數值小於3的材質。
  71. 如申請專利範圍第69項所述之線路元件，其中該保護層更包括一氧化矽層，且該氧化矽層位在該含氮化合物層之下。
  72. 如申請專利範圍第69項所述之線路元件，其中該第一金屬柱體包括一金層。
  73. 如申請專利範圍第69項所述之線路元件，其中該第一金屬柱體包括一銅層。
  74. 如申請專利範圍第69項所述之線路元件，其中該第一金屬柱體包括一鎳層。
  75. 如申請專利範圍第69項所述之線路元件，其中該第一金屬柱體的最大橫向寬度係介於3微米至50微米之間。
  76. 如申請專利範圍第69項所述之線路元件，其中該第二金屬柱體之最大橫向尺寸除以該第二金屬柱體之高度的比值小於4。
  77. 如申請專利範圍第69項所述之線路元件，其中該第一金屬柱體之最大橫向尺寸除以該第一金屬柱體之高度的比 值小於3。
  78. 如申請專利範圍第69項所述之線路元件，其中該第一金屬柱體之中心點至該第二金屬柱體之中心點的距離係介於10微米至175微米之間。
  79. 如申請專利範圍第69項所述之線路元件，更包括一含鈦金屬層位在該第一含錫金屬層與該第四上表面之間。
  80. 如申請專利範圍第69項所述之線路元件，更包括一鈦鎢合金層位在該第一含錫金屬層與該第四上表面之間。
  81. 如申請專利範圍第69項所述之線路元件，更包括一含鉭金屬層位在該第一含錫金屬層與該第四上表面之間。
  82. 如申請專利範圍第69項所述之線路元件，更包括一濺鍍金屬層位在該第一含錫金屬層與該第四上表面之間。
  83. 如申請專利範圍第69項所述之線路元件，更包括一第二聚合物層直接位在該保護層上，且該第一聚合物層直接位在該第二聚合物層上。
  84. 如申請專利範圍第69項所述之線路元件，更包括一第二聚合物層直接位在該第一聚合物層上。
  85. 一種線路元件，包括：一矽基底；一介電層，位在該矽基底之上；一金屬線路層，位在該矽基底之上；一第一接點，位在該金屬線路層之上，且該第一接點連接該金屬線路層；一第二接點，位在該金屬線路層之上，且該第二接點 連接該金屬線路層；一保護層，位在該金屬線路層之上；一第一金屬層，位在該保護層之上以及位在該第一接點之上，且該第一金屬層藉由通過該保護層內的一第一開口連接該第一接點；一第二金屬層，位在該保護層之上以及位在該第二接點之上，且該第二金屬層藉由通過該保護層內的一第二開口連接該第二接點；一第一金屬柱體，位在該第一金屬層之上，且該第一金屬柱體透過該第一金屬層連接該第一接點；以及一第二金屬柱體，位在該第二金屬層之上，該第二金屬柱體透過該第二金屬層連接該第二接點，且該第一金屬柱體之中心點至該第二金屬柱體之中心點的距離係介於10微米至250微米之間。
  86. 如申請專利範圍第85項所述之線路元件，其中該第一金屬柱體包括一銅層。
  87. 如申請專利範圍第85項所述之線路元件，其中該第一金屬柱體包括一金層。
  88. 如申請專利範圍第85項所述之線路元件，其中該第一金屬柱體包括一銅層與一金層，且該金層位在該銅層之上。
  89. 如申請專利範圍第85項所述之線路元件，其中該第一金屬柱體包括一銅層與一鎳層，且該鎳層位在該銅層上。
  90. 如申請專利範圍第85項所述之線路元件，其中該第一金屬柱體包括一銅層、一鎳層與一金層，且該鎳層位在該 銅層上，該金層位在該鎳層上。
  91. 如申請專利範圍第85項所述之線路元件，更包括一含錫金屬層位在該第一金屬柱體之上。
  92. 如申請專利範圍第85項所述之線路元件，其中該金屬線路層的材質包括電鍍銅。
  93. 如申請專利範圍第85項所述之線路元件，其中該第一金屬層包括厚度介於2微米至30微米之間的一金層。
  94. 如申請專利範圍第85項所述之線路元件，其中該第一金屬層包括厚度介於2微米至30微米之間的一銅層。
  95. 如申請專利範圍第85項所述之線路元件，其中該第一金屬層包括一電鍍銅層。
  96. 如申請專利範圍第85項所述之線路元件，更包括一聚合物層位在該第一金屬柱體與該第二金屬柱體之間。
  97. 如申請專利範圍第85項所述之線路元件，更包括一聚合物層位在該第一金屬層與該第二金屬層之間。
  98. 如申請專利範圍第85項所述之線路元件，其中該保護層包括一含氮化合物層。
  99. 如申請專利範圍第85項所述之線路元件，更包括一電路板連接該第一金屬柱體與該第二金屬柱體。
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