CN110544679B - 芯片重布线结构及其制备方法 - Google Patents

芯片重布线结构及其制备方法 Download PDF

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CN110544679B
CN110544679B CN201910811918.7A CN201910811918A CN110544679B CN 110544679 B CN110544679 B CN 110544679B CN 201910811918 A CN201910811918 A CN 201910811918A CN 110544679 B CN110544679 B CN 110544679B
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window
wiring layer
layer
chip
pin
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CN110544679A (zh
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许冠猛
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Hefei Qizhong Technology Co ltd
Chipmore Technology Corp Ltd
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Beijing Eswin Technology Co Ltd
Chipmore Technology Corp Ltd
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Priority to CN201910811918.7A priority Critical patent/CN110544679B/zh
Priority to KR1020217041153A priority patent/KR102646248B1/ko
Priority to US17/622,683 priority patent/US20220254719A1/en
Priority to PCT/CN2019/119964 priority patent/WO2021036027A1/zh
Priority to JP2021576131A priority patent/JP7320633B2/ja
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Abstract

本发明提供了一种芯片重布线结构及其制备方法，所述芯片重布线结构包括芯片本体、连接所述芯片本体的第一布线层与第二布线层，所述芯片本体表面设有第一引脚与第二引脚，所述芯片重布线结构还包括设置在所述芯片本体表面的介电层，所述介电层向下凹陷形成有第一窗口、第二窗口及连通第一窗口的凹槽，所述第一窗口、第二窗口分别对应于所述第一引脚、第二引脚，所述第一布线层沿所述凹槽延伸设置且与所述第一引脚相连通，所述第二布线层设置在所述介电层上方且与所述第二引脚相连通。本申请通过设有凹槽的介电层使得第一布线层、第二布线层沿高度方向错位设置，克服现有重布线工艺的尺寸限制，能够提高重布线密度，并降低短路风险。

Description

芯片重布线结构及其制备方法
技术领域
本发明涉及一种半导体制造技术领域，尤其涉及一种芯片重布线结构及其制备方法。
背景技术
随着半导体行业持续发展，各类电子产品所涉及芯片的集成密度要求也不断提高。封装过程中，芯片表面由顶层金属(top metal)构成的引脚通常需采用重布线层(RDL，redistribution layer)重新分配连接至相应的导电凸块。RDL自身的线路尺寸以及不同的RDL的间隙受实际工艺能力限制，无法持续减小，也就是说芯片表面RDL的布线密度不能无限制提高。
此种状况下，业内一般采用多层布线的方式进行RDL制备，即在相应的重布线层上制备介电层，再于该介电层上制得另一重布线层。上述方案需在介电层上方重新制备金属种子层，并在相应重布线层制备完成后蚀刻清除多余的金属种子层，工艺较复杂。
鉴于此，有必要提供一种新的芯片重布线结构及其制备方法。
发明内容
本发明的目的在于提供一种芯片重布线结构及其制备方法，能够克服重布线层的工艺限制，提高芯片表面的重布线密度，降低短路风险。
为实现上述目的，本发明提供了一种芯片重布线结构，包括芯片本体、连接所述芯片本体的第一布线层与第二布线层，所述芯片本体表面设有第一引脚与第二引脚，所述芯片重布线结构还包括设置在所述芯片本体上的介电层，所述介电层向下凹陷形成有第一窗口、第二窗口及连通第一窗口的凹槽，所述第一窗口、第二窗口分别对应于所述第一引脚、第二引脚，所述第一布线层沿所述凹槽延伸设置且与所述第一引脚相连通，所述第二布线层设置在所述介电层上方且与所述第二引脚相连通。
作为本发明的进一步改进，所述芯片重布线结构还包括金属种子层，所述第一布线层、第二布线层均设置在所述金属种子层上。
作为本发明的进一步改进，所述第一布线层包括设置在所述凹槽内的第一主体部、连接所述第一主体部且位于所述第一窗口内的第一连接部；所述第二布线层包括设置在所述介电层的顶面上的第二主体部、连接所述第二主体部且位于所述第二窗口内的第二连接部。
作为本发明的进一步改进，所述第一布线层向上不超出所述凹槽的开口位置。
作为本发明的进一步改进，所述第一布线层、第二布线层两者采用同样的材料制得。
作为本发明的进一步改进，所述芯片本体包括半导体衬底、形成于所述半导体衬底表面的线路层、覆设在所述线路层上的保护层，所述第一引脚、第二引脚连接至所述线路层。
本申请还提供一种芯片重布线结构的制备方法，主要包括：
提供芯片本体，所述芯片本体表面设有第一引脚与第二引脚；
在所述芯片本体表面制备介电层，所述介电层具有对应第一引脚的第一窗口、对应第二引脚的第二窗口以及连通第一窗口的凹槽；
涂布第一光刻胶，并经曝光、显影使得所述第一窗口与凹槽向外暴露，在所述第一窗口与凹槽内制得第一布线层；
涂布第二光刻胶，并经曝光、显影使得第二窗口与介电层既定区域的顶面向外暴露，在所述第二窗口及向外暴露的顶面上制得第二布线层。
作为本发明的进一步改进，涂布第一光刻胶前，在所述介电层的顶面以及所述第一窗口、第二窗口、凹槽内溅镀得到金属种子层，所述第一布线层、第二布线层均设置在所述金属种子层上。
作为本发明的进一步改进，涂布第一光刻胶后，经曝光、显影使得所述第二窗口与第一窗口、凹槽均向外暴露。
作为本发明的进一步改进，所述第一布线层、第二布线层均采用电镀工艺制得。
本发明的有益效果是：采用本发明芯片重布线结构及其制备方法，所述芯片本体上设置介电层，并在所述介电层上开设凹槽，再将所述第一布线层、第二布线层分别设置在所述凹槽内与介电层的顶面上，也就是说，通过将所述第一布线层、第二布线层沿高度方向进行错位设置，以便于减小两者沿水平方向的间隙，克服了现有重布线工艺的尺寸限制，能够提高重布线密度，并降低短路风险。
附图说明
图1是本发明芯片重布线结构的结构示意图；
图2是本发明芯片重布线结构的平面结构示意图；
图3是本发明芯片重布线结构制备方法的主要流程示意图；
图4是本发明芯片重布线结构中金属种子层制备完成时的结构示意图；
图5是本发明芯片重布线结构中第一布线层制备完成时的结构示意图；
图6是本发明芯片重布线结构中第二布线层制备完成时的结构示意图；
图7是本发明芯片重布线结构制备方法的另一实施例中第一布线层制备完成时的结构示意图；
图8是本发明芯片重布线结构制备方法的另一实施例中第二布线层制备完成时的结构示意图。
具体实施方式
以下将结合附图所示的实施方式对本发明进行详细描述。但该实施方式并不限制本发明，本领域的普通技术人员根据该实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
如图1与图2所示，本发明提供的芯片重布线结构100包括芯片本体10、设置在所述芯片本体10上的介电层20、连接所述芯片本体10的第一布线层31与第二布线层32。
所述芯片本体10表面设有第一引脚11与第二引脚12，所述介电层20向下凹陷形成有第一窗口21、第二窗口22及连通第一窗口21的凹槽23。所述第一窗口21、第二窗口22分别对应于所述第一引脚11、第二引脚12。所述第一布线层31沿所述凹槽23延伸设置且与所述第一引脚11相连通，所述第二布线层32设置在所述介电层20上方且与所述第二引脚12相连通。所述第一布线层31、第二布线层32两者采用同样的材料制得，通常优选采用金属铜制备得到所述第一布线层31与第二布线层32。当然，根据实际产品需求，所述第一布线层31、第二布线层32两者也可采用不同的材料成型制备；进一步地，所述第一布线层31、第二布线层32还可采用两种或多种不同导电材料共同制得，如将所述第二布线层32设置为Cu/Ni/Au三层结构。
其中，所述介电层20还具有沿水平方向大致呈平面延伸的顶面24。所述第一布线层31包括设置在所述凹槽23内的第一主体部311、连接所述第一主体部311且位于所述第一窗口11内的第一连接部312、以及位于所述第一主体部311背离所述第一连接部312一端的第一配合部313。所述第一主体部311优选为不超出所述凹槽23的开口位置，也就是说，所述第一主体部311沿高度方向不超出所述介电层20的顶面24。所述第二布线层32包括设置在所述顶面24上的第二主体部321、连接所述第二主体部321且位于所述第二窗口12内的第二连接部322、位于所述第二主体部321背离所述第二连接部322一端的第二配合部323。此处，所述第一配合部313、第二配合部323两者均设置在所述介电层20的顶面24上，所述第一配合部313、第二配合部323用以配合制备相应的导电凸块，以实现后续封装。
本实施例中，所述芯片本体10包括半导体衬底101、形成于所述半导体衬底101表面的线路层102、覆设在所述线路层102上的保护层103，所述第一引脚11、第二引脚12均连接至所述线路层102。显然地，所述保护层103具有对应所述第一引脚11、第二引脚12设置的开口，以使得所述线路层102可与外部进行配合连接。
所述芯片重布线结构100还包括金属种子层40，所述第一布线层31、第二布线层32均设置在所述金属种子层40上。此处，所述第一布线层31、第二布线层32形成在同一所述金属种子层40上，并在第一布线层31与第二布线层32两者均制备完成后，再蚀刻去除第一布线层31、第二布线层32未覆盖区域的金属种子层40，工艺更为简洁。所述第一布线层31、第二布线层32在高度方向间隙设置，使得两者在水平方向的间隙可以进一步缩小，突破现有工艺的限制。换言之，所述芯片本体10表面的重布线密度能够得以提高，并可降低不同布线层之间的短路风险。
需要说明的是，前文中“水平”、“上下”、“高度”等方向描述并非对该芯片重布线结构100的制备工艺与安置方位的限定，而仅为更清楚的说明其结构位置关系所作的描述。
结合图3至图6所示，本申请还提供一种前述芯片重布线结构100的制备方法，主要包括：
提供芯片本体10，所述芯片本体表面设有第一引脚11与第二引脚12；
在所述芯片本体10表面制备介电层20，所述介电层20具有对应第一引脚11的第一窗口21、对应第二引脚12的第二窗口22以及连通第一窗口21的凹槽23；
在所述介电层20的顶面24以及所述第一窗口21、第二窗口22、凹槽23内溅镀金属种子层40；
涂布第一光刻胶50，并经曝光、显影使得所述第一窗口21与凹槽23向外暴露，在所述第一窗口21与凹槽23内制得第一布线层31，当然，第一布线层31还包括延伸设置在所述顶面24既定位置的第一配合部313；
涂布第二光刻胶60，并经曝光、显影使得第二窗口22与介电层20既定区域的顶面24向外暴露，在所述第二窗口22及向外暴露的顶面24上制得第二布线层32，第二布线层32还包括延伸设置在所述顶面24既定位置的第二配合部323。
此处，所述介电层20多采用绝缘树脂材料制得，所述第一窗口21、第二窗口22及凹槽23的制备过程中，其侧壁自下向上形成有一定程度向外倾斜的角度，利于所述金属种子层40、第一布线层31、第二布线层32的制备与结构稳定性。
所述第一布线层31、第二布线层32均采用电镀工艺制得。所述制备方法还包括：在所述第一布线层31制备完成后，去除第一光刻胶50；在所述第二布线层32制备完成后，去除第二光刻胶60及第一布线层31、第二布线层32未覆盖区域的金属种子层40。
参图7与图8所示，所述涂布第一光刻胶50后，经曝光、显影使得所述第二窗口22与第一窗口21、凹槽23均向外暴露。也就是说，在进行所述第一布线层31的制备的同时，在所述第二窗口22的第二引脚12上同样电镀得导一层与所述第一布线层31相同的导电材料。在后续第二布线层32的制备过程中，降低所述第二主体部321与第二连接部322的高度差，所述第一布线层31与第二布线层32优选采用同一导电材料电镀制得。
综上，采用本发明芯片重布线结构100及其制备方法，通过在所述芯片本体10上设置介电层20，并在所述介电层20上开设凹槽23，再将所述第一主体部311、第二主体部321分别设置在所述凹槽23内与介电层20的顶面24上，通过高度方向的错位设置，减小两者沿水平方向的间隙，克服了现有重布线工艺的尺寸限制，能够提高重布线密度，并降低短路风险。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (9)

1.一种芯片重布线结构，包括芯片本体、连接所述芯片本体的第一布线层与第二布线层，所述芯片本体表面设有第一引脚与第二引脚，其特征在于：所述芯片重布线结构还包括设置在所述芯片本体上的介电层，所述介电层向下凹陷形成有第一窗口、第二窗口及连通第一窗口的凹槽，所述第一窗口、第二窗口分别对应于所述第一引脚、第二引脚，所述第一布线层沿所述凹槽延伸设置且与所述第一引脚相连通，所述第一布线层包括设置在所述凹槽内的第一主体部、连接所述第一主体部且位于所述第一窗口内的第一连接部，所述第一主体部不超出所述凹槽的开口位置；所述第二布线层设置在所述介电层上方且与所述第二引脚相连通。
2.根据权利要求1所述的芯片重布线结构，其特征在于：所述芯片重布线结构还包括金属种子层，所述第一布线层、第二布线层均设置在所述金属种子层上。
3.根据权利要求1所述的芯片重布线结构，其特征在于：所述第二布线层包括设置在所述介电层的顶面上的第二主体部、连接所述第二主体部且位于所述第二窗口内的第二连接部。
4.根据权利要求1所述的芯片重布线结构，其特征在于：所述第一布线层、第二布线层两者采用同样的材料制得。
5.根据权利要求1所述的芯片重布线结构，其特征在于：所述芯片本体包括半导体衬底、形成于所述半导体衬底表面的线路层、覆设在所述线路层上的保护层，所述第一引脚、第二引脚连接至所述线路层。
6.一种芯片重布线结构的制备方法，其特征在于：
提供芯片本体，所述芯片本体表面设有第一引脚与第二引脚；
在所述芯片本体表面制备介电层，所述介电层具有对应第一引脚的第一窗口、对应第二引脚的第二窗口以及连通第一窗口的凹槽；
涂布第一光刻胶，并经曝光、显影使得所述第一窗口与凹槽向外暴露，在所述第一窗口与凹槽内制得第一布线层，其中，所述第一布线层包括设置在所述凹槽内的第一主体部、连接所述第一主体部且位于所述第一窗口内的第一连接部，控制所述第一主体部不超出所述凹槽的开口位置；
涂布第二光刻胶，并经曝光、显影使得第二窗口与介电层既定区域的顶面向外暴露，在所述第二窗口及向外暴露的顶面上制得第二布线层。
7.根据权利要求6所述的制备方法，其特征在于：涂布第一光刻胶前，在所述介电层的顶面以及所述第一窗口、第二窗口、凹槽内溅镀得到金属种子层，所述第一布线层、第二布线层均设置在所述金属种子层上。
8.根据权利要求6所述的制备方法，其特征在于：涂布第一光刻胶后，经曝光、显影使得所述第二窗口与第一窗口、凹槽均向外暴露。
9.根据权利要求6所述的制备方法，其特征在于：所述第一布线层、第二布线层均采用电镀工艺制得。
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CN110544679A (zh) 2019-12-06
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