CN203536403U - Esd保护器件 - Google Patents

Esd保护器件 Download PDF

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Publication number
CN203536403U
CN203536403U CN201190000602.7U CN201190000602U CN203536403U CN 203536403 U CN203536403 U CN 203536403U CN 201190000602 U CN201190000602 U CN 201190000602U CN 203536403 U CN203536403 U CN 203536403U
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China
Prior art keywords
electrode
esd protection
protection device
terminal electrode
input
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Expired - Lifetime
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CN201190000602.7U
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English (en)
Inventor
加藤登
佐佐木纯
山田浩辅
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Abstract

本实用新型提供了一种ESD保护器件(101)，包括：具有输入输出电极(21A、21B)等的半导体基板(20)和形成在其表面上的再布线层(30)。在半导体基板(20)的表层形成有ESD保护电路，输入输出电极(21A，21B)与该ESD保护电路连接。再布线层(30)包括层间布线(24A、24B)、面内布线(25A、25B)及柱电极(27A、27B)。设置在厚度方向上的层间布线(24A、24B)的一端与设置在半导体基板(20)表面上的输入输出电极(21A、21B)连接，另一端与在平面方向上走线的面内布线(25A、25B)的一端连接。而且，第一及第二柱电极(27A，27B)的中心间距离(A)大于第一及第二输入输出电极(21A，21B)的中心间距离(B)。

Description

ESD保护器件
技术领域
本发明涉及保护半导体IC等使其不受静电影响的ESD保护器件，尤其涉及功能部分构成在硅基板上的CSP型ESD保护器件。 
背景技术
在以移动通信终端、数码相机、笔记本电脑为代表的各种电器设备中，具备构成逻辑电路、存储电路等的半导体集成电路(IC芯片)。由于上述半导体集成电路是由形成在半导体基板上的微细布线图案所构成的恒压驱动电路，因此，通常对于浪涌那样的静电放电较为脆弱。因此，使用ESD(Electro-Static-Discharge：静电释放)保护器件来保护上述半导体集成电路不受静电放电影响。 
如专利文献1～4中所记载的那样，ESD保护器件由形成在半导体基板上、包括二极管的ESD保护电路所构成。ESD保护电路中的二极管的保护动作利用了对二极管施加反向电压时的击穿现象，击穿电压即为动作电压。 
专利文献4中揭示了将ESD保护器件构成作为表面安装器件的例子。这里，利用图1对专利文献4的ESD保护器件的结构进行说明。图1是构成专利文献4的ESD保护器件的半导体装置的剖视图。该半导体装置包括硅基板(半导体基板)1。硅基板1的上表面中央部设置有集成电路，在上表面周边部设置有多个连接焊盘2，该连接焊盘2与集成电路连接。除连接焊盘2的中央部以外，在硅基板1的上表面设置有由氧化硅形成的绝缘膜3，连接焊盘2的中央部经由绝缘膜3所设置的开口部4露出。 
在绝缘膜3的上表面设置有由聚酰亚胺等有机树脂形成的保护膜(绝缘膜)5。在保护膜5的与绝缘膜3的开口部4相对应的部分设置有开口部6。在保护膜5上表面的再布线形成区域设置有凹部7。凹部7与开口部6连通。 
从经由两开口部4、6露出的连接焊盘2的上表面到保护膜5的凹部7内上 表面的规定部位设置有由底层金属层8a及设置在该底层金属层8a上的上层金属层8b所形成的再布线8。 
在再布线8的连接焊盘部上表面设置有柱状电极10。在包括再布线8的保护膜5的上表面设置有密封膜11，使得该密封膜11的上表面与柱状电极10的上表面成为同一平面。在柱状电极10的上表面设置有焊球12。 
现有技术文献 
专利文献 
专利文献1：日本专利特开平4-146660号公报 
专利文献2：日本专利特开2001-244418号公报 
专利文献3：日本专利特开2007-013031号公报 
专利文献4：日本专利特开2004-158758号公报 
发明内容
发明所要解决的技术问题 
然而，若将上述ESD保护器件置于高频电路中，会有如下问题：受到二极管寄生电容的影响。即，将ESD器件插入信号线路会导致阻抗由于二极管的寄生电容的影响而产生偏移，其结果可能会导致信号损失。特别是在高频电路所使用的ESD保护器件中，要求寄生电容较小，以防止使与之相连的信号线路和保护对象即集成电路的高频特性下降。 
然而，在图1所示那样的现有的ESD保护器件中，除了二极管的寄生电容以外，还会在电极间产生结构上的寄生电容，这可能会导致ESD保护器件本身电容的增加。 
本发明的目的在于提供一种ESD保护器件，该ESD保护器件能减轻由二极管的寄生电容所带来的影响并抑制电路特性的劣化。 
解决技术问题所采用的技术方案 
本发明的ESD保护器件包括：半导体基板，该半导体基板上形成有包括二极管的ESD保护电路、和与所述ESD保护电路导通的第一及第二输入输出电极；以及 
再布线层，该再布线层包括与所述第一输入输出电极和第一端子电极 导通的柱状的第一柱电极、和与所述第二输入输出电极和第二端子电极导通的柱状的第二柱电极， 
所述第一及第二柱电极的中心间距离大于所述第一及第二输入输出电极的中心间距离。 
例如，所述第一柱电极和所述第二柱电极之间的最短距离大于所述第一及第二输入输出电极的中心间距离。 
此外，所述再布线层包括形成在内层的第一及第二面内布线、以及分别将该第一及第二面内布线和所述第一及第二输入输出电极连接起来的第一及第二层间布线，所述第一柱电极将所述第一面内布线和所述第一端子电极之间连接，所述第二柱电极将所述第二面内布线和所述第二端子电极之间连接。 
优选所述第一及第二柱电极的与中心轴正交的面上的、所述端子电极一侧的截面积大于所述输入输出电极一侧的截面积。 
例如，所述第一及第二柱电极的所述截面积包括从所述输入输出电极向所述端子电极呈连续或阶梯状地增大的形状。 
此外，本发明的ESD保护器件在例如所述半导体基板的由第一侧面和与该第一侧面相邻的第三、第四侧面所构成的两个角部的附近的再布线层上，分别包括与第一信号线连接的第一端子电极及与第二信号线连接的第二端子电极， 
在所述半导体基板的由与所述第一侧面相对的第二侧面和与该第二侧面相邻的第三、第四侧面所构成的两个角部的附近的再布线层上，分别包括与电源线连接的第三端子电极及与接地线连接的第四端子电极， 
所述ESD保护电路分别连接在第一端子电极和第三端子电极之间、第一端子电极和第四端子电极之间、第二端子电极和第三端子电极之间、及第二端子电极和第四端子电极之间。 
发明效果 
根据本发明，能将柱电极间的寄生电容抑制在最小限度，并能实现寄生电容较小且高频特性优良的ESD保护器件。 
附图说明
图1是构成专利文献4的ESD保护器件的半导体装置的剖视图。 
图2A是实施方式1所涉及的ESD保护器件101的主要部分的剖视图。 
图2B是ESD保护器件101的俯视图。 
图3是ESD保护器件101的立体图。 
图4A是表示图2A所示的ESD保护器件101的柱电极尺寸和面内布线的焊盘尺寸的图。 
图4B是比较例的图。 
图5是应用了实施方式1所涉及的ESD保护器件101的电路图的示例。 
图6是将其应用于天线部分时的电路图的示例。 
图7A是表示ESD保护器件101和安装对象即印刷布线板的结构的图。 
图7B是表示ESD保护器件101对印刷布线板的安装状态的结构的图。 
图8A是实施方式2所涉及的ESD保护器件102的主要部分的剖视图。 
图8B是实施方式2所涉及的ESD保护器件102的从安装面侧进行观察时的俯视图。 
图9是ESD保护器件102的电路图。 
图10A是表示ESD保护器件102和安装对象即印刷布线板的结构的图。 
图10B是表示ESD保护器件102对印刷布线板的安装状态的结构的图。 
图11是实施方式3所涉及的ESD保护器件103的主要部分的剖视图。 
具体实施方式
实施方式1 
下面参照各图对实施方式1所涉及的ESD保护器件进行说明。 
图2A是实施方式1所涉及的ESD保护器件101的主要部分的剖视图。图2B是ESD保护器件101的俯视图。图3是ESD保护器件101的立体图。 
如图2A所示，ESD保护器件101包括：具有输入输出电极21A、21B的半导体基板20和形成在其表面上的再布线层30。虽然图2A中没有示出，但半导体基板20的表层形成有ESD保护电路，且输入输出电极21A、21B与该ESD保护电路连接。再布线层30包括层间布线24A、24B、面内布线25A、 25B及柱电极27A、27B。 
设置在厚度方向上的层间布线24A、24B的一端与设置在半导体基板20的表面上的输入输出电极21A、21B连接，另一端与在平面方向上走线的面内布线25A、25B的一端连接。面内布线25A、25B的另一端与设置在厚度方向上的柱电极27A、27B的一端连接。 
如图2B所示，ESD保护器件101的上表面侧形成有两个矩形的端子电极28A、28B。即，ESD保护器件101的上表面形状形成为具有长边(尺寸：L1)及短边(尺寸：W1)的长方形，且端子电极28A、28B也形成为具有长边(尺寸：W2)及短边(尺寸：L2)的长方形。端子电极28A、28B的短边形成为与ESD保护器件的长边平行，且端子电极28A、28B的长边形成为与ESD保护器件101的端面平行。 
ESD保护器件101包括肖特基势垒二极管等二极管，且该二极管与输入输出电极21A、21B连接。各输入输出电极构成作为铝的焊盘(Al焊盘)。在半导体基板20的形成有ESD保护电路的表面上，设置有由SiO2形成的无机绝缘层22，该无机绝缘层22中，在设置有Al焊盘的部分形成有开口部。在该开口部及该开口部的周边区域，形成有由Ti及Cu形成的UBM(Under Bump Metal：凸点下金属)层，该UBM层构成层间布线24A、24B。在UBM层的表面设置有由Cu形成的面内布线25A、25B。面内布线25A、25B以如下方式进行走线：即，相邻的柱电极27A、27B配置在相互离开的方向上。 
在面内布线25A、25B和无机绝缘层22之间，通过聚酰亚胺形成有用于提高UBM层和无机绝缘层22的附着性的绝缘粘接层23A、23B。 
对于面内布线25A、25B，若以第一区域表示各自的第一端，以第二区域表示各自的第二端，则第一区域是与层间布线24A、24B连接的区域，第二区域是与柱电极27A、27B连接的区域。各个柱电极27A、27B在由环氧类树脂形成的有机绝缘膜26中直立成柱状，并在垂直于半导体基板20的主面的方向上延伸设置。 
第一柱电极27A和第二柱电极27B以如下方式配置：即，两柱电极的中心之间的距离A大于第一输入输出电极21A和第二输入输出电极21B的中心之间的距离B。 
由此，通过使相邻的第一及第二柱电极27A-27B之间的距离大于相邻的第一及第二输入输出电极21A-21B之间的距离，能将柱电极27A-27B之间的寄生电容抑制到最小限度，并能实现寄生电容较小、高频特性优良的ESD保护器件。 
此外，通过将层间布线24A、24B和柱电极27A、27B配置成在俯视下不产生重叠，使得即使将该ESD保护器件101直接装载到印刷布线板那样的母基板上，来自母基板的热应力、掉落冲击也很难直接对ESD保护器件101产生影响。 
在该ESD保护器件101中，第一及第二柱电极27A、27B以如下方式配置：即，两个柱电极的最大宽度大于第一及第二层间布线24A、24B的直径，而且，各个柱电极27A、27B之间的最短距离C大于第一及第二输入输出电极21A、21B的中心间距离B。利用该结构，能使柱电极27A、27B间产生的寄生电容小于等于层间布线24A、24B间产生的寄生电容。因此，抑制了设置柱电极27A、27B所导致的寄生电容的增加。 
如图2A、图2B、图3所示，柱电极27A、27B在面内布线25A、25B一侧的面积较小，在端子电极28A、28B一侧的面积较大，因此柱电极与延伸方向(厚度方向)平行的截面形状为梯形。下面基于图4A、图4B对该形状的效果进行说明。图4A是表示图2A所示的ESD保护器件101的柱电极尺寸和面内布线的焊盘尺寸的图。图4B是比较例的图。 
在实施方式1所涉及的ESD保护器件101中，柱电极27A、27B的半导体基板20一侧的宽度较小，对母板的安装面一侧的宽度较大。因此，在确保与母板的连接可靠性的同时，能减小面内布线25A、25B的尺寸。若面内布线25A、25B的尺寸较小，则面内布线25A、25B和半导体基板20之间(特别是与柱电极27A、27B连接的面内布线的焊盘P27和半导体基板20之间)产生的电容较小，因此，能实现寄生电容较小、高频特性优良的ESD保护器件。 
此外，由于柱电极27A、27B的垂直于延伸方向的截面(横截面)成为矩形，因此能增大柱电极27A、27B的截面积，故能有效利用半导体基板的面积，因此即使尺寸变小，也能实现与母板的连接可靠性较高、而且高频特性优良的ESD保护器件。 
另外，柱电极27A、27B的横截面积也可以是从输入输出电极21A、21B侧向端子电极28A、28B呈阶梯状增大的形状。 
在各个柱电极27A、27B的端子电极28A、28B一侧，即在与印刷布线板等母板的连接面一侧，设置有Ni/Au或Ni/Sn等金属镀膜。柱电极27A的表面上形成的金属镀膜构成信号线用的端子电极28A，柱电极27B的表面上形成的金属镀膜构成接地端子用的端子电极28B。 
各个柱电极27A、27B例如包括Cu镀膜，Ni镀膜起到作为Cu镀膜和Au镀膜之间的防扩散层或Cu镀膜和Sn镀膜之间的防扩散层的作用。 
图5是应用了实施方式1所涉及的ESD保护器件101的电路图的示例。另外，图6是将其应用于天线部分时的电路图的示例。 
ESD保护器件101构成两个肖特基势垒二极管面对面串联连接的ESD保护电路。如图5所示，该ESD保护器件101连接在信号线和GND线之间。例如，在图6的示例中，通过将ESD保护器件101的信号线用端子电极28A连接至信号线，将接地端子用端子电极28B连接至GND，来将ESD保护器件插入到天线和RF电路之间。由此，从天线输入进来的ESD的瞬变电流被分流至大地，从而能将信号线的电压限制在安全的电平。 
图7A是表示ESD保护器件101和安装对象即印刷布线板的结构的图，图7B是表示ESD保护器件101对印刷布线板的安装状态的结构的图。 
如图7A、图7B所示，ESD保护器件101通过回流焊接法等方法，经由设置在印刷布线板50的焊盘电极51A、51B上的焊料52A、52B装载并固定在这些焊盘电极51A、51B上。该ESD保护器件101是构成作为单通道产品的一个例子，对一根信号线发挥ESD保护功能。 
由此，通过将再布线层30中的柱电极形成为矩形截面的柱状，在信号频带下能增大柱电极的电感分量，能显著降低ESD保护电路的二极管所具有的寄生电容。其结果是，不会降低ESD保护性能，而能实现对高频信号的寄生电容较小、低损耗且又小又薄的ESD保护器件。 
此外，优选利用一端与输入输出电极21A、21B连接的层间布线24A、24B、一端与层间布线24A、24B的另一端连接的面内布线25A、25B、以及与面内布线25A、25B的另一端连接的柱电极27A、27B来构成再布线层30 的导体部分，因为这样提高了柱电极27A、27B的位置自由度，且其形状的自由度也随之得到了提高。 
如图7A、图7B所示，ESD保护器件101以其安装面朝下的方式安装至印刷布线板50。在上述实施方式1中，将ESD保护器件101的安装面侧设定为ESD保护器件101的上表面侧。 
实施方式2 
图8A是实施方式2所涉及的ESD保护器件102的主要部分的剖视图。图8B是从其安装面侧进行观察时的俯视图。图8A是沿图8B中的X-X线的剖视图。 
ESD保护器件102包括：具有输入输出电极21A、21D等的半导体基板20和形成在其表面上的再布线层30。虽然图8A、图8B中没有示出，但在半导体基板20的表层形成有ESD保护电路，且输入输出电极(21A、21D等)与该ESD保护电路连接。再布线层30包括层间布线(24A、24D等)、面内布线(25A、25D等)及柱电极(27A、27D等)。 
图8A所示的截面的结构与实施方式1中所示的ESD保护器件101的情况相同。然而，实施方式2中，在端子电极(28A、28D等)上利用焊料凸点形成端子电极(29A、29D等)。此外，柱电极(27A、27D等)为圆柱形。在该实施方式2中包括四个端子电极，并构成双通道的ESD保护器件。 
图9是上述ESD保护器件102的电路图。这里，端子电极29C是与电源线连接的端子，端子电极29D是与大地连接的端子，端子电极29A是与第一信号线连接的端子，端子电极29B是与第二信号线连接的端子。 
由此，第一信号线和电源线之间连接有二极管D1，第一信号线和大地之间连接有二极管D4。同样地，第二信号线和电源线之间连接有二极管D2，第二信号线和大地之间连接有二极管D3。此外，电源线和大地之间连接有二极管D5。此外，对于电源线以反向插入二极管D6。在这些二极管中，二极管D1～D5对从端子电极29A、29B进入的浪涌电流形成旁路，使浪涌流入电源线或大地。 
所述二极管D5是肖特基势垒二极管，其它的二极管D1～D4、D6是PN结二极管。另外，二极管D6是用于阻断从端子电极29A、29B流向电源线的 电流而设置的。另外，根据需要的电流容量，将多个二极管进行并联连接来构成这些二极管D1～D6。 
图10A是表示ESD保护器件102和安装对象即印刷布线板的结构的图，图10B是表示ESD保护器件102对印刷布线板的安装状态的结构的图。 
如图10A、图10B所示，该ESD保护器件102通过回流焊接法等方法装载并固定至印刷布线板50的焊盘电极(51A、51D等)。该ESD保护器件102是构成作为双通道产品的一个例子，对两根信号线发挥ESD保护功能。 
实施方式3 
图11是实施方式3所涉及的ESD保护器件103的主要部分的剖视图。在该ESD保护器件103中，柱电极27A、27B在器件的侧面露出，在该侧面的表面上形成有利用金属镀膜形成的端子电极28A、28B。即，形成有在ESD保护器件的底面(在图11所示的方向中为上方的表面)及侧面上连续的端子电极28A、28B。 
由于具备上述结构的端子电极，使得在将该ESD保护器件103安装至母板时，焊料也包覆到端子电极28A、28B的侧面，从而增大了焊料和端子电极28A、28B之间的接合面积。其结果是，可以使ESD保护器件103的结合强度提高，而且也容易确定其安装状态(焊接状态)。 
标号说明 
D1～D6  二极管 
P27  焊盘 
20  半导体基板 
21A、21B、21D  输入输出电极 
22  无机绝缘层 
23A、23B  绝缘粘接层 
24A、24B  层间布线 
25A、25B  面内布线 
26  有机绝缘膜 
27A、27B、27D  柱电极 
28A  信号线用端子电极 
28B  接地端子用端子电极 
29A、29B、29C、29D  焊料凸点端子电极 
30  再布线层 
50  印刷布线板 
51A、51B  焊盘电极 
101～103  ESD保护器件。

Claims (6)

1.一种ESD保护器件，其特征在于， 
包括：半导体基板，该半导体基板上形成有包括二极管的ESD保护电路、和与所述ESD保护电路导通的第一及第二输入输出电极；以及 
再布线层，该再布线层包括与所述第一输入输出电极和第一端子电极导通的柱状的第一柱电极、和与所述第二输入输出电极和第二端子电极导通的柱状的第二柱电极， 
所述第一及第二柱电极的中心间距离大于所述第一及第二输入输出电极的中心间距离。 
2.如权利要求1所述的ESD保护器件，其特征在于， 
所述第一柱电极和所述第二柱电极之间的最短距离大于所述第一及第二输入输出电极的中心间距离。 
3.如权利要求1所述的ESD保护器件，其特征在于， 
所述再布线层包括形成在内层的第一及第二面内布线、以及分别将该第一及第二面内布线和所述第一及第二输入输出电极连接起来的第一及第二层间布线，所述第一柱电极将所述第一面内布线和所述第一端子电极之间连接，所述第二柱电极将所述第二面内布线和所述第二端子电极之间连接。 
4.如权利要求3所述的ESD保护器件，其特征在于， 
所述第一及第二柱电极的与中心轴正交的面上的、所述端子电极一侧的截面积大于所述输入输出电极一侧的截面积。 
5.如权利要求4所述的ESD保护器件，其特征在于， 
所述第一及第二柱电极的所述截面积包括从所述输入输出电极向所述端子电极呈连续或阶梯状地增大的形状。 
6.如权利要求1至5中任一项所述的ESD保护器件，其特征在于， 
在所述半导体基板的由第一侧面和与该第一侧面相邻的第三、第四侧面所构成的两个角部的附近的再布线层上，分别包括与第一信号线连接的第一端子电极及与第二信号线连接的第二端子电极， 
在所述半导体基板的由与所述第一侧面相对的第二侧面和与该第二侧面相邻的第三、第四侧面所构成的两个角部的附近的再布线层上，分别包括与电源线连接的第三端子电极及与接地线连接的第四端子电极， 
所述ESD保护电路分别连接在第一端子电极和第三端子电极之间、第一端子电极和第四端子电极之间、第二端子电极和第三端子电极之间、及第二端子电极和第四端子电极之间。 
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JP5532137B2 (ja) 2014-06-25
JPWO2012023394A1 (ja) 2013-10-28
JP2014033207A (ja) 2014-02-20
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US9202791B2 (en) 2015-12-01
US20150061146A1 (en) 2015-03-05

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