TWI419268B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI419268B
TWI419268B TW097119799A TW97119799A TWI419268B TW I419268 B TWI419268 B TW I419268B TW 097119799 A TW097119799 A TW 097119799A TW 97119799 A TW97119799 A TW 97119799A TW I419268 B TWI419268 B TW I419268B
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Taiwan
Prior art keywords
film
semiconductor device
low dielectric
forming
wiring
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TW097119799A
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English (en)
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TW200915500A (en
Inventor
Aiko Mizusawa
Osamu Okada
Takeshi Wakabayashi
Ichiro Mihara
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Teramikros Inc
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Publication of TW200915500A publication Critical patent/TW200915500A/zh
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Publication of TWI419268B publication Critical patent/TWI419268B/zh

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Description

半導體裝置及其製造方法
本發明係關於半導體裝置及其製造方法，尤其是關於在低介電率膜上具有配線之半導體裝置。
作為搭載於以行動電子機器等為代表之小型電子機器上的半導體裝置，已知一種具有與半導體基板大致相同大小(尺寸&容積)之CSP(Chip Size Package)。在此CSP之中，亦是在晶圓狀態下完成封裝，並藉由切割而分離成各單個的半導體裝置，其亦被稱為WLP(Wafer Level Package)。
在先前之此種半導體裝置(例如，參照專利文獻1)中，於被覆形成於半導體基板上之連接墊的絕緣膜的上面延伸出配線，於形成於延伸出之配線一端的連接墊部上面設置多個柱狀電極，並於絕緣膜上面之柱狀電極之間形成封裝膜以被覆配線。封裝膜係將其上面設置成與柱狀電極之上面成為同一面，並於柱狀電極之上面設置焊球。
[專利文獻1]日本特開2004－349461號公報
然而，如上述之半導體裝置，係具有在半導體基板與絕緣膜之間設置由層間絕緣膜及配線之積層構造所構成的層間絕緣膜配線積層構造部者。在此情況時，當隨著微細化而使得層間絕緣膜配線積層構造部之配線間的間隔變小時，該配線間之容量增大，使得傳遞於該配線之信號的延遲亦會增大。
為了改善此狀況，作為層間絕緣膜之材料，一種介電 率比一般作為層間絕緣膜之材料使用的氧化矽的介電率4.2~4.0更低之稱為Low－k材料等的低介電率材料正受到矚目。Low－k材料係可舉出在氧化矽(SiO2)添碳(C)的SiOC或進一步含H的SiOCH等。另外，為了進一步減低介電率，亦對含空氣之多孔(多孔性)型的低介電率膜進行了檢討。
然而，在具備該低介電率膜之半導體裝置中，尤其是如具有中空構造之多孔型的低介電率膜所代表，具有機械強度低、且容易受到水份之影響，進而容易自襯底層剝離之問題。
在此，本發明之目的在於，提供一種可大幅改善低介電率膜之剝離的半導體裝置及其製造方法。
本發明之半導體裝置，其半導體基板(1)係於一面上具有低介電率膜配線積層構造部(3)。低介電率膜配線積層構造部(3)，係具有比介電率為3.0以下且玻璃轉移溫度為400℃以上之低介電率膜(4)及配線(5)之積層構造。於該低介電率膜配線積層構造部(3)上形成有絕緣膜(9)，於該絕緣膜(9)上形成有與該低介電率膜配線積層構造部(3)之最上層的配線(5)的連接墊部(5a)連接而設之電極用連接墊部、設於該電極用連接墊部上之外部連接用凸塊電極(13)、及至少設於該外部連接用凸塊電極(13)周圍之該絕緣膜(9)上並由 有機樹脂所構成的封裝膜(14)。該低介電率膜配線積層構造部(3)之側面，係由該絕緣膜(9)及該封裝膜(14)之任一方所被覆。
本發明之半導體裝置之製造方法，其特徵為具有準備步驟，係在半導體晶圓(21)的一面上形成積層有比介電率為3.0以下且玻璃轉移溫度為400℃以上之低介電率膜(4)及配線(5)之低介電率膜配線積層構造部(3)。其次，藉由照射雷射光束以除去該半導體晶圓(21)的切割路(22)上及其兩側之區域中的該低介電率膜配線積層構造部(3)，形成使該低介電率膜配線積層構造部(3)之側面露出的槽(23)。再者，形成用以被覆該低介電率膜配線積層構造部(3)之側面的有機樹脂膜(9,14)。然後，沿該切割路(22)將該有機樹脂膜(9,14)及該半導體晶圓(21)切斷，獲得複數個之單個的半導體裝置。
 (用以實施發明的最佳形態) (第1實施形態)
第1圖為本發明之第1實施形態的半導體裝置之剖視圖。此半導體裝置係具備矽基板(半導體基板)1。在矽基板1之上面，雖未圖示，但設有電晶體等多個之主動型半導體元件，在上面周邊部設有僅圖示2個但實際上具有多個之由鋁系金屬等所構成的連接墊2，且設置成連接於各半導體元件上。在此，連接墊2係各半導體元件之輸入輸出 端子或電源端子。
在矽基板1之上面，於除了連接墊2外側之周邊部以外之區域設置低介電率膜配線積層構造部3。低介電率膜配線積層構造部3，係成為由複數層、例如4層之低介電率膜4及同層數的銅或鋁系金屬所構成之配線5交互地積層所形成之構造。
作為低介電率膜4之材料，係可舉出具有Si－O鍵及Si－H鍵之聚矽氧烷系材料(HSQ：Hydrogen silsesquioxane、比介電率3.0)、具有Si－O鍵及Si－CH3 鍵之聚矽氧烷系材料(MSQ：Methyl silsesquioxane、介電率2.7~2.9)、添碳氧化矽(SiOC：Carbon doped silicon oxide、介電率2.7~2.9)、有機聚合物系之low－k材料等，可使用比介電率為3.0以下且玻璃轉移溫度為400℃以上者。
作為有機聚合物系之low－k材料，係可舉出Dow Chemical公司製之「SiLK(比介電率2.6)」、及Honeywell Electronic Materials公司製之「FLARE(比介電率2.8)」等。在此，所謂玻璃轉移溫度為400℃以上，係為了能充分地承受後述之製造步驟中的溫度。又，亦可使用上述各材料之多孔型。
另外，作為低介電率膜4之材料，除上述之外，藉由作成比通常狀態下之比介電率3.0更大，但屬多孔型，可使用比介電率為3.0以下且玻璃轉移溫度為400℃以上者。例如，添氟氧化矽(FSG：Fluorinated Silicate Glass、比介 電率為3.5~3.7)、添硼氧化矽(BSG：Boron－doped Silicate Glass、比介電率為3.5)、氧化矽(比介電率為4.0~4.2)。
在低介電率膜配線積層構造部3中，各層之配線5係於層間相互連接。最下層之配線5的一端部，係透過設於最下層之低介電率膜4的開口部6而與連接墊2連接。最上層之配線5的連接墊部5a，係配置於最上層之低介電率膜4的上面周邊部。
在包含最上層之配線5的最上層之低介電率膜4上面，設有由氧化矽等之無機材料所構成之鈍化膜7。在對應於最上層之配線5的連接墊部5a的部分之鈍化膜7設有開口部8。在鈍化膜7之上面設有主要成份由聚醯亞胺、環氧、苯酚、雙馬來醯亞胺、丙烯、合成橡膠、聚苯并氧化物等之有機材料所構成的保護膜(絕緣膜)9。在對應於鈍化膜7之開口部8的部分之保護膜9上設置開口部10。
在保護膜9之上面設有由銅等所構成之襯底金屬層11。在襯底金屬層11之整個上面設有由銅所構成之上層配線12。含襯底金屬層11之上層配線12的一端部，係透過鈍化膜7及保護膜9之開口部8、10而與最上層之配線5的連接墊部5a連接。在上層配線12之連接墊部(電極用連接墊部)上面設有由銅所構成之柱狀電極(外部連接用凸塊電極)13。
在包含上層配線12之保護膜9的上面及矽基板1之周邊部上面設有由環氧樹脂系等的有機材料所構成之封裝膜 14，且將封裝膜14之上面設成與柱狀電極13上面成為同一面。在此狀態之下，低介電率膜配線積層構造部3、鈍化膜7及保護膜9之側面，係實質上形成一面，並由封裝膜14所被覆。在柱狀電極13上面設有焊球15。
如上述，在此半導體裝置中，在除了矽基板1之周邊部以外之區域，設有由低介電率膜4及配線5之積層構造所構成的低介電率膜配線積層構造部3，且藉由封裝膜14來被覆低介電率膜配線積層構造部3、鈍化膜7及保護膜9之側面，而形成不容易從矽基板1剝離低介電率膜配線積層構造部3的構造。
其次，說明此半導體裝置之製造方法的一例。首先如第2圖所示，準備在晶圓狀態之矽基板(以下，稱為半導體晶圓21)上設置連接墊2、各4層之低介電率膜4及配線5、和鈍化膜7，最上層之配線5的連接墊部5a的中央部係透過設於鈍化膜7之開口部8而露出者。
作為低介電率膜4之材料，可舉出如上述者，包含屬多孔型者在內，可使用比介電率為3.0以下且玻璃轉移溫度為400℃以上者。又，在第2圖中，元件符號22所示區域係對應於切割路之區域。
再者，如第3圖所示，藉由網版印刷法、旋轉塗佈法等，在包含透過鈍化膜7之開口部8而露出的最上層之配線5的連接墊部5a上面之鈍化膜7上面，形成由聚醯亞胺系樹脂等的有機材料所構成之保護膜9。其次，如第4圖 所示，藉由網版印刷法、旋轉塗佈法等，在保護膜9之上面形成由聚乙烯醇(PVA)、聚丙烯醯胺(PAM)等之水溶性高分子所構成的水溶性保護膜17。
接著，如第4圖所示，藉由照射雷射光束之雷射加工，在切割路22及其兩側之區域中的水溶性保護膜17、保護膜9、鈍化膜7及4層之低介電率膜4形成槽23，且在對應於最上層之配線5之連接墊部5a的部分之含水溶性保護膜17的鈍化膜7及保護膜9上形成開口部8、10。
在此情況時，當雷射光束照射於低介電率膜4上時，低介電率膜4熔化，並成為低介電率膜片而飛散。此飛散之低介電率膜片，落下並穿刺於水溶性保護膜17的上面，而不會落下並穿刺於保護膜9之上面。然後，當以水洗除去水溶性保護膜17時，穿刺於水溶性保護膜17上面之低介電率膜片亦被同時除去。又，若藉由真空抽吸來吸引飛散之低介電率膜片的話，亦可不設置水溶性保護膜17。
在此，因低介電率膜4較脆，所以在藉由刀刃切斷而形成槽23之情況，在切斷面，會在低介電率膜4上產生多處之缺口、破損，所以，槽23之形成，推薦使用以雷射光束來切斷低介電率膜4的方法。在藉由雷射光束來加工槽23的情況，當雷射光束照射於矽基板1之上面時，矽基板1之上面熔化，並成為矽片跳起後落下於矽基板1上，所以，槽23之底面成為如第5圖所示之凹凸。
在此狀態、亦即在除去水溶性保護膜17之狀態下，如 第6圖所示，切割路22及其兩側之區域的半導體晶圓21的上面係透過槽23露出。另外，積層於半導體晶圓21上之4層的低介電率膜4、鈍化膜7及保護膜9係由槽23所分離，藉以形成第1圖所示之低介電率膜配線積層構造部3。
在此，作為一例，槽23之寬度係成為10~1000 μm×2＋切割路22(切割刀)的寬度。即，參照第1圖進行說明，被覆低介電率膜配線積層構造部3、鈍化膜7及保護膜9之側面的封裝膜14的寬度，係10~1000 μm。
接著，如第7圖所示，在包含透過鈍化膜7及保護膜9之開口部8、10露出的最上層之配線5的連接墊部5a上面及透過槽23露出之半導體晶圓21的上面之保護膜9的整個上面，形成襯底金屬層11。在此情況時，襯底金屬層11可僅為由無電解電鍍所形成之銅層，亦可僅為由濺鍍所形成之銅層，又，亦可為在由濺鍍所形成之鈦等的薄膜層上藉由濺鍍形成銅層者。
接著，在襯底金屬層11之上面將鍍覆阻劑膜24形成圖案。在此情況時，在對應於上層配線12形成區域之部分的鍍覆阻劑膜24上形成開口部25。然後，藉由進行將襯底金屬層11作為電鍍電流路之銅的電解電鍍，在鍍覆阻劑膜24之開口部25內的襯底金屬層11上面形成上層配線12。接著將鍍覆阻劑膜24剝離。
接著，如第8圖所示，在包含上層配線12之襯底金屬 層11的上面將鍍覆阻劑膜26形成圖案。在此情況時，在對應於上層配線12之連接墊部(柱狀電極13形成區域)之部分的鍍覆阻劑膜26形成開口部27。
然後，藉由進行將襯底金屬層11作為電鍍電流路之銅的電解電鍍，在鍍覆阻劑膜26之開口部27內的上層配線12之連接墊部上面，形成高度為50~150 μm的柱狀電極13。然後將鍍覆阻劑膜26剝離，接著將上層配線12作為遮罩而利用蝕刻處理除去襯底金屬層11之不要部分，如第9圖所示，僅在上層配線12之下殘留襯底金屬層11。
接著，如第10圖所示，藉由網版印刷法、旋轉塗佈法等，在包含上層配線12、柱狀電極13之保護膜9上面及透過槽23露出之半導體晶圓21的上面，形成由環氧系樹脂等的有機材料所構成之封裝膜(有機樹脂膜)14，且將其厚度形成為比柱狀電極13之高度更厚。藉此，在此狀態之下，柱狀電極13之上面係由封裝膜14所被覆。另外，保護膜9、鈍化膜7及4層之低介電率膜4之側面係由封裝膜14所被覆。
然後，適宜地研削封裝膜14之上面側，如第11圖所示，使柱狀電極13之上面露出，且將包含此露出之柱狀電極13上面的封裝膜14上面加以平坦化。亦可在此封裝膜14上面之平坦化時，將封裝膜14及柱狀電極13的上面部一起研削數μm~十數μm。
接著，如第12圖所示，在柱狀電極13的上面形成焊 球15。接著，如第13圖所示，沿著槽23內之中央部的切割路22，將封裝膜14及半導體晶圓21切斷。於是，如上述，因為槽23係形成為比切割路22更寬，所以，如第1圖所示，低介電率膜配線積層構造部3之側面係由封裝膜14所被覆、配合，因此，可獲得多個鈍化膜7之側面及保護膜9的上面及側面被封裝膜14所被覆之構造的半導體裝置。
又，在上述實施形態中，半導體晶圓21之上面被圖示為如槽23之底部，但亦可以雷射光束除去半導體晶圓21之上面以形成槽23，以使槽23之底部比半導體晶圓21之上面更為陷入。另外，在半導體晶圓21之上面形成有場氧化膜等之絕緣膜的情況，亦可以此場氧化膜之上面或其膜厚之中間部成為槽23之底部的方式，使槽23之底部比半導體晶圓21之上面位於更上方。
(第2實施形態)
第14圖為本發明之第2實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第1圖所示半導體裝置的差異點在於：鈍化膜7之上面及側面、及低介電率膜配線積層構造部3之側面係由保護膜9所被覆，並由封裝膜14來被覆保護膜9之側面。
在製造此半導體裝置時，作為一例，係在準備第2圖所示者之後，如第15圖所示，藉由網版印刷法、旋轉塗佈法等，在包含透過鈍化膜7之開口部8露出的最上層之配 線5的連接墊部5a之鈍化膜7上面，形成由聚乙烯醇(PVA)、聚丙烯醯胺(PAM)等之水溶性高分子所構成的水溶性保護膜17。
接著，如第16圖所示，藉由照射雷射光束之雷射加工，在切割路22及其兩側之區域的水溶性保護膜17、鈍化膜7及4層之低介電率膜4形成槽23。此情況下亦是，當雷射光束照射於低介電率膜4上時，低介電率膜4熔化，並成為低介電率膜片而飛散。此飛散之低介電率膜片，落下並穿刺於水溶性保護膜17的上面，而不會落下並穿刺於鈍化膜7之上面。然後，當以水洗除去水溶性保護膜時，穿刺於水溶性保護膜上面之低介電率膜片亦被同時除去。又，此情況亦是，若藉由真空抽吸來吸引飛散之低介電率膜片的話，亦可不設置水溶性保護膜17。
在此狀態、亦即在除去水溶性保護膜17之狀態下，如第17圖所示，切割路22及其兩側之區域的半導體晶圓21的上面，係透過槽23露出。另外，積層於半導體晶圓21上之4層的低介電率膜4及鈍化膜7，係由槽23所分離，藉以形成第14圖所示之低介電率膜配線積層構造部3。
接著，如第18圖所示，藉由網版印刷法、旋轉塗佈法等，在包含透過鈍化膜7之開口部8露出的最上層配線5的連接墊部5a上面之鈍化膜7上面及透過槽23而露出之半導體晶圓21的上面，形成由聚醯亞胺系樹脂等的有機材料所構成之保護膜(有機樹脂膜)9。在此情況時，形成於鈍 化膜7上面及槽23內之保護膜9，係以形成為其表面大致成為平坦狀為較佳。
接著，如第19圖所示，藉由照射雷射光束之雷射加工、或光微影技術，在切割路22及其兩側之區域中的保護膜9上形成比槽23之寬度略窄之槽23a，且在對應於最上層之配線5的連接墊部5a之部分的鈍化膜7及保護膜9形成開口部8、10。以下，與該第1實施形態之第7圖以下的步驟相同，故而省略說明。
(第3實施形態)
第20圖為本發明之第3實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第14圖所示半導體裝置的差異點在於：被覆鈍化膜7之上面及側面、及低介電率膜配線積層構造部3之側面的保護膜(有機樹脂膜)9，係延伸至與矽基板1的端面為相同之面。
在製造此半導體裝置時，如第18圖所示，將保護膜9完全充填於槽23內，亦可不形成如第19圖所示之槽23a。藉此，在此情況時，在最終步驟中，沿切割路22將封裝膜14、保護膜9及半導體晶圓21切斷。
(第4實施形態)
第21圖為本發明之第4實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第1圖所示半導體裝置的差異點在於：將保護膜9之側面配置於比低介電率膜配線積層構造部3及鈍化膜7之側面更位於內側。亦即保護膜9係 在鈍化膜7上形成為比該鈍化膜7之尺寸更小。在此情況時，鈍化膜7及低介電率膜配線積層構造部3之側面，係實質上形成一面。
其次，說明此半導體裝置之製造方法的一例。在此情況時，例如，如第3圖所示，將保護膜(有機樹脂膜)9成膜於鈍化膜7上的全面，接著，使用光微影技術對此保護膜9進行圖案加工，形成如第21圖所示之保護膜9。保護膜9之圖案加工，係以保護膜9之側面9a成為未到達切割路22之位置的方式所進行。在此情況時，保護膜9之側面9a與鈍化膜7及低介電率膜配線積層構造部3的側面，係作成比下一步驟之雷射照射時的對位偏移更大的尺寸。然後，根據需要，在整個上面形成水溶性保護膜，接著，可照射雷射光束來加工鈍化膜7及低介電率膜4，以形成槽23。
其次，說明此半導體裝置之製造方法的另一例。另一例係如第17圖所示，在保護膜9成膜之前，藉由照射雷射光束來加工鈍化膜7及低介電率膜4，以形成槽23。接著，如第18圖所示，照射雷射光束來形成槽23之後，圖案加工保護膜9。接著，藉由旋轉塗佈等，在含槽23內之鈍化膜7上整面進行保護膜9的成膜，然後使用光微影技術，以除去槽23內及鈍化膜7之周緣部的方式將此保護膜9進行圖案加工，形成如第21圖所示之保護膜9。
無論哪一方法，在此半導體裝置之製造方法中，藉由雷射光束來加工鈍化膜7及低介電率膜4，而不加工保護 膜9，所以，保護膜9之材料，如聚醯亞胺系樹脂等，對容易吸收雷射能量而不容易利用雷射光束之照射進行切斷的情況，特別有效。
(第5實施形態)
第22圖為本發明之第5實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第21圖所示半導體裝置的差異點在於：將鈍化膜7之側面配置於比保護膜9之側面更位於內側。亦即鈍化膜7係在低介電率膜配線積層構造部3上形成為比保護膜9之尺寸更小。
在製造此半導體裝置時，如第2圖所示，將鈍化膜7成膜於最上層之低介電率膜4上的全面，接著，使用光微影技術對此鈍化膜7進行圖案加工。然後將保護膜9成膜於鈍化膜7上及自鈍化膜7露出之最上層的低介電率膜4上，接著，使用光微影技術對此保護膜9進行圖案加工。然後，可根據需要在整個上面形成水溶性保護膜，接著，可照射雷射光束來加工低介電率膜4，以形成槽23。
在此半導體裝置之製造方法中，藉由雷射光束僅加工低介電率膜4，而不加工鈍化膜7及保護膜9，所以，可設定為對低介電率膜4之加工而言為最適宜之雷射光束的條件，所以，具有可有效且高精度地進行低介電率膜4之加工的功效。又，亦可將鈍化膜7之尺寸作成與保護膜9相同大小之尺寸，以使鈍化膜7及保護膜9之側面基本上形成為一面。
(第6實施形態)
第23圖為本發明之第6實施形態的半導體裝置之剖視圖。在此半導體裝置中，與第21圖所示半導體裝置的差異點在於：將低介電率膜配線積層構造部3，作成在其最上層之配線5與其最上層之低介電率膜4之間具有下層鈍化膜16的構造。
在此情況時，鈍化膜7及下層鈍化膜16，係可由氧化矽等之相同無機材料所形成。另外，鈍化膜7亦可由氮化矽所形成，下層鈍化膜16亦可由氧化矽所形成。
(其他實施形態)
例如，在上述第1實施形態中，在第3圖所示步驟後，在保護膜9之整個上面形成襯底金屬層11，接著，藉由電解電鍍形成上層配線12及柱狀電極13，接著將上層配線12作為遮罩，利用蝕刻處理除去襯底金屬層11之不要部分，僅在上層配線12下殘留襯底金屬層。然後，亦可根據需要，在整個上面形成水溶性保護膜，接著，照射雷射光束來加工保護膜9、鈍化膜7及低介電率膜4，以形成槽23。在此情況時，在形成槽2之後，當除去水溶性保護膜時，成為第9圖所示狀態。
另外，例如，參照第21圖進行說明，低介電率膜配線積層構造部3亦可作成將其最上層之低介電率膜4作為下層鈍化膜的構造。亦即，低介電率膜配線積層構造部3亦可作成在其最上層之配線5與其下之配線5之間具有下層 鈍化膜的構造。
在此情況時，鈍化膜7及下層鈍化膜，亦可由氧化矽等之相同的無機材料所形成。另外，鈍化膜7係可由氮化矽所形成，下層鈍化膜係可由氧化矽所形成。
另外，在上述各實施形態中，雖具有在保護膜9上形成上層配線12，並在此上層配線12之連接墊部上形成柱狀電極13的構造，但本發明亦可適用於在保護膜9上僅形成連接墊部，並於此連接墊部上形成焊球15等之外部連接用凸塊電極的構造。
(發明效果)
如上述詳細說明，根據本發明，於除了半導體基板上之周邊部以外之區域，設置由比介電率為3.0以下且玻璃轉移溫度為400℃以上之低介電率膜及配線之積層構造所構成的低介電率膜配線積層構造部，並由有機樹脂膜所構成之絕緣膜及封裝膜之至少任一方來被覆此低介電率膜配線積層構造部之側面，所以可大幅改善低介電率膜之剝離。
1‧‧‧基板
2‧‧‧連接墊
3‧‧‧低介電率膜配線積層構造部
4‧‧‧低介電率膜
5‧‧‧配線
7‧‧‧鈍化膜
9‧‧‧保護膜
11‧‧‧襯底金屬層
12‧‧‧上層配線
13‧‧‧柱狀電極
14‧‧‧封裝膜
15‧‧‧焊球
16‧‧‧下層鈍化膜
17‧‧‧水溶性保護膜
21‧‧‧半導體晶圓
22‧‧‧切割路
23‧‧‧槽
23a‧‧‧槽
第1圖為本發明之第1實施形態的半導體裝置之剖視圖。
第2圖為第1圖所示之半導體裝置的製造時最初所準備之構件的剖視圖。
第3圖為接續第2圖之步驟的剖視圖。
第4圖為接續第3圖之步驟的剖視圖。
第5圖為接續第4圖之步驟的剖視圖。
第6圖為接續第5圖之步驟的剖視圖。
第7圖為接續第6圖之步驟的剖視圖。
第8圖為接續第7圖之步驟的剖視圖。
第9圖為接續第8圖之步驟的剖視圖。
第10圖為接續第9圖之步驟的剖視圖。
第11圖為接續第10圖之步驟的剖視圖。
第12圖為接續第11圖之步驟的剖視圖。
第13圖為接續第12圖之步驟的剖視圖。
第14圖為本發明之第2實施形態的半導體裝置之剖視圖。
第15圖為第14圖所示之半導體裝置的製造時指定步驟的剖視圖。
第16圖為接續第15圖之步驟的剖視圖。
第17圖為接續第16圖之步驟的剖視圖。
第18圖為接續第17圖之步驟的剖視圖。
第19圖為接續第18圖之步驟的剖視圖。
第20圖為本發明之第3實施形態的半導體裝置之剖視圖。
第21圖為本發明之第4實施形態的半導體裝置之剖視圖。
第22圖為本發明之第5實施形態的半導體裝置之剖視圖。
第23圖為本發明之第6實施形態的半導體裝置之剖視圖。
1‧‧‧基板
2‧‧‧連接墊
3‧‧‧低介電率膜配線積層構造部
4‧‧‧低介電率膜
5‧‧‧配線
5a‧‧‧連連接墊部
6‧‧‧開口部
7‧‧‧鈍化膜
8‧‧‧開口部
9‧‧‧保護膜
10‧‧‧開口部
11‧‧‧襯底金屬層
12‧‧‧上層配線
13‧‧‧柱狀電極
14‧‧‧封裝膜
15‧‧‧焊球

Claims (22)

  1. 一種半導體裝置，其特徵為具備：半導體基板(1)；低介電率膜配線積層構造部(3)，係設於除了該半導體基板(1)之一面上的周邊部以外之區域，並由比介電率為3.0以下且玻璃轉移溫度為400℃以上之低介電率膜(4)及配線(5)之積層構造所構成；絕緣膜(9)，係設於該低介電率膜配線積層構造部(3)上；電極用連接墊部，係設於該絕緣膜(9)上，並與該低介電率膜配線積層構造部(3)之最上層配線(5)之連接墊部(5a)連接；外部連接用凸塊電極(13)，係設於該電極用連接墊部上；封裝膜(14)，係由有機樹脂所構成，至少設於該外部連接用凸塊電極(13)周圍之該絕緣膜(9)上；及鈍化膜(7)，係在該絕緣膜(9)與該低介電率膜配線積層構造部(3)之間由無機材料所構成，該鈍化膜(7)及該低介電率膜配線積層構造部(3)之側面，係實質上形成一面，該鈍化膜(7)及該低介電率膜配線積層構造部(3)之側面係由該絕緣膜(9)所被覆。
  2. 如申請專利範圍第1項之半導體裝置，其中該絕緣膜(9)之側面係由該封裝膜(14)所被覆。
  3. 如申請專利範圍第1項之半導體裝置，其中該絕緣膜(9)，係延伸至與該半導體基板(1)的端面相同之面。
  4. 如申請專利範圍第1項之半導體裝置，其中該低介電率膜配線積層構造部(3)係在其最上層之配線(5)及其最上層之低介電率膜(4)之間具有下層鈍化膜(16)。
  5. 如申請專利範圍第1項之半導體裝置，其中該低介電率膜配線積層構造部(3)係在其最上層之配線(5)及其下方之配線(5)之間具有下層鈍化膜。
  6. 如申請專利範圍第4或5項之半導體裝置，其中該下層鈍化膜係由氧化矽所構成。
  7. 如申請專利範圍第6項之半導體裝置，其中該絕緣膜係包含由氮化矽所構成之鈍化膜。
  8. 如申請專利範圍第1項之半導體裝置，其中在該絕緣膜(9)上形成具有該電極用連接墊部之上層配線(12)。
  9. 如申請專利範圍第8項之半導體裝置，其中形成於該上層配線(12)之連接墊部上之外部連接用凸塊電極(13)係柱狀電極。
  10. 如申請專利範圍第9項之半導體裝置，其中在該柱狀電極(13)上設有焊球(15)。
  11. 如申請專利範圍第1至10項中任一項之半導體裝置，其中該低介電率膜(4)係包含：具有Si-O鍵及Si-H鍵之聚 矽氧烷系材料、具有Si-O鍵及Si-CH3 鍵之聚矽氧烷系材料、添碳氧化矽、有機聚合物系之low-k材料之任一者，或是包含添氟氧化矽、添硼氧化矽、氧化矽之任一者之多孔型者。
  12. 如申請專利範圍第1項之半導體裝置，其中該絕緣膜(9)接觸的該半導體基板的表面具有凹凸。
  13. 一種半導體裝置之製造方法，其特徵為具備：準備步驟，係準備在半導體晶圓(21)之一面上形成有低介電率膜配線積層構造部(3)者，該低介電率膜配線積層構造部(3)係由比介電率為3.0以下且玻璃轉移溫度為400℃以上之低介電率膜(4)及配線(5)所積層者；形成鈍化膜(7)之步驟，係在該低介電率膜配線積層構造部(3)上，形成由無機材料所構成的鈍化膜(7)；形成有機樹脂膜(9)之步驟，係在該鈍化膜(7)上形成有機樹脂膜(9)；形成槽(23)之步驟，係藉由照射雷射光束以除去切割路(22)上及其兩側之區域中的該低介電率膜配線積層構造部(3)，使該低介電率膜配線積層構造部(3)之側面及該鈍化膜(7)之側面，以實質上形成一面的方式露出；形成封裝膜(14)之步驟，係在該有機樹脂膜(9)上形成由有機樹脂所構成的封裝膜(14)；及獲得複數個之單個的半導體裝置的步驟，其係沿該切割路(22)將該封裝膜(14)及該半導體晶圓(21)切斷。
  14. 如申請專利範圍第13項之半導體裝置之製造方法，其中形成該槽(23)之步驟，包含：在形成該槽(23)之前，於該有機樹脂膜(9)的整個上面形成水溶性保護膜(17)，並在形成該槽(23)之後，除去該水溶性保護膜(17)的步驟。
  15. 如申請專利範圍第13項之半導體裝置之製造方法，其中更具備：使電極用連接墊部連接於該低介電率膜配線積層構造部(3)之最上層的配線(5)之連接墊部上而形成於該有機樹脂膜(9)上的步驟；及在該電極用連接墊部上形成外部連接用凸塊電極(13)之步驟。
  16. 如申請專利範圍第13項之半導體裝置之製造方法，其中更具備：使電極用連接墊部連接於該低介電率膜配線積層構造部(3)之最上層的配線(5)之連接墊部上而形成於該有機樹脂膜(9)上的步驟，及在該電極用連接墊部上形成外部連接用凸塊電極(13)之步驟；形成該封裝膜(14)之步驟，係包含形成由有機樹脂所構成的封裝膜(14)之步驟，該封裝膜(14)係用以被覆該外部連接用凸塊電極(13)的周圍之該有機樹脂膜(9)的上面，該有機樹脂膜(9)之側面及該低介電率膜配線積層構造部(3)之側面。
  17. 如申請專利範圍第16項之半導體裝置之製造方法，其中形成該封裝膜(14)之步驟，係包含將該封裝膜(14)充填 於該槽(23)內之步驟。
  18. 如申請專利範圍第13項之半導體裝置之製造方法，其中形成該槽(23)之步驟，包含：除去切割路(22)上及其兩側之區域中的該鈍化膜(7)及該低介電率膜配線積層構造部(3)，以形成使該鈍化膜(7)之側面及該低介電率膜配線積層構造部(3)之側面露出的槽(23)之步驟。
  19. 如申請專利範圍第13項之半導體裝置之製造方法，其中形成該封裝膜(14)之步驟，係包含以不會將該封裝膜(14)延伸出切割路(22)上之方式，將該封裝膜(14)形成圖案的步驟。
  20. 如申請專利範圍第13項之半導體裝置之製造方法，其中形成該有機樹脂膜(9)之步驟具有：形成被充填於該槽(23)內且除去與該槽之中央部對應的部分之絕緣膜(9)的步驟；形成該封裝膜(14)之步驟包含：在該被除去之該絕緣膜(9)的部分充填有機樹脂，以形成封裝膜(14)之步驟。
  21. 如申請專利範圍第20項之半導體裝置之製造方法，其中形成該封裝膜(14)之步驟，係包含以該封裝膜(14)被覆該絕緣膜(9)之側面的步驟。
  22. 如申請專利範圍第13至21項中任一項之半導體裝置之製造方法，其中該低介電率膜係包含：具有Si-O鍵及Si-H鍵之聚矽氧烷系材料、具有Si-O鍵及Si-CH3 鍵之聚矽 氧烷系材料、添碳氧化矽、有機聚合物系之low-k材料之任一者，或是包含添氟氧化矽、添硼氧化矽、氧化矽之任一者之多孔型者。
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