JP5393722B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5393722B2 JP5393722B2 JP2011085808A JP2011085808A JP5393722B2 JP 5393722 B2 JP5393722 B2 JP 5393722B2 JP 2011085808 A JP2011085808 A JP 2011085808A JP 2011085808 A JP2011085808 A JP 2011085808A JP 5393722 B2 JP5393722 B2 JP 5393722B2
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- dielectric constant
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Description
請求項2に記載の発明に係る半導体装置は、請求項1に記載の発明において、前記絶縁膜は無機材料からなるパッシベーション膜と有機材料からなる保護膜とを含むことを特徴とするものである。
請求項3に記載の発明に係る半導体装置は、請求項2に記載の発明において、前記保護膜と前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は実質的に一面を形成し、前記保護膜と前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は前記封止膜によって覆われていることを特徴とするものである。
請求項4に記載の発明に係る半導体装置は、請求項2に記載の発明において、前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は実質的に一面を形成し、前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は前記保護膜によって覆われていることを特徴とするものである。
請求項5に記載の発明に係る半導体装置は、請求項4に記載の発明において、前記保護膜の側面は前記封止膜によって覆われていることを特徴とするものである。
請求項6に記載の発明に係る半導体装置は、請求項4に記載の発明において、前記保護膜は前記半導体基板の端面と同一面まで延出されていることを特徴とするものである。
請求項7に記載の発明に係る半導体装置は、請求項2に記載の発明において、前記保護膜の側面は前記低誘電率膜配線積層構造部の側面よりも内側に配置されていることを特徴とするものである。
請求項8に記載の発明に係る半導体装置は、請求項7に記載の発明において、前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は実質的に一面を形成していることを特徴とするものである。
請求項9に記載の発明に係る半導体装置は、請求項6に記載の発明において、前記パッシベーション膜の側面は前記保護膜の側面よりも内側に配置されていることを特徴とするものである。
請求項10に記載の発明に係る半導体装置は、請求項7に記載の発明において、前記保護膜と前記パッシベーション膜の側面は実質的に一面を形成していることを特徴とするものである。
請求項11に記載の発明に係る半導体装置は、請求項1に記載の発明において、前記低誘電率膜配線積層構造部は、その最上層の配線とその最上層の低誘電率膜との間に下層パッシベーション膜を有することを特徴とするものである。
請求項12に記載の発明に係る半導体装置は、請求項1に記載の発明において、前記低誘電率膜配線積層構造部は、その最上層の配線とその下の配線との間に下層パッシベーション膜を有することを特徴とするものである。
請求項13に記載の発明に係る半導体装置は、請求項11または12に記載の発明において、前記下層パッシベーション膜は酸化シリコンからなることを特徴とするものである。
請求項14に記載の発明に係る半導体装置は、請求項13に記載の発明において、前記絶縁膜は窒化シリコンからなるパッシベーション膜を含むことを特徴とするものである。
請求項15に記載の発明に係る半導体装置は、請求項1に記載の発明において、前記絶縁膜上に前記電極用接続パッド部を有する上層配線が形成されていることを特徴とするものである。
請求項16に記載の発明に係る半導体装置は、請求項15に記載の発明において、前記上層配線の接続パッド部上に形成された外部接続用バンプ電極は柱状電極であることを特徴とするものである。
請求項17に記載の発明に係る半導体装置は、請求項16に記載の発明において、前記柱状電極上に半田ボールが設けられていることを特徴とするものである。
図1はこの発明の第1実施形態としての半導体装置の断面図を示す。この半導体装置はシリコン基板(半導体基板)1を備えている。シリコン基板1の上面には所定の機能の集積回路、特に、トランジスタ、ダイオード、抵抗、コンデンサ等の素子(図示せず)が形成され、上面周辺部には、上記集積回路の各素子に接続されたアルミニウム系金属等からなる接続パッド2が設けられている。接続パッド2は2個のみを図示するが、実際にはシリコン基板1の上面に多数配列されている。
図14はこの発明の第2実施形態としての半導体装置の断面図を示す。この半導体装置において、図1に示す半導体装置と異なる点は、パッシベーション膜7の上面および側面、および低誘電率膜配線積層構造部3の側面を保護膜9で覆い、保護膜9の側面を封止膜14で覆った点である。
図20はこの発明の第3実施形態としての半導体装置の断面図を示す。この半導体装置において、図14に示す半導体装置と異なる点は、パッシベーション膜7の上面および側面、および低誘電率膜配線積層構造部3の側面を覆う保護膜(有機樹脂膜)9が、シリコン基板1の端面と同一面まで延出されている点である。
図21はこの発明の第4実施形態としての半導体装置の断面図を示す。この半導体装置において、図1に示す半導体装置と異なる点は、保護膜9の側面を低誘電率膜配線積層構造部3およびパッシベーション膜7の側面よりも内側に配置した点である。すなわち、保護膜9は、パッシベーション膜7上に該パッシベーション膜7よりも小さいサイズに形成されている。この場合、パッシベーション膜7と低誘電率膜配線積層構造部3の側面は実質的に一面を形成している。
図22はこの発明の第5実施形態としての半導体装置の断面図を示す。この半導体装置において、図21に示す半導体装置と異なる点は、パッシベーション膜7の側面を保護膜9の側面よりも内側に配置した点である。すなわち、パッシベーション膜7は、低誘電率膜配線積層構造部3上に保護膜9よりも小さいサイズに形成されている。
図23はこの発明の第6実施形態としての半導体装置の断面図を示す。この半導体装置において、図21に示す半導体装置と異なる点は、低誘電率膜配線積層構造部3を、その最上層の配線5とその最上層の低誘電率膜4との間に下層パッシベーション膜16を有する構造とした点である。
例えば、上記第1実施形態において、図3に示す工程後に、保護膜9の上面全体に下地金属層11を形成し、次いで、電解メッキにより上層配線12および柱状電極13を形成し、次いで、上層配線12をマスクとして下地金属層11の不要な部分をエッチングして除去し、上層配線12下にのみ下地金属層を残存させる。この後、必要に応じて、全上面に水溶性保護膜を形成し、次いで、レーザビームを照射して、保護膜9、パッシベーション膜7および低誘電率膜4を加工し、溝23を形成するようにしてもよい。この場合、溝23を形成した後に、水溶性保護膜を除去すると、図9に示す状態となる。
2 接続パッド
3 低誘電率膜配線積層構造部
4 低誘電率膜
5 配線
7 パッシベーション膜
9 保護膜
11 下地金属層
12 上層配線
13 柱状電極
14 封止膜
15 半田ボール
16 下層パッシベーション膜
17 水溶性保護膜
21 半導体ウエハ
22 ダイシングストリート
23 溝
23a 溝
Claims (17)
- 半導体基板と、前記半導体基板の一面上の周辺部を除く領域に設けられ、比誘電率が3.0以下でガラス転移温度が400℃以上である低誘電率膜と配線との積層構造からなる低誘電率膜配線積層構造部と、前記低誘電率膜配線積層構造部上に設けられた有機樹脂からなる絶縁膜と、前記絶縁膜上に前記低誘電率膜配線積層構造部の最上層の配線の接続パッド部に接続されて設けられた電極用接続パッド部と、前記電極用接続パッド部上に設けられた外部接続用バンプ電極と、少なくとも前記外部接続用バンプ電極の周囲における前記絶縁膜上に設けられた有機樹脂からなる封止膜とを備え、前記低誘電率膜配線積層構造部の側面が前記絶縁膜および前記封止膜のいずれか一方の膜によって覆われていて、前記一方の膜は前記半導体基板に接触するように形成され、前記一方の膜が接触している前記半導体基板の表面は凹凸を有し、前記低誘電率膜は、Si−O結合とSi−H結合を有するポリシロキサン系材料、Si−O結合とSi−CH 3 結合を有するポリシロキサン系材料、炭素添加酸化シリコン、有機ポリマー系のlow−k材料のいずれかを含み、あるいは、フッ素添加酸化シリコン、ボロン添加酸化シリコン、酸化シリコンのいずれかであってポーラス型のものを含むことを特徴とする半導体装置。
- 請求項1に記載の発明において、前記絶縁膜は無機材料からなるパッシベーション膜と有機材料からなる保護膜とを含むことを特徴とする半導体装置。
- 請求項2に記載の発明において、前記保護膜と前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は実質的に一面を形成し、前記保護膜と前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は前記封止膜によって覆われていることを特徴とする半導体装置。
- 請求項2に記載の発明において、前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は実質的に一面を形成し、前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は前記保護膜によって覆われていることを特徴とする半導体装置。
- 請求項4に記載の発明において、前記保護膜の側面は前記封止膜によって覆われていることを特徴とする半導体装置。
- 請求項4に記載の発明において、前記保護膜は前記半導体基板の端面と同一面まで延出されていることを特徴とする半導体装置。
- 請求項2に記載の発明において、前記保護膜の側面は前記低誘電率膜配線積層構造部の側面よりも内側に配置されていることを特徴とする半導体装置。
- 請求項7に記載の発明において、前記パッシベーション膜と前記低誘電率膜配線積層構造部の側面は実質的に一面を形成していることを特徴とする半導体装置。
- 請求項6に記載の発明において、前記パッシベーション膜の側面は前記保護膜の側面よりも内側に配置されていることを特徴とする半導体装置。
- 請求項7に記載の発明において、前記保護膜と前記パッシベーション膜の側面は実質的に一面を形成していることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記低誘電率膜配線積層構造部は、その最上層の配線とその最上層の低誘電率膜との間に下層パッシベーション膜を有することを特徴とする半導体装置。
- 請求項1に記載の発明において、前記低誘電率膜配線積層構造部は、その最上層の配線とその下の配線との間に下層パッシベーション膜を有することを特徴とする半導体装置。
- 請求項11または12に記載の発明において、前記下層パッシベーション膜は酸化シリコンからなることを特徴とする半導体装置。
- 請求項13に記載の発明において、前記絶縁膜は窒化シリコンからなるパッシベーション膜を含むことを特徴とする半導体装置。
- 請求項1に記載の発明において、前記絶縁膜上に前記電極用接続パッド部を有する上層配線が形成されていることを特徴とする半導体装置。
- 請求項15に記載の発明において、前記上層配線の接続パッド部上に形成された外部接続用バンプ電極は柱状電極であることを特徴とする半導体装置。
- 請求項16に記載の発明において、前記柱状電極上に半田ボールが設けられていることを特徴とする半導体装置。
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JP5839923B2 (ja) * | 2011-10-06 | 2016-01-06 | 株式会社ディスコ | パシベーション膜が積層された基板のアブレーション加工方法 |
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