CN108122820B - 互连结构及其制造方法 - Google Patents
互连结构及其制造方法 Download PDFInfo
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- CN108122820B CN108122820B CN201611066883.1A CN201611066883A CN108122820B CN 108122820 B CN108122820 B CN 108122820B CN 201611066883 A CN201611066883 A CN 201611066883A CN 108122820 B CN108122820 B CN 108122820B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 89
- 229910052751 metal Inorganic materials 0.000 claims abstract description 89
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims description 42
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L2221/1068—Formation and after-treatment of conductors
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Abstract
Description
Claims (18)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201611066883.1A CN108122820B (zh) | 2016-11-29 | 2016-11-29 | 互连结构及其制造方法 |
US15/716,261 US10553536B2 (en) | 2016-11-29 | 2017-09-26 | Method of manufacturing an interconnect structure by forming metal layers in mask openings |
EP17203759.0A EP3327762B1 (en) | 2016-11-29 | 2017-11-27 | Interconnect structure and manufacturing method thereof |
US16/734,610 US11373949B2 (en) | 2016-11-29 | 2020-01-06 | Interconnect structure having metal layers enclosing a dielectric |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201611066883.1A CN108122820B (zh) | 2016-11-29 | 2016-11-29 | 互连结构及其制造方法 |
Publications (2)
Publication Number | Publication Date |
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CN108122820A CN108122820A (zh) | 2018-06-05 |
CN108122820B true CN108122820B (zh) | 2020-06-02 |
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CN201611066883.1A Active CN108122820B (zh) | 2016-11-29 | 2016-11-29 | 互连结构及其制造方法 |
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Country | Link |
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US (2) | US10553536B2 (zh) |
EP (1) | EP3327762B1 (zh) |
CN (1) | CN108122820B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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EP3671821A1 (en) * | 2018-12-19 | 2020-06-24 | IMEC vzw | Interconnection system of an integrated circuit |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0226385A1 (en) * | 1985-12-02 | 1987-06-24 | Tektronix, Inc. | Rhodium capped gold IC metallization |
CN1242107A (zh) * | 1996-12-16 | 2000-01-19 | 国际商业机器公司 | 集成电路芯片上的电镀互连结构 |
CN1412821A (zh) * | 2001-10-15 | 2003-04-23 | 新光电气工业株式会社 | 在硅基片上形成通孔或凹陷的方法 |
CN1885524A (zh) * | 2005-06-24 | 2006-12-27 | 米辑电子股份有限公司 | 线路组件结构制造方法及其结构 |
CN105789114A (zh) * | 2012-09-24 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制造方法 |
CN107026115A (zh) * | 2015-12-15 | 2017-08-08 | 台湾积体电路制造股份有限公司 | 至部分填充的沟槽的通孔互连件 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW290731B (zh) * | 1995-03-30 | 1996-11-11 | Siemens Ag | |
JP3228181B2 (ja) * | 1997-05-12 | 2001-11-12 | ヤマハ株式会社 | 平坦配線形成法 |
US5920790A (en) * | 1997-08-29 | 1999-07-06 | Motorola, Inc. | Method of forming a semiconductor device having dual inlaid structure |
US6359328B1 (en) * | 1998-12-31 | 2002-03-19 | Intel Corporation | Methods for making interconnects and diffusion barriers in integrated circuits |
US6376370B1 (en) * | 2000-01-18 | 2002-04-23 | Micron Technology, Inc. | Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy |
US6352917B1 (en) | 2000-06-21 | 2002-03-05 | Chartered Semiconductor Manufacturing Ltd. | Reversed damascene process for multiple level metal interconnects |
US6426558B1 (en) * | 2001-05-14 | 2002-07-30 | International Business Machines Corporation | Metallurgy for semiconductor devices |
US6670271B1 (en) * | 2002-01-17 | 2003-12-30 | Advanced Micro Devices, Inc. | Growing a dual damascene structure using a copper seed layer and a damascene resist structure |
US7026244B2 (en) * | 2003-08-08 | 2006-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low resistance and reliable copper interconnects by variable doping |
US7169698B2 (en) * | 2004-01-14 | 2007-01-30 | International Business Machines Corporation | Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner |
WO2005109485A2 (en) * | 2004-05-06 | 2005-11-17 | Etech Ag | Metallic air-bridges |
US7582556B2 (en) * | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
US8569888B2 (en) * | 2011-05-24 | 2013-10-29 | International Business Machines Corporation | Wiring structure and method of forming the structure |
US9029260B2 (en) * | 2011-06-16 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap filling method for dual damascene process |
US8735283B2 (en) * | 2011-06-23 | 2014-05-27 | International Business Machines Corporation | Method for forming small dimension openings in the organic masking layer of tri-layer lithography |
US9093164B2 (en) * | 2011-11-17 | 2015-07-28 | International Business Machines Corporation | Redundant via structure for metal fuse applications |
KR102090210B1 (ko) * | 2011-12-20 | 2020-03-17 | 인텔 코포레이션 | 등각 저온 밀봉 유전체 확산 장벽들 |
US8835305B2 (en) * | 2012-07-31 | 2014-09-16 | International Business Machines Corporation | Method of fabricating a profile control in interconnect structures |
US10319630B2 (en) * | 2012-09-27 | 2019-06-11 | Stmicroelectronics, Inc. | Encapsulated damascene interconnect structure for integrated circuits |
US9412648B1 (en) * | 2016-01-11 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via patterning using multiple photo multiple etch |
US9818689B1 (en) * | 2016-04-25 | 2017-11-14 | Globalfoundries Inc. | Metal-insulator-metal capacitor and methods of fabrication |
US10755972B2 (en) * | 2016-11-29 | 2020-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
-
2016
- 2016-11-29 CN CN201611066883.1A patent/CN108122820B/zh active Active
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2017
- 2017-09-26 US US15/716,261 patent/US10553536B2/en active Active
- 2017-11-27 EP EP17203759.0A patent/EP3327762B1/en active Active
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2020
- 2020-01-06 US US16/734,610 patent/US11373949B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0226385A1 (en) * | 1985-12-02 | 1987-06-24 | Tektronix, Inc. | Rhodium capped gold IC metallization |
CN1242107A (zh) * | 1996-12-16 | 2000-01-19 | 国际商业机器公司 | 集成电路芯片上的电镀互连结构 |
CN1412821A (zh) * | 2001-10-15 | 2003-04-23 | 新光电气工业株式会社 | 在硅基片上形成通孔或凹陷的方法 |
CN1885524A (zh) * | 2005-06-24 | 2006-12-27 | 米辑电子股份有限公司 | 线路组件结构制造方法及其结构 |
CN105789114A (zh) * | 2012-09-24 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制造方法 |
CN107026115A (zh) * | 2015-12-15 | 2017-08-08 | 台湾积体电路制造股份有限公司 | 至部分填充的沟槽的通孔互连件 |
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US11373949B2 (en) | 2022-06-28 |
US20200144175A1 (en) | 2020-05-07 |
US10553536B2 (en) | 2020-02-04 |
US20180151488A1 (en) | 2018-05-31 |
CN108122820A (zh) | 2018-06-05 |
EP3327762A1 (en) | 2018-05-30 |
EP3327762B1 (en) | 2019-09-11 |
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