US7189638B2 - Method for manufacturing metal structure using trench - Google Patents
Method for manufacturing metal structure using trench Download PDFInfo
- Publication number
- US7189638B2 US7189638B2 US10/739,578 US73957803A US7189638B2 US 7189638 B2 US7189638 B2 US 7189638B2 US 73957803 A US73957803 A US 73957803A US 7189638 B2 US7189638 B2 US 7189638B2
- Authority
- US
- United States
- Prior art keywords
- trench
- semiconductor substrate
- seed layer
- insulating layer
- metal material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000002184 metal Substances 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000007769 metal material Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 33
- 238000007796 conventional method Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Definitions
- the present invention relates to a method for manufacturing a semiconductor. More particularly, the present invention relates to a method for manufacturing a metal structure by filling a trench formed in a substrate with a metal material.
- a trench having a higher aspect ratio is filled with a metal material to be used for interlayer electrical connections in multi-layered structures, or to form a third structure with other structures.
- FIGS. 1A to 1C illustrate schematic cross-sectional views showing an example of a prior art method for manufacturing a metal structure by means of a trench.
- a semiconductor substrate 10 is etched to a desired shape and depth by means of a patterning process, thereby forming a trench 15 .
- a seed layer 12 is deposited over the semiconductor substrate 10 having the trench 15 .
- a plating process is performed on the semiconductor substrate 10 deposited with the seed layer 12 , as shown in FIG. 1B .
- the seed layer 12 and a metal material 14 on the semiconductor substrate 10 are physically or chemically etched, as shown in FIG. 1C .
- the metal structure is present in the semiconductor substrate 10 , it is possible to easily manufacture a multi-layered structure.
- the structure is formed by filling the trench 15 with the metal material 14 .
- the inlet of the trench may become clogged before the trench 15 , which has a higher aspect ratio, can be completely filled with the metal material 14 .
- an undesirable void 16 is generated, causing reliability of the fabricated device to be degraded.
- FIGS. 2A to 2C illustrate schematic views showing an example of another prior art method for manufacturing a metal structure by means of a trench.
- this method for manufacturing the metal structure first, a seed layer 22 is deposited over a semiconductor substrate 20 , as shown in FIG. 2A , and a mold 23 is formed over the deposited seed layer 22 to form a trench 25 . Then, the trench 25 formed by the mold 23 is filled with a metal material 24 , as shown in FIG. 2B . Thereafter, the mold 23 and the seed layer 22 underlying the mold 23 are removed, as shown in FIG. 2C .
- the method for manufacturing the metal structure on the semiconductor substrate 20 by means of the mold 23 is very easy.
- the metal structure is formed on the semiconductor substrate 20 by means of the mold 23 , there is a problem that subsequent processes become very difficult when manufacturing a multi-layered structure.
- a planar structure is formed on a plated structure, a plurality of processes must be added, thereby increasing complexity and cost of the manufacturing process.
- the present invention provides a method for manufacturing a metal structure using a trench in which, when forming a multi-layered structure, subsequent processes may be easily carried out, thereby simplifying the manufacturing process.
- a feature of an embodiment of the present invention to provide a method for manufacturing a metal structure using a trench, the method including etching a semiconductor substrate to form a trench, depositing a seed layer over the semiconductor substrate including in the trench, stacking an insulating layer over the seed layer, removing a portion of the insulating layer to expose a portion of the seed layer at a bottom of the trench, filling the trench with a metal material and removing the seed layer and the insulating layer on the semiconductor substrate.
- removing the portion of the insulating layer comprises removing a portion of the insulating layer formed on the bottom of the trench.
- a method of manufacturing a metal structure using a trench of the present invention it is possible to prevent an inlet of the trench from becoming clogged with a metal layer in a plating process, and since the metal structure is formed in a trench in the semiconductor substrate, subsequent processes for manufacturing a multi-layered structure are simplified.
- FIGS. 1A to 1C illustrate cross-sectional views sequentially showing an example of a prior art process of manufacturing a metal structure by means of a trench;
- FIGS. 2A to 2C illustrate cross-sectional views sequentially showing an example of another prior art process of manufacturing a metal structure by means of a trench
- FIGS. 3A to 3C illustrate sequential process steps of manufacturing a metal structure by means of a trench according to an embodiment of the present invention.
- FIGS. 3A to 3C show processes of manufacturing a metal structure using a trench according to an embodiment of the present invention.
- a semiconductor substrate 100 is etched to a desired depth and width by means of a patterning process to form a trench 105 .
- a seed layer 102 is deposited over the semiconductor substrate 100 including in the trench 105 .
- an insulating layer 103 is stacked over the seed layer 102 .
- a portion of the insulating layer 103 on a bottom of the trench 105 is removed so that the seed layer 102 is exposed at the bottom of the trench 105 .
- FIG. 3A illustrates a cross-sectional view of the semiconductor substrate 100 having the trench 105 in which the seed layer 102 is exposed at the bottom thereof.
- the trench 105 having the exposed seed layer 102 is filled with a metal material 104 by a plating process, as shown in FIG. 3B .
- the insulating layer 103 functions as a protective film that prevents the inlet of the trench 105 from becoming clogged before the trench 105 is completely filled with the metal material 104 .
- the metal material 104 is upwardly grown from the bottom of the trench 105 , to cause the grown metal material 104 to follow the shape of the trench 105 .
- FIG. 3B illustrates a cross-sectional view of the semiconductor substrate 100 having the trench 105 filled with the metal material 104 by means of the plating process.
- FIG. 3C illustrates a view of the semiconductor substrate after etching the insulating layer 103 and the seed layer 102 .
- a method of forming a metal structure using a trench includes forming a trench in a semiconductor substrate, forming a seed layer at the bottom of the trench, protecting an opening of the trench with an insulating layer, and performing a plating process to grow the metal material from the bottom of the trench on the seed layer to form the metal structure.
- the present invention it is possible by the present invention to obtain a semiconductor substrate having a metal structure formed therein by an easy manufacturing process, while preventing an inlet of a trench from becoming clogged in a plating process.
- a step of removing a mold is eliminated in the present invention.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method for manufacturing a metal structure using a trench includes etching a semiconductor substrate to form a trench, depositing a seed layer over the semiconductor substrate including in the trench, stacking an insulating layer over the seed layer, removing a portion of the insulating layer to expose a portion of the seed layer at a bottom of the trench, filling the trench with a metal material, and removing the seed layer and the insulating layer on the semiconductor substrate. As a result, a subsequent process in forming a multi-layered structure may be easily carried out, thereby simplifying a manufacturing process.
Description
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor. More particularly, the present invention relates to a method for manufacturing a metal structure by filling a trench formed in a substrate with a metal material.
2. Description of the Prior Art
As semiconductor fabrication technology advances, it is possible to manufacture semiconductor devices having higher aspect ratios, i.e., higher ratios of width to depth of trenches. Also, in a conventional method, a trench having a higher aspect ratio is filled with a metal material to be used for interlayer electrical connections in multi-layered structures, or to form a third structure with other structures.
However, a problem may arise in a case that the structure is formed by filling the trench 15 with the metal material 14. Because the entire surface of the semiconductor substrate 10 that is deposited with the seed layer 12 is subjected to plating during a plating process, the inlet of the trench may become clogged before the trench 15, which has a higher aspect ratio, can be completely filled with the metal material 14. In this case, an undesirable void 16 is generated, causing reliability of the fabricated device to be degraded.
As such, the method for manufacturing the metal structure on the semiconductor substrate 20 by means of the mold 23 is very easy. However, in a case where the metal structure is formed on the semiconductor substrate 20 by means of the mold 23, there is a problem that subsequent processes become very difficult when manufacturing a multi-layered structure. Particularly, in a case in which a planar structure is formed on a plated structure, a plurality of processes must be added, thereby increasing complexity and cost of the manufacturing process.
In an effort to overcome the aforementioned problems, the present invention provides a method for manufacturing a metal structure using a trench in which, when forming a multi-layered structure, subsequent processes may be easily carried out, thereby simplifying the manufacturing process.
To provide these and other features and advantages, it is a feature of an embodiment of the present invention to provide a method for manufacturing a metal structure using a trench, the method including etching a semiconductor substrate to form a trench, depositing a seed layer over the semiconductor substrate including in the trench, stacking an insulating layer over the seed layer, removing a portion of the insulating layer to expose a portion of the seed layer at a bottom of the trench, filling the trench with a metal material and removing the seed layer and the insulating layer on the semiconductor substrate. Preferably, removing the portion of the insulating layer comprises removing a portion of the insulating layer formed on the bottom of the trench.
According to a method of manufacturing a metal structure using a trench of the present invention, it is possible to prevent an inlet of the trench from becoming clogged with a metal layer in a plating process, and since the metal structure is formed in a trench in the semiconductor substrate, subsequent processes for manufacturing a multi-layered structure are simplified.
The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
Korean patent application no. 2002-81580, filed on Dec. 20, 2003, and entitled, “Method For Manufacturing Metal Structure Using Trench,” is incorporated by reference herein in its entirety.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout
In the method for manufacturing a metal structure using a trench according to an embodiment of the present invention first, a semiconductor substrate 100 is etched to a desired depth and width by means of a patterning process to form a trench 105. Then, a seed layer 102 is deposited over the semiconductor substrate 100 including in the trench 105. Subsequently, an insulating layer 103 is stacked over the seed layer 102. Thereafter, a portion of the insulating layer 103 on a bottom of the trench 105 is removed so that the seed layer 102 is exposed at the bottom of the trench 105. FIG. 3A illustrates a cross-sectional view of the semiconductor substrate 100 having the trench 105 in which the seed layer 102 is exposed at the bottom thereof.
The trench 105 having the exposed seed layer 102 is filled with a metal material 104 by a plating process, as shown in FIG. 3B . When the trench 105 is filled with the metal material 104, the insulating layer 103 functions as a protective film that prevents the inlet of the trench 105 from becoming clogged before the trench 105 is completely filled with the metal material 104. Thereby, the metal material 104 is upwardly grown from the bottom of the trench 105, to cause the grown metal material 104 to follow the shape of the trench 105. FIG. 3B illustrates a cross-sectional view of the semiconductor substrate 100 having the trench 105 filled with the metal material 104 by means of the plating process.
Subsequently, the insulating layer 103 and the seed layer 102 on the semiconductor substrate 100 subjected to the plating process are etched. Thus, it is possible to obtain the semiconductor substrate having a metal structure formed therein. FIG. 3C illustrates a view of the semiconductor substrate after etching the insulating layer 103 and the seed layer 102.
As described above, a method of forming a metal structure using a trench according to an embodiment of the present invention includes forming a trench in a semiconductor substrate, forming a seed layer at the bottom of the trench, protecting an opening of the trench with an insulating layer, and performing a plating process to grow the metal material from the bottom of the trench on the seed layer to form the metal structure.
Thus, it is possible by the present invention to obtain a semiconductor substrate having a metal structure formed therein by an easy manufacturing process, while preventing an inlet of a trench from becoming clogged in a plating process. In addition, a step of removing a mold is eliminated in the present invention.
Further, in accordance with a method of forming a metal structure using a trench in an embodiment of the present invention, since the metal structure is formed in a semiconductor substrate, a subsequent process for manufacturing a multi-layered structure is simplified.
Preferred embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Claims (8)
1. A method for manufacturing a metal structure using a trench, the method comprising:
etching a semiconductor substrate to form a trench;
depositing a seed layer over the semiconductor substrate including in the trench;
stacking an insulating layer over the seed layer;
removing a portion of the insulating layer only at a bottom of the trench to expose a portion of the seed layer at the bottom of the trench;
filling the trench with a metal material; and
removing the seed layer and the insulating layer on the semiconductor substrate, wherein at least a portion of the deposited seed layer extending substantially parallel to a plane along which the semiconductor substrate extends directly contacts the semiconductor substrate.
2. The method as claimed in claim 1 , where etching the semiconductor substrate comprises using a patterning process.
3. The method as claimed in claim 1 , where filling the trench with a metal material comprises plating the metal material on the exposed portion of the seed layer at the bottom of the trench.
4. The method as claimed in claim 3 , where the metal material fills the trench from the bottom, growing upward.
5. The method as claimed in claim 3 , where the metal material conforms to the shape of the trench.
6. The method as claimed in claim 3 , where the metal material fills in the trench without any voids.
7. A method for manufacturing a metal structure using a trench, the method comprising:
etching a semiconductor substrate to form a trench;
depositing a seed layer over the semiconductor substrate including in the trench, the seed layer directly contacting the semiconductor substrate;
stacking an insulating layer over the seed layer;
removing a portion of the insulating layer only at a bottom of the trench to expose a portion of the seed layer at the bottom of the trench;
filling the trench with a metal material; and
removing the seed layer and the insulating layer on the semiconductor substrate.
8. A method for manufacturing a metal structure using a trench, the method comprising:
etching a semiconductor substrate to form a trench;
depositing a seed layer over the semiconductor substrate including in the trench;
stacking an insulating layer over the seed layer;
removing a portion of the insulating layer only at a bottom of the trench to expose a portion of the seed layer at the bottom of the trench;
filling the trench with a metal material; and
removing the seed layer and the insulating layer on the semiconductor substrate after filling the trench with the metal material, wherein when the trench is filled with the metal material, a portion of the seed layer extending substantially parallel to an upper surface of the semiconductor substrate is covered by a portion of the insulating layer remaining after the insulating layer at the bottom of the trench is removed.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2002-81580 | 2002-12-20 | ||
| KR10-2002-0081580A KR100449026B1 (en) | 2002-12-20 | 2002-12-20 | Method for manufacturing metal structure using trench |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20040219778A1 US20040219778A1 (en) | 2004-11-04 |
| US7189638B2 true US7189638B2 (en) | 2007-03-13 |
Family
ID=32388340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/739,578 Expired - Lifetime US7189638B2 (en) | 2002-12-20 | 2003-12-19 | Method for manufacturing metal structure using trench |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7189638B2 (en) |
| EP (1) | EP1432026A1 (en) |
| JP (1) | JP2004207728A (en) |
| KR (1) | KR100449026B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080182409A1 (en) * | 2007-01-31 | 2008-07-31 | Robert Seidel | Method of forming a metal layer over a patterned dielectric by electroless deposition using a selectively provided activation layer |
| US20150140809A1 (en) * | 2010-10-06 | 2015-05-21 | International Business Machines Corporation | Integrated circuit and interconnect, and method of fabricating same |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170002113U (en) | 2015-12-07 | 2017-06-15 | 주식회사 에이에프프라텍 | Cup lid |
| CN114141699A (en) * | 2020-09-04 | 2022-03-04 | 盛合晶微半导体(江阴)有限公司 | Semiconductor structure and preparation method thereof |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5098860A (en) * | 1990-05-07 | 1992-03-24 | The Boeing Company | Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers |
| JPH0590262A (en) | 1991-09-27 | 1993-04-09 | Nec Corp | Semiconductor device and manufacture thereof |
| US5723387A (en) * | 1996-07-22 | 1998-03-03 | Industrial Technology Research Institute | Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates |
| US6080656A (en) * | 1999-09-01 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Method for forming a self-aligned copper structure with improved planarity |
| JP2000188293A (en) | 1998-12-18 | 2000-07-04 | Texas Instr Inc <Ti> | Method for optimizing chemical-mechanical polishing of copper in copper interconnecting process for integrated circuit |
| US6110817A (en) * | 1999-08-19 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method for improvement of electromigration of copper by carbon doping |
| US6197181B1 (en) * | 1998-03-20 | 2001-03-06 | Semitool, Inc. | Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece |
| US6224737B1 (en) * | 1999-08-19 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | Method for improvement of gap filling capability of electrochemical deposition of copper |
| US6350364B1 (en) * | 2000-02-18 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Method for improvement of planarity of electroplated copper |
| US6492268B1 (en) * | 1999-12-22 | 2002-12-10 | Hyundai Electronics Industries Co., Ltd. | Method of forming a copper wiring in a semiconductor device |
| US6699396B1 (en) * | 2001-06-29 | 2004-03-02 | Novellus Systems, Inc. | Methods for electroplating large copper interconnects |
-
2002
- 2002-12-20 KR KR10-2002-0081580A patent/KR100449026B1/en not_active IP Right Cessation
-
2003
- 2003-12-18 EP EP03257982A patent/EP1432026A1/en not_active Withdrawn
- 2003-12-19 JP JP2003421878A patent/JP2004207728A/en active Pending
- 2003-12-19 US US10/739,578 patent/US7189638B2/en not_active Expired - Lifetime
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5098860A (en) * | 1990-05-07 | 1992-03-24 | The Boeing Company | Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers |
| US5436504A (en) | 1990-05-07 | 1995-07-25 | The Boeing Company | Interconnect structures having tantalum/tantalum oxide layers |
| JPH0590262A (en) | 1991-09-27 | 1993-04-09 | Nec Corp | Semiconductor device and manufacture thereof |
| US5420068A (en) | 1991-09-27 | 1995-05-30 | Nec Corporation | Semiconductor integrated circuit and a method for manufacturing a fully planar multilayer wiring structure |
| US5723387A (en) * | 1996-07-22 | 1998-03-03 | Industrial Technology Research Institute | Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates |
| US6197181B1 (en) * | 1998-03-20 | 2001-03-06 | Semitool, Inc. | Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece |
| JP2000188293A (en) | 1998-12-18 | 2000-07-04 | Texas Instr Inc <Ti> | Method for optimizing chemical-mechanical polishing of copper in copper interconnecting process for integrated circuit |
| US6162728A (en) | 1998-12-18 | 2000-12-19 | Texas Instruments Incorporated | Method to optimize copper chemical-mechanical polishing in a copper damascene interconnect process for integrated circuit applications |
| US6110817A (en) * | 1999-08-19 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method for improvement of electromigration of copper by carbon doping |
| US6224737B1 (en) * | 1999-08-19 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | Method for improvement of gap filling capability of electrochemical deposition of copper |
| US6080656A (en) * | 1999-09-01 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Method for forming a self-aligned copper structure with improved planarity |
| US6492268B1 (en) * | 1999-12-22 | 2002-12-10 | Hyundai Electronics Industries Co., Ltd. | Method of forming a copper wiring in a semiconductor device |
| US6350364B1 (en) * | 2000-02-18 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Method for improvement of planarity of electroplated copper |
| US6699396B1 (en) * | 2001-06-29 | 2004-03-02 | Novellus Systems, Inc. | Methods for electroplating large copper interconnects |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080182409A1 (en) * | 2007-01-31 | 2008-07-31 | Robert Seidel | Method of forming a metal layer over a patterned dielectric by electroless deposition using a selectively provided activation layer |
| US20150140809A1 (en) * | 2010-10-06 | 2015-05-21 | International Business Machines Corporation | Integrated circuit and interconnect, and method of fabricating same |
| US9390969B2 (en) * | 2010-10-06 | 2016-07-12 | GlobalFoundries, Inc. | Integrated circuit and interconnect, and method of fabricating same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004207728A (en) | 2004-07-22 |
| KR100449026B1 (en) | 2004-09-18 |
| US20040219778A1 (en) | 2004-11-04 |
| KR20040055016A (en) | 2004-06-26 |
| EP1432026A1 (en) | 2004-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2934353B2 (en) | Semiconductor device and manufacturing method thereof | |
| US7737027B2 (en) | Method of manufacturing a semiconductor device | |
| US7189638B2 (en) | Method for manufacturing metal structure using trench | |
| US20080286962A1 (en) | Method for fabricating metal pad | |
| JPH03248534A (en) | Manufacture of semiconductor element | |
| JP2616134B2 (en) | SOI transistor stacked semiconductor device and method of manufacturing the same | |
| CN108122820B (en) | Interconnect structure and method of making the same | |
| JPH04134827A (en) | Manufacture of semiconductor device | |
| JPH0797581B2 (en) | Method for manufacturing semiconductor device | |
| US5804504A (en) | Method for forming wiring of semiconductor device | |
| KR0134108B1 (en) | Fabrication method of semiconductor device | |
| KR100698741B1 (en) | Method for forming metal wiring layer of semiconductor device | |
| US6599825B2 (en) | Method for forming wiring in semiconductor device | |
| KR960004078B1 (en) | Contact forming method by stacked thin layer structure | |
| JPH07106419A (en) | Fabrication of semiconductor device | |
| KR100284302B1 (en) | Method for forming metal wire of semiconductor device | |
| KR0156122B1 (en) | Fabrication method of semiconductor device | |
| KR100313529B1 (en) | Wiring forming method for semiconductor device | |
| KR100571408B1 (en) | Dual damascene wiring manufacturing method of semiconductor device | |
| KR100207530B1 (en) | Process for forming contact hole in semiconductor device | |
| JPH08236621A (en) | Fabrication of semiconductor device | |
| JPH08293552A (en) | Forming method of plug | |
| JPH0453130A (en) | Semiconductor device and manufacture thereof | |
| KR20050041431A (en) | Method for forming gate of semiconductor device | |
| JPH07321201A (en) | Method of forming interconnection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIM, DONG-SIK;NA, KYUNG-WON;CHOI, SANG-ON;AND OTHERS;REEL/FRAME:015517/0316 Effective date: 20040617 |
|
| FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
| STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
| FPAY | Fee payment |
Year of fee payment: 4 |
|
| FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
| FPAY | Fee payment |
Year of fee payment: 8 |
|
| MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |