JP2006179570A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP2006179570A
JP2006179570A JP2004369230A JP2004369230A JP2006179570A JP 2006179570 A JP2006179570 A JP 2006179570A JP 2004369230 A JP2004369230 A JP 2004369230A JP 2004369230 A JP2004369230 A JP 2004369230A JP 2006179570 A JP2006179570 A JP 2006179570A
Authority
JP
Japan
Prior art keywords
chip
mother
semiconductor device
solder
daughter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004369230A
Other languages
English (en)
Inventor
Toshihiro Iwasaki
俊寛 岩崎
Michitaka Kimura
通孝 木村
Kozo Harada
耕三 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004369230A priority Critical patent/JP2006179570A/ja
Priority to US11/241,986 priority patent/US7443036B2/en
Priority to KR1020050107767A priority patent/KR20060071310A/ko
Publication of JP2006179570A publication Critical patent/JP2006179570A/ja
Priority to US12/172,812 priority patent/US7745258B2/en
Priority to KR1020120098253A priority patent/KR101268238B1/ko
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

【課題】 マザーチップを回路基板上にフリップチップ接続するために用いる半田ボールを効率的に形成することができる半導体装置の製造方法を得る。
【解決手段】 本発明の半導体装置の製造方法は、マザーチップの回路面に半田ボールを形成する第１工程と、第１工程の後に、マザーチップの回路面にドータチップをフリップチップ接続する第２工程と、半田ボールを用いて回路基板上にマザーチップをフリップチップ接続する第３工程とを有する。
【選択図】 図１

Description

本発明は、マザーチップにドータチップをフリップチップ接続し、更にマザーチップを回路基板上にフリップチップ接続する半導体装置の製造方法に関し、特に、マザーチップを回路基板上にフリップチップ接続するために用いる半田ボールを効率的に形成することができる半導体装置の製造方法に関するものである。
近年、マザーチップにドータチップをフリップチップ接続したＣＯＣ（チップ・オン・チップ）構造を有し、更にマザーチップを回路基板にフリップチップ接続した半導体装置が提案されている（例えば、特許文献１参照）。この半導体装置を製造する際に、従来は、マザーチップの回路面にドータチップをフリップチップ接続した後に、マザーチップの回路面に半田ボールを形成し、この半田ボールを用いてマザーチップを回路基板上にフリップチップ接続していた。
特開２００４−１４６７２８号公報
マザーチップと回路基板を接続する半田ボールの数は多く、例えば１０００個以上である。従って、半田ボールを効率的に形成するために、ウェハ上に形成された複数のマザーチップに対して一括して実施する枚葉式の半田ボール形成方法を用いる必要がある。
このような枚葉式の半田ボール形成方法として、マザーチップの回路面にレジストを塗布し、そのレジストの開口に半田ペーストを充填させる方法と、マザーチップの回路面にメタルマスクを重ね合わせ、そのメタルマスクの開口に半田ペーストを充填する方法がある。
しかし、従来のＣＯＣ型の半導体装置の製造工程では、半田ボールを形成する際、マザーチップの表面は、ドータチップが接続されていて平坦ではない。従って、レジストを均一に塗布することができず、また、表面の凹凸に合わせて薄いメタルマスクを加工するのも困難であるため、上記の枚葉式の半田ボール形成方法を用いることができなかった。
本発明は、上述のような課題を解決するためになされたもので、その目的は、マザーチップを回路基板上にフリップチップ接続するために用いる半田ボールを効率的に形成することができる半導体装置の製造方法を得るものである。
本発明に係る半導体装置の製造方法は、マザーチップの回路面に半田ボールを形成する第１工程と、第１工程の後に、マザーチップの回路面にドータチップをフリップチップ接続する第２工程と、半田ボールを用いて回路基板上にマザーチップをフリップチップ接続する第３工程とを有する。本発明のその他の特徴は以下に明らかにする。
本発明は、マザーチップの回路面にドータチップをフリップチップ接続する前の凹凸が少ない段階で半田ボールを形成するため、枚葉式の半田ボール形成方法を用いることができる。このため、マザーチップを回路基板上にフリップチップ接続するために用いる半田ボールを効率的に形成することができる。
実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置の製造方法を示すフローチャートである。このフローチャート及び図２〜４を参照しながら、実施の形態１に係る半導体装置の製造方法について説明する。
まず、マザーチップ１０の製造工程及び半田ボールの形成工程について説明する。図２（ａ）に示すように、基板１１上（回路面）にＡｌ電極１２を形成し、それ以外の領域を表面保護膜１３で覆う。そして、このＡｌ電極１２にプローブを当てて検査を行う（ステップＳ１）。この検査はウェハ上に形成された複数のマザーチップ１０に対してそれぞれ行い、ウェハ上の各マザーチップ１０の合否を示すウェハマップを作成する。
次に、図２（ｂ）に示すように、全面にＣｕ，Ｎｉ，Ｃｒ，Ｗ等の多層膜からなるバリアメタル１４をスパッタ技術又はめっき技術等により形成する。そして、図２（ｃ）に示すように、Ａｌ電極１２の存在する領域に開口を有するレジスト１５を形成し、レジスト１５の開口にめっき技術によりＣｕ等を充填してメタルポスト１６を形成する。その後、図２（ｄ）に示すように、レジスト１５を除去し、メタルポスト１６をマスクとしてバリアメタル１４を異方性エッチングする（ステップＳ２）。なお、メタルポスト１６の厚みは１５μｍ程度、メタルポスト１６同士のピッチは２０〜１００μｍである。
次に、図２（ｅ）に示すように、半田ボール（後述）を形成する領域に開口を有するレジスト１７を形成し、レジスト１７の開口に半田ペースト１８をめっき技術により充填する（ステップＳ３）。なお、メタルポスト１６の表面に極薄い金めっきを施すと、半田ペースト１８との濡れ性を確保することができるので好ましい。
次に、レジスト１７を除去した後に、マザーチップ１０を加熱して半田ペースト１８を溶融（リフロー）して半田ボール１９を形成する（ステップＳ４）。その後、洗浄（ステップＳ５）及び外観検査（ステップＳ６）を行う。以上の工程により、マザーチップ１０の回路面に半田ボールが形成される。
次に、ドータチップ２０の製造工程について説明する。図３（ａ）に示すように、基板２１上（回路面）にＡｌ電極２２を形成し、それ以外の領域を表面保護膜２３で覆う。そして、このＡｌ電極２２にプローブを当てて検査を行う（ステップＳ７）。この検査はウェハ上に形成された複数のドータチップ２０に対してそれぞれ行い、ウェハ上の各ドータチップ２０の合否を示すウェハマップを作成する。
次に、図３（ｂ）に示すように、全面にＣｕ，Ｎｉ，Ｃｒ，Ｗ等の多層膜からなるバリアメタル２４をスパッタ技術又はめっき技術等により形成する。そして、図３（ｃ）に示すように、Ａｌ電極２２の存在する領域に開口を有するレジスト２５を形成し、レジスト２５の開口にめっき技術によりＣｕ等を充填してメタルポスト２６を形成し、その上に半田等の接合部材２７を形成する。その後、図３（ｄ）に示すように、レジスト２５を除去し、メタルポスト２６及び接合部材２７をマスクとしてバリアメタル２４を異方性エッチングする（ステップＳ８）。なお、メタルポスト１６の厚みは１５μｍ程度、メタルポスト１６同士のピッチは２０〜１００μｍである。
次に、図３（ｅ）に示すように、ウェハ上に形成された複数のドータチップ２０をダイシングにより個々に分離する（ステップＳ９）。以上の工程により、ドータチップ２０が形成される。なお、ドータチップ２０としては、チップコンデンサ等の受動素子や、メモリ等の能動素子を用いることができる。
次に、マザーチップの回路面にドータチップをフリップチップ接続する工程及びマザーチップを回路基板にフリップチップ接続する工程について説明する。
まず、ステップＳ１のプローブ検査及びステップＳ６の外観検査で合格したマザーチップ１０の回路面に、ステップＳ７のプローブ検査で合格したドータチップ２０をフリップチップ接続する（ステップＳ１０）。
具体的には、まず、図４（ａ）に示すように、マザーチップ１０をステージ３１に載せ、ドータチップ２０をハンドル部３２により保持して、互いの回路面を向かい合わせる。そして、ドータチップ２０をハンドル部３２に設けられたヒータにより半田の融点（１８３℃）よりも高温、例えば３００℃に加熱して、マザーチップ１０上に設けられたメタルポスト１６とドータチップ２０上に設けられたメタルポスト２６とを接合部材２７を介して熱圧着させる。これにより、溶融しない材料で構成したメタルポスト１６，２６で挟まれた接合部材２７が大きく変化し溶融するため、接合部材２７の表面酸化膜が破壊され、フラックスレスで良好な接合が得られる。
ただし、この熱圧着の際に、ステージ３１に設けたヒータを調整して、マザーチップ１０の温度を半田ボール１９の融点よりも低く、例えば１００℃〜１５０℃にして半田ボール１９を再溶融させないようにする。これにより、再溶融による半田ボール１９の表面の酸化や、半田ボール１９同士のリンクを防ぐことができる。なお、ドータチップ２０を半田の融点よりも高温に保ったままフリップチップ接続するが、マザーチップ１０は熱伝導が良く、熱が広がり、マザーチップ１０を設置しているステージ３１は熱容量が大きいため、温度の上昇を抑制することができる。
次に、ウェハ上に形成された複数のマザーチップ１０をダイシングにより個々に分離する（ステップＳ１１）。そして、図４（ｂ）に示すように、半田ボール１９を用いて回路基板３３上にマザーチップ１０をフリップチップ接続する（ステップＳ１２）。なお、回路基板３３としては、多層有機基板、シリコンインターポーザ、チップ等を用いることができる。
その後、マザーチップ１０と回路基板３３の間に樹脂３４を注入してアンダーフィルを行う（ステップＳ１３）。また、外部接続用に回路基板３３の下面にアウターボール３５を形成する。
以上の工程により、マザーチップ１０の回路面にドータチップ２０がフリップチップ接続され、このマザーチップ１０が回路基板にフリップチップ接続された半導体装置が製造される。なお、この半導体装置において、半田ボール１９同士の間隔が２００μｍ程度、メタルポスト１６（又はメタルポスト２６）同士の間隔が２０〜１００μｍ、ドータチップ２０の厚みが５０〜３００μｍ、半田ボールの直径が１００μｍ、アウターボール３５同士の間隔が０．６〜１．８ｍｍである。
以上説明したように、マザーチップ１０の回路面にドータチップ２０をフリップチップ接続する前の凹凸が少ない段階で半田ボールを形成するため、枚葉式の半田ボール形成方法を用いることができる。このため、マザーチップ１０を回路基板上にフリップチップ接続するために用いる半田ボールを効率的に形成することができる。
なお、メタルポスト１６，２６としてＣｕを用い、接合部材２７としてＳｎを用いることができる。この場合、熱圧着により接合部材２７はＣｕＳｎ合金となる。または、メタルポスト１６としてＣｕを用い、メタルポスト２６としてＮｉを用い、接合部材２７としてＳｎＡｇ（融点２１２℃）を用いてもよい。接合部材が接合されるメタルポスト表面にはＡｕめっきを施し、濡れを確保するとよい。
また、プラズマ処理のような表面清浄化処理を実施することでもメタルポスト１６，２６を接合することができる。この場合、大きな圧力をかけた接合部材２７の変形により表面酸化膜を破壊する必要がなく、接合部材２７の量を低減しても接合でき、メタルポスト１６，２６側面への接合部材２７の漏れを減少することができ、メタルポスト１６，２６の高さを薄くすることができる。これにより、マザーチップ１０とドータチップ２０の間隔を狭くすることができるため、チップ間の樹脂の熱膨張による応力を低減することができる。
実施の形態２．
実施の形態２に係る半導体装置の製造方法は、マザーチップ１０の回路面に半田ペーストを堆積する工程が実施の形態１の図２（ｅ）とは異なる。その他の工程は、実施の形態１と同様である。
即ち、実施の形態２では、図５に示すように、マザーチップ１０の回路面に、半田ボールを形成する領域と開口が一致するようにメタルマスク３６を重ね合わせ、メタルマスク３６の開口に半田ペースト１８を印刷して充填する。その後、メタルマスク３６を取り外し、図２（ｆ）と同様に、マザーチップ１０を加熱して半田ペーストを溶融して半田ボールを形成する。
このように、マザーチップ１０の回路面に半田ボールを形成する工程において、実施の形態１ようなレジスト１７を用いる代わりにメタルマスク３６を用いても、実施の形態１と同様の効果を得ることができる。
実施の形態３．
実施の形態３に係る半導体装置の製造方法は、マザーチップ１０の回路面にドータチップ２０をフリップチップ接続する工程が実施の形態１の図４（ａ）とは異なる。その他の工程は、実施の形態１と同様である。
即ち、実施の形態３では、図６に示すように、メタルポスト１６，２６をＮｉで構成して、両者の表面にＡｕ膜３７，３８をそれぞれ形成する。または、メタルポスト１６，２６をＡｕで構成してもよい。そして、マザーチップ１０及びドータチップ２０を１５０℃に保った状態で、ドータチップ２０に超音波振動をかけて、マザーチップ１０上に設けられたメタルポストとドータチップ２０上に設けられたメタルポストとを熱圧着させる。
このように超音波振動をかけることにより、実施の形態１よりも低い温度で熱圧着ができるため、再溶融による半田ボール１９の表面の酸化や、半田ボール１９同士のリンクを防ぐことができる。
実施の形態４．
図７は、本発明の実施の形態４に係る半導体装置を示す断面図である。この半導体装置は、回路基板３３の上面に、ドータチップ２０に対応する領域に凹部３５を設けたものである。その他の構成は実施の形態１と同様である。これにより、ドータチップ２０が厚い場合でも、マザーチップ１０と回路基板３３を良好にフリップチップ接続することができる。
実施の形態５．
図８は、本発明の実施の形態５に係る半導体装置を示す断面図である。この半導体装置は、本発明をマザーチップ１０の回路面に再配線層４０を形成し、その上を表面保護膜４１で覆っている。ただし、ドータチップ２０を接続する領域には再配線層４０及び表面保護膜４１は形成しないようにする。これにより、メタルポスト１６，２６の高さを確保することができるため、アンダーフィルの際にチップ間に樹脂３４を注入しやすくなる。
実施の形態６．
図９は、本発明の実施の形態６に係る半導体装置を示す断面図である。この半導体装置は、マザーチップ１０の回路面に、ドータチップ２０の他に、チップコンデンサ４２が搭載されている。その他の構成は実施の形態１と同様である。
このようにチップコンデンサ等の受動素子と能動素子がマザーチップ１０上に混載した場合にも本発明を適用することができ、同様の効果を得ることができる。
また、マザーチップ１０に２以上のドータチップ２０をフリップチップ接続してもよい。この場合、ドータチップ２０として、例えば、フラッシュメモリとＤＲＡＭを用いることができる。
本発明の実施の形態１に係る半導体装置の製造方法を示すフローチャートである。 マザーチップの回路面に半田ボールを形成する工程を示す断面図である。 ドータチップを形成する工程を示す断面図である。 マザーチップの回路面にドータチップをフリップチップ接続する工程及びマザーチップを回路基板にフリップチップ接続する工程を示す断面図である。 本発明の実施の形態２に係る半導体装置を示す断面図である。 本発明の実施の形態３に係る半導体装置を示す断面図である。 本発明の実施の形態４に係る半導体装置を示す断面図である。 本発明の実施の形態５に係る半導体装置を示す断面図である。 本発明の実施の形態６に係る半導体装置を示す断面図である。
符号の説明
１０ マザーチップ
１７ レジスト
１６，２６ メタルポスト
１８ 半田ペースト
１９ 半田ボール
２０ ドータチップ
２７ 接合部材
３１ ステージ
３２ ハンドル部
３３ 回路基板
３５ 凹部
３６ メタルマスク
４０ 再配線層
４１ 表面保護膜
４２ チップコンデンサ

Claims (7)

  1. マザーチップの回路面に半田ボールを形成する第１工程と、
    前記第１工程の後に、前記マザーチップの回路面にドータチップをフリップチップ接続する第２工程と、
    前記半田ボールを用いて回路基板上に前記マザーチップをフリップチップ接続する第３工程とを有することを特徴とする半導体装置の製造方法。
  2. 前記第１工程は、ウェハ上に形成された複数のマザーチップに対して一括して実施し、
    前記第２工程の後に、前記複数のマザーチップをダイシングにより個々に分離して前記第３工程を実施することを特徴とする請求項１に記載の半導体装置の製造方法。
  3. 前記第１工程は、
    前記マザーチップの回路面に、前記半田ボールを形成する領域に開口を有するレジストを形成する工程と、
    前記レジストの開口に半田ペーストを充填する工程と、
    前記レジストを除去した後、前記マザーチップを加熱して前記半田を溶融して前記半田ボールを形成する工程とを有することを特徴とする請求項１又は２に記載の半導体装置の製造方法。
  4. 前記第１工程は、
    前記マザーチップの回路面に、前記半田ボールを形成する領域と開口が一致するようにメタルマスクを重ね合わせる工程と、
    前記メタルマスクの開口に半田ペーストを充填する工程と、
    前記メタルマスクを取り外した後、前記マザーチップを加熱して前記半田を溶融して前記半田ボールを形成する工程とを有することを特徴とする請求項１又は２に記載の半導体装置の製造方法。
  5. 前記第２工程において、前記マザーチップの温度を前記半田ボールの融点よりも低くして、前記半田ボールを再溶融させないことを特徴とする請求項１〜４の何れか１項に記載の半導体装置の製造方法。
  6. 前記第２工程において、前記ドータチップを加熱して、前記マザーチップ上に設けられたメタルポストと前記ドータチップ上に設けられたメタルポストとを接合部材を介して熱圧着させることを特徴とする請求項５に記載の半導体装置の製造方法。
  7. 前記第２工程において、前記ドータチップに超音波振動をかけて、前記マザーチップ上に設けられたメタルポストと前記ドータチップ上に設けられたメタルポストとを熱圧着させることを特徴とする請求項５に記載の半導体装置の製造方法。
JP2004369230A 2004-12-21 2004-12-21 半導体装置の製造方法 Pending JP2006179570A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2004369230A JP2006179570A (ja) 2004-12-21 2004-12-21 半導体装置の製造方法
US11/241,986 US7443036B2 (en) 2004-12-21 2005-10-04 Manufacturing method of semiconductor device
KR1020050107767A KR20060071310A (ko) 2004-12-21 2005-11-11 반도체 장치의 제조 방법
US12/172,812 US7745258B2 (en) 2004-12-21 2008-07-14 Manufacturing method of semiconductor device
KR1020120098253A KR101268238B1 (ko) 2004-12-21 2012-09-05 반도체 장치의 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004369230A JP2006179570A (ja) 2004-12-21 2004-12-21 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010093034A Division JP5187341B2 (ja) 2010-04-14 2010-04-14 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JP2006179570A true JP2006179570A (ja) 2006-07-06

Family

ID=36596472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004369230A Pending JP2006179570A (ja) 2004-12-21 2004-12-21 半導体装置の製造方法

Country Status (3)

Country Link
US (2) US7443036B2 (ja)
JP (1) JP2006179570A (ja)
KR (2) KR20060071310A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package
KR20190132478A (ko) * 2017-03-29 2019-11-27 자일링크스 인코포레이티드 고밀도 2.5d 및 3d 집적을 위한 인터커넥트 방법

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
US7582556B2 (en) 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
JP4687430B2 (ja) * 2005-12-06 2011-05-25 株式会社デンソー 電子装置およびその製造方法
US7850060B2 (en) * 2007-04-05 2010-12-14 John Trezza Heat cycle-able connection
US7748116B2 (en) * 2007-04-05 2010-07-06 John Trezza Mobile binding in an electronic connection
US20090166889A1 (en) * 2007-12-31 2009-07-02 Rajen Murugan Packaged integrated circuits having surface mount devices and methods to form packaged integrated circuits
CN103050420A (zh) * 2008-06-05 2013-04-17 丘费尔资产股份有限公司 对电连接中具有高迁移率的组分的束缚
US9608403B2 (en) * 2014-11-03 2017-03-28 International Business Machines Corporation Dual bond pad structure for photonics
US20180041003A1 (en) * 2016-08-08 2018-02-08 Intel Corporation Chip on chip (coc) package with interposer
US11404365B2 (en) * 2019-05-07 2022-08-02 International Business Machines Corporation Direct attachment of capacitors to flip chip dies

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9502178D0 (en) * 1995-02-03 1995-03-22 Plessey Semiconductors Ltd MCM-D Assemblies
WO1998040915A1 (fr) 1997-03-10 1998-09-17 Seiko Epson Corporation Composant electronique et dispositif a semi-conducteurs, procede de fabrication correspondant, carte a circuit imprime ainsi equipee, et equipement electronique comportant cette carte a circuit imprime
JPH11340270A (ja) 1998-05-29 1999-12-10 Matsushita Electric Ind Co Ltd はんだバンプ形成方法及び半導体モジュールの製造方法
US6504241B1 (en) * 1998-10-15 2003-01-07 Sony Corporation Stackable semiconductor device and method for manufacturing the same
JP3772066B2 (ja) 2000-03-09 2006-05-10 沖電気工業株式会社 半導体装置
JP2001308258A (ja) 2000-04-26 2001-11-02 Sony Corp 半導体パッケージ及びその製造方法
JP3735526B2 (ja) 2000-10-04 2006-01-18 日本電気株式会社 半導体装置及びその製造方法
JP2003059958A (ja) 2001-08-15 2003-02-28 Sony Corp マイクロバンプの形成方法
JP2004146728A (ja) 2002-10-28 2004-05-20 Sony Corp 半導体装置とその製造方法
JP2004253663A (ja) * 2003-02-20 2004-09-09 Sony Corp 半導体装置の製造方法、及び同製造方法に用いるチップボンディング装置
US7122906B2 (en) * 2004-01-29 2006-10-17 Micron Technology, Inc. Die-wafer package and method of fabricating same
JP2004356655A (ja) 2004-09-06 2004-12-16 Oki Electric Ind Co Ltd 半導体装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package
US9633973B2 (en) 2012-12-20 2017-04-25 Samsung Electronics Co., Ltd. Semiconductor package
KR20190132478A (ko) * 2017-03-29 2019-11-27 자일링크스 인코포레이티드 고밀도 2.5d 및 3d 집적을 위한 인터커넥트 방법
JP2020512703A (ja) * 2017-03-29 2020-04-23 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ 高密度２．５ｄおよび３ｄ集積のための相互接続の方法
JP7145169B2 (ja) 2017-03-29 2022-09-30 ザイリンクス インコーポレイテッド 高密度２．５ｄおよび３ｄ集積のための相互接続の方法
KR102496142B1 (ko) 2017-03-29 2023-02-03 자일링크스 인코포레이티드 반도체 구조물 및 집적 회로 패키지

Also Published As

Publication number Publication date
KR20120116373A (ko) 2012-10-22
US20080274590A1 (en) 2008-11-06
KR101268238B1 (ko) 2013-05-31
US7443036B2 (en) 2008-10-28
US20060134832A1 (en) 2006-06-22
US7745258B2 (en) 2010-06-29
KR20060071310A (ko) 2006-06-26

Similar Documents

Publication Publication Date Title
US7745258B2 (en) Manufacturing method of semiconductor device
JP5664392B2 (ja) 半導体装置、半導体装置の製造方法、及び配線基板の製造方法
JP6547745B2 (ja) 半導体装置およびその製造方法
TWI337056B (en) An electronic parts packaging structure
JP2001338947A (ja) フリップチップ型半導体装置及びその製造方法
JP6458801B2 (ja) 半導体装置およびその製造方法
JP2005129955A (ja) 超薄型フリップチップパッケージの製造方法
JP2006202969A (ja) 半導体装置およびその実装体
JP6586952B2 (ja) 半導体装置およびその製造方法
JP2002164369A (ja) 半導体装置およびその製造方法
JP6656836B2 (ja) 実装構造体及びその製造方法
JP2009218233A (ja) 半導体装置及びその製造方法
JP5187341B2 (ja) 半導体装置の製造方法
JP6544354B2 (ja) 半導体装置の製造方法
JP3116926B2 (ja) パッケージ構造並びに半導体装置、パッケージ製造方法及び半導体装置製造方法
JP2017028155A (ja) 半導体装置及びその製造方法
JP2007294560A (ja) 半導体装置およびその製造方法
JP6534700B2 (ja) 半導体装置の製造方法
JP2008047710A (ja) 半導体基板、半導体装置およびこれらの製造方法
JP2006108182A (ja) 半導体装置およびその実装体およびその製造方法
JP2004071906A (ja) 半導体装置
JP2004253598A (ja) 電子部品の実装方法
JP4668608B2 (ja) 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法
JP2004014571A (ja) 端子、半導体装置、端子形成方法及びフリップチップ型半導体装置の製造方法
JP3674550B2 (ja) 半導体装置

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071210

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090903

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090908

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091105

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100202