JP2020512703A - 高密度2.5dおよび3d集積のための相互接続の方法 - Google Patents
高密度2.5dおよび3d集積のための相互接続の方法 Download PDFInfo
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- JP2020512703A JP2020512703A JP2019553500A JP2019553500A JP2020512703A JP 2020512703 A JP2020512703 A JP 2020512703A JP 2019553500 A JP2019553500 A JP 2019553500A JP 2019553500 A JP2019553500 A JP 2019553500A JP 2020512703 A JP2020512703 A JP 2020512703A
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Abstract
Description
本開示の例は、概して集積回路に関し、より特定的には銅−銅(Cu−Cu)接合を用いた集積回路パッケージングに関する。
電子装置(たとえば、コンピュータ、ラップトップ、タブレット、コピー機、デジタルカメラ、スマートフォンなど)は、しばしば集積回路(IC:integrated circuit、「チップ」としても知られる)を用いる。これらの集積回路は、典型的には、集積回路パッケージにおいてパッケージされた半導体ダイとして実装される。半導体ダイは、メモリ、ロジック、および/または様々な他の好適な回路タイプの任意のものを含み得る。
本開示の1つの例は、半導体構造である。半導体構造は、一般的に、半導体層と、半導体層の上方に配置される接着層と、接着層の上方に配置されるアノード金属層と、アノード金属層の上方に配置されるカソード金属層とを含む。
いくつかの実施形態において、アノード金属層は、アルミニウム(Al)、亜鉛(Zn)、およびニッケル(Ni)からなる群から選択される元素を含み得る。
いくつかの実施形態において、アノード金属層の酸化電位は、カソード金属層の酸化電位よりも高いものであり得る。
本開示の別の例は、半導体構造を製造する方法である。上記方法は、概して、半導体の上方に接着層を配置することと、接着層の上方にアノード金属層を配置することと、アノード金属層の上方にカソード金属層を配置することとを含む。
本開示の上述の構成が詳細に理解されることが可能であるように、上記に要約された本開示のより特定的な説明が、実施例を参照することによってなされ得る。そのいくつかが、添付された図面に示される。しかしながら、添付された図面は、この開示の典型的な例示のみを示し、したがってその範囲の限定であると考えられるべきではなく、本開示のために他の等しく効果的な実施例が認められ得ることに留意されたい。
本開示の実施例は、酸化物生成に対する懸念が低減されたCu−Cu接合のための技術および装置を提供し、これにより、この接合のために特別な要求なく、低減温度(たとえば、高くとも200℃)およびより速いサイクル時間での十分な接合を提供する。本開示の実施例は、より長いキュー(queue)(Q)またはステージング時間も可能にし得る。
チップツーチップ(C2C)、チップツーウェハ(C2W)、およびウェハツーウェハ(W2W)接合技術は、チップおよび/またはウェハが様々なストレス(たとえば、温度、ひずみ、ねじれなど)に曝されるときに接続不良を回避するように実質的に堅牢である相互接続技術に頼っている。はんだ相互接続を有する銅(Cu)ピラーは、数十年もの間、低密度設計および高密度設計のための、この産業の主力商品であった。しかしながら、密度が増加し続け、ピッチが低減されるにつれて、このCuピラー技術は、低減されたはんだ体積、脆弱な金属間化合物(IMC:intermetallic compound)、ボイディング(voiding)、低熱伝導度などの様々な問題に直面している。銅−銅(Cu−Cu)接合は、数年もの間、産業によって追求されてきた代替的な相互接続であるが、今日まで、実用的なまたは大量製造(HVM:high volume manufacturing)の解決法を提示していない。Cu−Cu接合に対する1つの重大な課題は、十分な相互接続を阻害するCu表面上での急速な酸化物生成である。
集積回路(IC)ダイ(「チップ」ともよばれる)は、典型的には、回路基板(たとえば、プリント回路基板(PCB))との電気接続のためにパッケージに配置される。パッケージは、腐食の原因になり得る、起こり得る物理的ダメージおよび湿度から集積回路ダイを保護する。本開示の実施例は、このようなICパッケージを形成するためにチップツーチップ(C2C)、チップツーウェハ(C2W)、またはウェハツーウェハ(W2W)接合のために利用され得る。Cu−Cu接合は、本開示の実施例にしたがって、C2C、C2W、またはW2W集積を実施するために200℃未満の温度で行われ得る。
図5は、本開示の実施例にしたがう、半導体構造および/または半導体構造を含むパッケージ(たとえば、以下に記載されるようなICパッケージ)を製造するための例示の動作500のフロー図である。動作500の少なくとも一部は、たとえば、半導体処理室を含み得る半導体構造を製造するためのシステムによって行われ得る。
いくつかの実施例によれば、アノード金属層は、アルミニウム(Al)、亜鉛(Zn)、およびニッケル(Ni)からなる群から選択される元素を含む。
いくつかの実施例によれば、アノード金属層の酸化電位は、カソード金属層の酸化電位よりも高い。
Claims (14)
- 半導体層と、
前記半導体層の上方に配置される、接着層と、
前記接着層の上方に配置される、アノード金属層と、
前記アノード金属層の上方に配置される、カソード金属層と、を備える、半導体構造。 - 前記アノード金属層は、マグネシウム(Mg)を含む、請求項1に記載の半導体構造。
- 前記アノード金属層は、アルミニウム(Al)、亜鉛(Zn)、およびニッケル(Ni)からなる群から選択される元素を含む、請求項1に記載の半導体構造。
- 前記カソード金属層は、銅(Cu)を含む、請求項1から請求項3のいずれか1項に記載の半導体構造。
- 前記アノード金属層の酸化電位は、前記カソード金属層の酸化電位よりも高い、請求項1から請求項4のいずれか1項に記載の半導体構造。
- 前記アノード金属層は、第1金属を含み、前記カソード金属層は、第2金属を含み、前記第1金属は、前記第2金属よりも高い酸化電位を有する、請求項1から請求項5のいずれか1項に記載の半導体構造。
- 前記第1金属は、前記第2金属よりも負の酸化物生成のギブス自由エネルギを有する、請求項6に記載の半導体構造。
- 前記アノード金属層は、多孔質酸化物と関連する金属を含み、前記多孔質酸化物の酸化速度は、時間の関数として線形である、請求項1から請求項7のいずれか1項に記載の半導体構造。
- 前記アノード金属層は、1.0未満の酸化物−金属体積比を有する金属を含む、請求項1から請求項8のいずれか1項に記載の半導体構造。
- 前記アノード金属層は、前記カソード金属層にカソード防食を提供することによって前記カソード金属層と結び付く酸化物の成長を阻害するように構成される、請求項1から請求項9のいずれか1項に記載の半導体構造。
- 前記接着層は、チタン(Ti)を含み、前記半導体層は、シリコン(Si)を含む、請求項1から請求項10のいずれか1項に記載の半導体構造。
- 前記カソード金属層は、前記アノード金属層上に直接配置される、請求項1から請求項11のいずれか1項に記載の半導体構造。
- 前記カソード金属層は、1つ以上のピラーを備える、請求項1から請求項12のいずれか1項に記載の半導体構造。
- パッケージ基板と、
前記パッケージ基板の上方に配置される、複数のダイと、を備え、
前記複数のダイの少なくとも1つは、複数の銅ピラーマイクロバンプを介して複数のダイの別のものに電気的に接続され、
前記複数のダイの少なくとも1つは、
前記銅ピラーマイクロバンプを形成する、カソード金属層と、
前記カソード金属層の上方に配置される、アノード金属層と、
前記アノード金属層の上方に配置される、接着層と、
前記接着層の上方に配置される、半導体層と、を備え、
前記アノード金属層の酸化電位は、前記カソード金属層の酸化電位よりも高い、集積回路パッケージ。
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US20180286826A1 (en) | 2018-10-04 |
US10593638B2 (en) | 2020-03-17 |
KR102496142B1 (ko) | 2023-02-03 |
EP3580779B1 (en) | 2021-09-01 |
KR20190132478A (ko) | 2019-11-27 |
CN110476240A (zh) | 2019-11-19 |
CN110476240B (zh) | 2023-10-20 |
JP7145169B2 (ja) | 2022-09-30 |
EP3580779A1 (en) | 2019-12-18 |
WO2018183453A1 (en) | 2018-10-04 |
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