KR940004858A - 반도체장치 및 그 제작방법 - Google Patents

반도체장치 및 그 제작방법 Download PDF

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KR940004858A
KR940004858A KR1019930016789A KR930016789A KR940004858A KR 940004858 A KR940004858 A KR 940004858A KR 1019930016789 A KR1019930016789 A KR 1019930016789A KR 930016789 A KR930016789 A KR 930016789A KR 940004858 A KR940004858 A KR 940004858A
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film
silicon oxide
semiconductor device
oxide film
manufacturing
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KR0131062B1 (ko
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순페이 야마자끼
장홍용
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순페이 야마자끼
가부시키가이샤 한도오따이 에네루기 겐큐쇼
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Priority claimed from JP05191934A external-priority patent/JP3122699B2/ja
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Abstract

저온에서의 특성·신뢰성이 우수한 박막트랜지스터를 고 스루풋으로 제조효율이 양효하게 제조하는 방법을 제공한다. 이 방법은 절연기판상에 박막 트랜지스터(TFT)를 형성하는 공정에 있어서, 반로체피막을 형성한 후 TEOS를 원료로 하여 화학적 기상성장법에 의해 게이트 산화막이 되는 산화규소막을 제작하고, 바람직하게는 산소, 오존, 산화질소 분위기 중에서 이것에 펄스 레이저광 또는 자외광을 조사하는 것에 의해 산화규소막 중의 탄소나 탄화수소등의 클러스터를 제거하고, 따라서 막중의 트랩센터를 제거하여, 게이트 산화막으로서 적당한 특성을 나타내는 산화막으로 하는 것을 특징으로 하는 박막형 반도체장치의 제작방법이다.
또한, 산화규소막으로 이루어지는 게이트 절연막에 대하여 질소 이온을 주입하고, 이어서 적외광에 의한 어닐을 행하는 것에 의해 게이트 절연막을 산화 질화규소로 하여 내압의 향상, 비유전율의 향상, 막질의 치밀화를 실현한다. 이렇게 하는 것으로서 TFT의 특성을 안정화시켜 신뢰성을 향상시킨다.

Description

반도체장치 및 그 제작방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 TFT(박막 트랜지스터)의 제작 방법도,
제2도는 본 발명에 의한 TFT의 제작 방법도,
제3도는 본 발명에 사용한 레이저, 자외광 처리장치의 개념도,
제4도는 실시예의 제작 공정도,
제5도는 실시예의 제작 공정도,
제6도는 실시예의 제작 공정도,
제7도는 본 발명에 의한 TFT의 제작방법.

Claims (25)

  1. 절연 기판상에 반도체 피막을 형성하는 공정과, 상기 반도체 피막상에 유기실란 또는 그 일부의 수소, 탄소 또는 탄화 수소기를 불소에 의해 치환(치환)한 재료를 원료로 하는 화학적 기상 성장법에 의해 산화규소막을 형성하는 공정과, 상기 반도체피막 및 산화규소막에 펄프 레이저광 또는 그것과 동등의 강광을 조사하는 공정과, 상기 산화규소막상에 게이트 전극을 형성하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  2. 제1항에 있어서, 산화규소막을 기판온도 200-500℃에서 형성하는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  3. 제1항에 있어서, 게이트 전극 형성후, 게이트 전극을 주된 마스크로 하여 자기정합적으로 고속 이온을 조사하는 공정과, 상기 이온 조사후 상기 게이트 전극을 주된 마스크로하여 펄스레이저광 또는 그것과 동등의 강광을 조사하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  4. 제1항에 있어서, 상기 유기 실란은 테트라·에틸·옥시실란으로 이루어지는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  5. 제1항에 있어서, 상기 화학적 기상성장법은 플라즈마 CVD, 열 CVD, 포토 CVD 또는 포토 플라즈마 CVD인 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  6. 제1항에 있어서, 상기 조사 공정전에 상기 산화규소막을 400∼700℃의 질소 분위기 중에서 열어닐하는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  7. 제1항에 있어서, 상기 조사 공정후 상기 산화규소막을 400∼700℃의 질소 분위기 중에서 열어닐 하는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  8. 절연기판상에 반도체피막을 형성하는 공정과, 상기 반도체피막상에 레이저광 또는 그것과 동등의 강광에 대하여 실질적으로 투명한 보호절연막을 형성하는 공정과, 상기 반도체피막과 펄스레이저광 또는 그것과 동등의 강광을 조사하는 것에 의해 상기 반도체피막의 결정성을 개선시키는 공정과, 상기 보호 절연피막을 제거하는 것에 의해 상기 반도체피막 표면을 노출시키는 공정과, 유기실란 또는 그 일부의 수소, 탄소 또는 탄화수소기를 불소에 의해 치환한 재료를 원료로 하는 화학적 기상 성장법에 의해 산화규소막을 형성하는 공정과, 상기 반도체피막 및 산화규소막에 펄스 레이저광 또는 그것과 동등의 강광을 조사하는 공정과, 상기 산화규소막상에 게이트 전극을 형성하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  9. 제8항에 있어서, 산화규소막을 기판온도 200∼500℃에서 형성하는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  10. 제8항에 있어서, 게이트 전극 형성후 게이트 전극을 주된 마스크로하여 자기 정합적으로 고속 이온을 조사하는 공정과, 상기 이온 조사후 상기 게이트 전극을 주된 마스크로하여 펄스레이저광 또는 그것과 동등의 강광을 조사하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  11. 제8항에 있어서, 상기 유기실란은 테트라·에틸·옥시실란으로 이루어지는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  12. 제8항에 있어서, 상기 화학적 기상성장법은 플라즈마 CVD, 열 CVD, 포토 CVD 또는 포토플라즈마 CVD인 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  13. 제8항에 있어서, 상기 조사 공정전에 상기 산화규소막을 400∼700℃의 질소 분위기 중에서 열어닐 하는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  14. 제8항에 있어서, 상기 조사 공정후에 상기 산화규소막을 400∼700℃의 질소 또는 산화 분위기 중에서 열어닐 하는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  15. 절연기판상에, 반도체 피막을 형성하는 공정과, 상기 반도체 피막상에 유기실란 또는 그 일부의 수소, 탄소 탄화수소기를 불소에 의해 치환한 재료를 원료로 하는 화학적 기상성장법에 의해 산화규소막을 형성하는 공정과, 상기 반도체피막 및 산화규소막에 산소, 오존 또는 산화질소를 포함한 분위기 중에서 파장 300nm이하의 자외광을 조사하는 공정과, 상기 산화규소막상에 게이트 전극을 형성하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  16. 제15항에 있어서, 상기 유기실란은 테트라·에틸·옥시실란으로 이루어지는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  17. 제15항에 있어서, 상기 화학적 기상성장법은 플라즈마 CVD, 열 CVD, 포토 CVD 또는 포토플라즈마 CVD인 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  18. 절연기판상에 규소 반도체피막을 형성하는 공정과, 500∼700℃ 온도의 산화물 기체중에서 상기 규소 반도체피막의 표면을 산화하고, 그 표면에 20∼200Å의 두께의 제1의 산화규소층을 형성하는 공정과, 상기 제1의 산화규소층상에 유기실란 또는 그 일부의 수소, 탄소 또는 탄화수소기를 불소에 의해 치환한 재료를 원료로 하는 화학적 기상성장법에 의해 제2의 산화규소막을 형성하는 공정과, 상기 제2의 산화규소층을 광어닐하는 공정과, 상기 반도체피막 및 산화규소막에 펄스레이저광 또는 그것과 동등의 강광을 조사하는 공정과, 상기 산화규소막 상에 게이트 전극을 형성하는 공정을 갖는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  19. 제15항에 있어서, 상기 광어닐을 펄스 레이저광 또는 그것과 동등의 강광을 상기 제2의 산화규소층에 조사하는 것에 의해 행하는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  20. 제20항에 있어서, 상기 산화물 기체는 순도 99.9％이상의 건조화 산소로 이루어지는 것을 특징으로 하는 박막형 반도체장치의 제작방법.
  21. 산화규소막을 갖는 반도체장치로서, 상기 산화규소막의 표면이 질화되어 있는 것을 특징으로 하는 반도체장치.
  22. 절연게이트형 전계효과 반도체장치로서, 그 표면이 질화된 산화규소막에 의해 게이트 절연막이 구성되어 있는 것을 특징으로 하는 반도체장치.
  23. 산화규소막을 갖는 반도체장치의 제작방법으로서, 산화규소막으로 이루어진 절연막 표면에 질소 이온을 주입하는 것에 의해 상기 산화규소막 표면을 산화질화규소로 하는 것을 특징으로 하는 반도체장치의 제작방법.
  24. 절연게이트형 전계효과 반도체장치의 제작방법으로서, 게이트 절연막으로서 산화규소막을 형성하는 공정과, 상기 산화규소막 표면에 질소이온을 주입하는 공정을 갖는 것을 특징으로 하는 반도체장치의 제작방법.
  25. 제24항에 있어서, 질소이온 주입 다음에 적외광의 조사에 의한 어닐을 행하는 것을 특징으로 하는 반도체장치의 제작방법.
KR1019930016789A 1992-08-27 1993-08-27 반도체장치 제작방법 KR0131062B1 (ko)

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JP5177410A JPH0786593A (ja) 1993-06-24 1993-06-24 半導体装置およびその作製方法
JP93-177410 1993-06-24
JP93-191934 1993-07-06
JP05191934A JP3122699B2 (ja) 1992-08-27 1993-07-06 薄膜状半導体装置の作製方法。

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CN1088712A (zh) 1994-06-29
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CN1560691B (zh) 2010-05-26
CN1248069A (zh) 2000-03-22
KR0131062B1 (ko) 1998-04-14
CN1248037A (zh) 2000-03-22
US7416907B2 (en) 2008-08-26
US6168980B1 (en) 2001-01-02
US20050003568A1 (en) 2005-01-06
CN100465742C (zh) 2009-03-04
CN1637565A (zh) 2005-07-13
CN1549316A (zh) 2004-11-24
CN1560691A (zh) 2005-01-05
CN100483651C (zh) 2009-04-29
US20050110091A1 (en) 2005-05-26

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