JP5577075B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5577075B2 JP5577075B2 JP2009258516A JP2009258516A JP5577075B2 JP 5577075 B2 JP5577075 B2 JP 5577075B2 JP 2009258516 A JP2009258516 A JP 2009258516A JP 2009258516 A JP2009258516 A JP 2009258516A JP 5577075 B2 JP5577075 B2 JP 5577075B2
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- electrode
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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Description
図1(A)に駆動回路に用いる第1の薄膜トランジスタ480と、画素部に用いる第2の薄膜トランジスタ170とを同一基板上に設ける例を示す。なお、図1(A)は表示装置の断面図の一例である。
実施の形態1では駆動回路の薄膜トランジスタとして一つの薄膜トランジスタを説明したが、ここでは、2つのnチャネル型の薄膜トランジスタを用いて駆動回路のインバータ回路を構成する例を基に以下に説明する。図2(A)に示す薄膜トランジスタは、実施の形態1の図1(A)に示した薄膜トランジスタ430と同一であるため、同じ部分には同じ符号を用いて説明する。
本実施の形態では、表示装置について、ブロック図等を参照して説明する。
本実施の形態では、実施の形態1に示した第2の薄膜トランジスタ170を含む表示装置の作製工程について、図9乃至図16を用いて説明する。
本実施の形態では、半導体装置として電子ペーパの例を示す。
本実施の形態では、半導体装置として発光表示装置の例を示す。表示装置の有する表示素子としては、ここではエレクトロルミネッセンスを利用する発光素子を用いて示す。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、一般的に、前者は有機EL素子、後者は無機EL素子と呼ばれている。
本実施の形態では、半導体装置の一形態に相当する液晶表示パネルの上面及び断面について、図21(A1)、図21(A2)、図21(B)を用いて説明する。図21(A1)、図21(A2)は、第1の基板4001上に形成された実施の形態1で示したIn−Ga−Zn−O系非単結晶膜を半導体層として含む薄膜トランジスタ4010、4011、及び液晶素子4013を、第2の基板4006との間にシール材4005によって封止した、パネルの上面図であり、図21(B)は、図21(A1)、図21(A2)のM−Nにおける断面図に相当する。
開示した発明に係る半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
101 ゲート電極
102 ゲート絶縁層
103 酸化物半導体層
105a ソース電極層
105b ドレイン電極層
106a ソース領域
106b ドレイン領域
107 保護絶縁層
108 容量配線
110 画素電極
112 走査線駆動回路
120 接続電極
121 端子
122 端子
125 コンタクトホール
126 コンタクトホール
127 コンタクトホール
128 透明導電膜
129 透明導電膜
141a n+層
141b n+層
146a ソース領域
146b ドレイン領域
142 n+層
143 n+層
144 n+層
145 n+層
150 端子
151 端子
152 ゲート絶縁層
153 接続電極
154 保護絶縁膜
155 透明導電膜
156 電極
170 薄膜トランジスタ
300 基板
301 画素部
302 走査線駆動回路
303 信号線駆動回路
310 基板
311 画素部
312 走査線駆動回路
313 走査線駆動回路
314 信号線駆動回路
320 基板
322 信号線入力端子
323 走査線
324 信号線
327 画素部
328 画素
329 画素TFT
330 保持容量部
331 画素電極
332 容量線
333 コモン端子
334 保護回路
335 保護回路
336 保護回路
337 容量バス線
351 フリップフロップ回路
352 制御信号線
353 制御信号線
354 制御信号線
355 制御信号線
356 制御信号線
357 リセット線
361 論理回路部
362 スイッチ部
363 TFT
364 TFT
365 TFT
366 TFT
367 TFT
368 TFT
369 TFT
370 TFT
371 TFT
372 TFT
373 EDMOS回路
381 電源線
382 リセット線
383 制御信号線
384 電源線
385 半導体層
386 配線層
387 配線層
388 配線層
389 コンタクトホール
390 制御信号線
400 基板
401 ゲート電極
402 ゲート電極
403 ゲート絶縁層
404 コンタクトホール
405 酸化物半導体層
406a n+層
406b n+層
408a n+層
408b n+層
407 酸化物半導体層
409 配線
410 配線
411 配線
412 ゲート絶縁層
420 n+層
423 n+層
425 n+層
430 薄膜トランジスタ
431 薄膜トランジスタ
432 薄膜トランジスタ
433 薄膜トランジスタ
470 ゲート電極
471 電極
471 ゲート電極
472 電極
473 絶縁層
474 電極
475 発光層
476 電極
480 薄膜トランジスタ
581 薄膜トランジスタ
585 絶縁層
587 電極層
588 電極層
589 球形粒子
590a 黒色領域
590b 白色領域
594 キャビティ
595 充填材
1000 携帯電話機
1001 筐体
1002 表示部
1003 操作ボタン
1004 外部接続ポート
1005 スピーカ
1006 マイク
2600 TFT基板
2601 対向基板
2602 シール材
2603 画素部
2604 表示素子
2605 着色層
2606 偏光板
2607 偏光板
2608 配線回路部
2609 フレキシブル配線基板
2610 冷陰極管
2611 反射板
2612 回路基板
2613 拡散板
4001 基板
4002 画素部
4003 信号線駆動回路
4004 走査線駆動回路
4005 シール材
4006 基板
4008 液晶層
4010 薄膜トランジスタ
4011 薄膜トランジスタ
4013 液晶素子
4015 接続端子電極
4016 端子電極
4018 FPC
4019 異方性導電膜
4020 絶縁層
4020 絶縁層(絶縁層
4021 絶縁層
4030 画素電極層
4031 対向電極層
4032 絶縁層
4501 基板
4502 画素部
4503a 信号線駆動回路
4504a 走査線駆動回路
4518a FPC
4505 シール材
4506 基板
4507 充填材
4509 薄膜トランジスタ
4510 薄膜トランジスタ
4511 発光素子
4512 電界発光層
4513 電極層
4515 接続端子電極
4516 端子電極
4517 電極層
4519 異方性導電膜
4520 隔壁
6400 画素
6401 スイッチング用トランジスタ
6402 駆動用トランジスタ
6403 容量素子
6404 発光素子
6405 信号線
6406 走査線
6407 電源線
6408 共通電極
7001 TFT
7002 発光素子
7003 陰極
7004 発光層
7005 陽極
7011 駆動用TFT
7012 発光素子
7013 陰極
7014 発光層
7015 陽極
7016 遮蔽膜
7017 導電膜
7021 駆動用TFT
7022 発光素子
7023 陰極
7024 発光層
7025 陽極
7027 導電膜
9100 携帯電話機
9101 筐体
9102 筐体
9103 連結部
9104 表示部
9106 操作キー
9200 携帯情報端末機器
9201 筐体
9202 表示部
9203 筐体
9205 キーボード
9207 連結部
9300 コンピュータ
9301 筐体
9302 筐体
9303 表示部
9304 キーボード
9400 通信装置
9401 筐体
9402 操作ボタン
9403 外部入力端子
9404 マイク
9405 スピーカ
9406 発光部
9410 表示装置
9411 筐体
9412 表示部
9413 操作ボタン
9500 デジタルビデオカメラ
9501 筐体
9503 表示部
9600 テレビジョン装置
9601 筐体
9603 表示部
9605 スタンド
9607 表示部
9609 操作キー
9610 リモコン操作機
9700 デジタルフォトフレーム
9701 筐体
9703 表示部
Claims (6)
- 第1の導電層を有し、
前記第1の導電層の上方に第1の絶縁層を有し、
前記第1の絶縁層の上方にn型の導電型を有する第1及び第2の層を有し、
前記第1の層の上方に第1の電極を有し、
前記第2の層の上方に第2の電極を有し、
前記第1の電極の上方にn型の導電型を有する第3の層を有し、
前記第2の電極の上方にn型の導電型を有する第4の層を有し、
前記第3の層と前記第4の層の間の前記第1の絶縁層の上方、前記第3の層の上方、及び前記第4の層の上方に第1の酸化物半導体層を有し、
前記第1の酸化物半導体層の上方に第2の絶縁層を有し、
前記第2の絶縁層の上方に第2の導電層を有し、
前記第1の導電層は、前記第1の酸化物半導体層と重なる領域を有し、
前記第2の導電層は、前記第1の酸化物半導体層と重なる領域を有することを特徴とする半導体装置。 - 第1のトランジスタと第2のトランジスタとを有し、
前記第1のトランジスタは、
第1の導電層を有し、
前記第1の導電層の上方に第1の絶縁層を有し、
前記第1の絶縁層の上方にn型の導電型を有する第1及び第2の層を有し、
前記第1の層の上方に第1の電極を有し、
前記第2の層の上方に第2の電極を有し、
前記第1の電極の上方にn型の導電型を有する第3の層を有し、
前記第2の電極の上方にn型の導電型を有する第4の層を有し、
前記第3の層と前記第4の層の間の前記第1の絶縁層の上方、前記第3の層の上方、及び前記第4の層の上方に第1の酸化物半導体層を有し、
前記第1の酸化物半導体層の上方に第2の絶縁層を有し、
前記第2の絶縁層の上方に第2の導電層を有し、
前記第1の導電層は、前記第1のトランジスタの第1のゲート電極として機能する領域を有し、
前記第2の導電層は、前記第1のトランジスタの第2のゲート電極として機能する領域を有し、
前記第2のトランジスタは、
第3の導電層を有し、
前記第3の導電層の上方に前記第1の絶縁層を有し、
前記第1の絶縁層の上方にn型の導電型を有する第5及び第6の層を有し、
前記第5の層の上方に第3の電極を有し、
前記第6の層の上方に第4の電極を有し、
前記第3の電極の上方にn型の導電型を有する第7の層を有し、
前記第4の電極の上方にn型の導電型を有する第8の層を有し、
前記第7の層と前記第8の層の間の前記第1の絶縁層の上方、前記第7の層の上方、及び前記第8の層の上方に第2の酸化物半導体層を有し、
前記第3の導電層は、前記第2のトランジスタのゲート電極として機能する領域を有し、
前記第1のトランジスタは駆動回路部に設けられ、
前記第2のトランジスタは画素部に設けられていることを特徴とする半導体装置。 - 第1のトランジスタと第2のトランジスタとを有し、
前記第1のトランジスタは、
第1の導電層を有し、
前記第1の導電層の上方に第1の絶縁層を有し、
前記第1の絶縁層の上方にn型の導電型を有する第1及び第2の層を有し、
前記第1の層の上方に第1の電極を有し、
前記第2の層の上方に第2の電極を有し、
前記第1の電極の上方にn型の導電型を有する第3の層を有し、
前記第2の電極の上方にn型の導電型を有する第4の層を有し、
前記第3の層と前記第4の層の間の前記第1の絶縁層の上方、前記第3の層の上方、及び前記第4の層の上方に第1の酸化物半導体層を有し、
前記第1の酸化物半導体層の上方に第2の絶縁層を有し、
前記第2の絶縁層の上方に第2の導電層を有し、
前記第1の導電層は、前記第1のトランジスタの第1のゲート電極として機能する領域を有し、
前記第2の導電層は、前記第1のトランジスタの第2のゲート電極として機能する領域を有し、
前記第2のトランジスタは、
第3の導電層を有し、
前記第3の導電層の上方に前記第1の絶縁層を有し、
前記第1の絶縁層の上方にn型の導電型を有する第5及び第6の層を有し、
前記第5の層の上方に第3の電極を有し、
前記第6の層の上方に第4の電極を有し、
前記第3の電極の上方にn型の導電型を有する第7の層を有し、
前記第4の電極の上方にn型の導電型を有する第8の層を有し、
前記第7の層と前記第8の層の間の前記第1の絶縁層の上方、前記第7の層の上方、及び前記第8の層の上方に第2の酸化物半導体層を有し、
前記第3の導電層は、前記第2のトランジスタのゲート電極として機能する領域を有し、
前記第1のトランジスタまたは前記第2のトランジスタの一方は、エンハンスメント型トランジスタとして機能させることができ、
前記第1のトランジスタまたは前記第2のトランジスタの他方は、デプレッション型トランジスタとして機能させることができることを特徴とする半導体装置。 - 請求項2において、
前記第2のトランジスタと電気的に接続された画素電極を有し、
前記第2の導電層は、透光性を有する導電材料を有し、
前記第2の導電層と前記画素電極とは、同一の導電層を加工する工程を経て形成されたものであることを特徴とする半導体装置。 - 請求項1乃至4のいずれか一において、
前記第1の層は、酸化物半導体を有し、且つ前記第1の酸化物半導体層よりもキャリア濃度の高い領域を有し、
前記第2の層は、酸化物半導体を有し、且つ前記第1の酸化物半導体層よりもキャリア濃度の高い領域を有し、
前記第3の層は、酸化物半導体を有し、且つ前記第1の酸化物半導体層よりもキャリア濃度の高い領域を有し、
前記第4の層は、酸化物半導体を有し、且つ前記第1の酸化物半導体層よりもキャリア濃度の高い領域を有することを特徴とする半導体装置。 - 請求項1乃至5のいずれか一において、
前記第3の層と前記第1の酸化物半導体層とは端部が一致しており、
前記第4の層と前記第1の酸化物半導体層とは端部が一致していることを特徴とする半導体装置。
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