1280664 13523twfl .doc/006 95-10-19 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種畫素結構(pixel structure)及其製 造方法，且特別是有關於一種具有雙閘極薄膜電晶體 (double gate thin film transistor)與畫素結構及其製造方法。 【先前技術】 由於顯示器的需求與日遽增，因此業界全力投入相關 顯不器的發展。其中，又以陰極射線管（Cathode Ray Tube) 因具有優異的顯示品質與技術成熟性，因此長年獨佔顯示 器市場。然而，近來由於綠色環保槪念的興起對於其能源 消耗較大與產生輻射量較大的特性，加上產品扁平化空間 有限，因此無法滿足市場對於輕、薄、短、小、美以及低 消耗功率的市場趨勢。因此，具有高畫質、空間利用效率 佳、低消耗功率、無輻射等優越特性之薄膜電晶體液晶顯 示器(Thin Film Transistor Liquid Crystal Display， TFT-LCD)已逐漸成爲市場之主流。 以薄膜電晶體液晶顯示模組（TFT-LCD module)而 言，其主要係由一液晶顯示面板（liquid crystal display Panel )及一背光模組（back light module )所構成。其中， 液晶顯示面板通常是由一薄膜電晶體陣列基板（thin film transistor substrate )、一 彩色爐光基板（color filter substrate )與配置於此兩基板間之一液晶層所構成，而背光 模組用以提供此液晶顯示面板所需之面光源，以使液晶顯 示模組達到顯示的效果。此外，薄膜電晶體陣列基板通常 包括多個資料配線(data line)、多個掃瞄配線（scan line)、多 1280664 13 523twfl .doc/006 95-10-19 個薄膜電晶體與多個畫素電極(pixel electrode)，其中這些 資料配線與這些掃瞄配線係配置於一基板上，而這些資料 配線與這些掃瞄配線係在基板上劃分出多個畫素區域。另 外，薄膜電晶體係配置於畫素區域(pixel region)上，而薄膜 電晶體係藉由資料配線與掃瞄配線驅動，且薄膜電晶體係 與畫素電極電性連接。 薄膜電晶體係透過掃瞄線配以及資料配線的控制而 驅動其呈現『開』或『關』的狀態，以決定與此薄膜電晶 體電性連接的畫素電極是否充入電荷。然而，由於傳統薄 膜電晶體爲單一閘極結構的設計，因此透過此薄膜電晶體 而充入畫素電極的電荷流量將有一定的極限。 【發明內容】 有鑒於此，本發明的目的就是在提供一種雙閘極薄膜 電晶體，其具有較大的輸出電流。 此外，本發明的再一目的是提供一種畫素結構，其具 有雙閘極薄膜電晶體，以提高使用此種畫素結構之顯示器 的顯示品質。 另外，本發明的又一目的是提供一種畫素結構的製造 方法，用以製造出具有雙閘極薄膜電晶體之畫素結構。 本發明提出一種雙閘極薄膜電晶體，其係包括一基 板、一第一聞極(gate)、一第一介電層（dielectric layer)、一 半導體層、一源極（source)、一汲極（drain)、一第二介電層 與一第二閘極。第一閘極係配置於基板上，而第一介電層 係配置於基板上並覆蓋住第一閘極。此外，半導體層係至 少配置於第一閘極上方之第一介電層上，而源極與汲極係 1280664 13523twfl.doc/006 95-10-19 配置於半導體層上。另外，第二介電層配置於第一介電層 上並覆蓋源極以及汲極。再者，第二閘極係至少配置於半 導體層上方之第二介電層上，且第二閘極係與第一閘極電 性連接。 本發明提出一種畫素結構，其係包括一基板、一掃瞄 配線、一貪料配線、一雙_極薄膜電晶體與一畫素電極。 掃瞄配線與資料配線係配置於基板上。此外，雙閘極薄膜 電晶體係配置於基板上。另外，畫素電極係配置於基板上， 而畫素電極係與雙閘極薄膜電晶體電性連接。 承上所述，雙閘極薄膜電晶體包括一第一閘極、一第 一介電層、一半導體層、一源極、一汲極、一第二介電層 與一第二閘極，其中第一閘極係與掃瞄配線電性連接。此 外，第一介電層係至少覆蓋第一閘極，而半導體層係至少 配置於第一閘極上方之第一介電層上。另外，源極與汲極 係配置於半導體層上，且源極係與資料配線電性連接，其 中畫素電極係與汲極電性連接。再者，第二介電層係配置 於第一介電層上並覆蓋源極以及汲極，而第二閘極係至少 配置於半導體層上方之第二介電層上，其中第二閘極係與 第一閘極電性連接，且畫素電極係與第二閘極電性隔離。 本發明提出一種畫素結構的製造方法，其係包括幾個 步驟。首先，提供一基板，其具有一主動元件區。然後， 在基板上形成一掃瞄配線以及與掃瞄配線連接之一第一閘 極。之後，在基板上形成一第一介電層，以覆蓋掃瞄配線 與第一閘極。隨後，至少在第一閘極上方之第一介電層上 形成一半導體層。接著，在基板上方形成一資料配線，並 1280664 13523twfl.doc/006 95-10-19 且同時於半導體層上形成一源極與一汲極，而源極係與資 料配線電性連接。再來，在基板上形成一第二介電層，以 覆蓋資料配線、源極以及汲極。在第二介電層上形成一第 二閘極與一畫素電極，其中第二閘極係與第一閘極電性連 接，而畫素電極係與汲極電性連接。 基於上述，本發明之雙閘極薄膜電晶體將第二閘極配 置於半導體層上方之第二介電層上，且第二閘極係電性連 接至第一閘極，透過此種雙重閘極的設計可以誘導（induce) 源極與汲極之間的通道產生較大的電流量。此外，在不額 外增加的製程步驟下，本發明之畫素結構的製造方法能夠 製造出具有雙閘極薄膜電晶體之畫素結構，其結果不僅無 須增加生產成本，更可以提高使用此畫素結構之液晶顯示 器的顯示品質。 爲讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式’作詳細 說明如下。 【實施方式】 本發明將一第二閘極配置於半導體層上方之第一介電 層上，並將第二閘極電性連接至第一閘極，以形成雙閘極· 薄膜電晶體，透過此種雙重閘極的設計可以誘導源極與汲 極之間的通道產生較大的電流量。此外’此種雙閘極薄膜 電晶體可以應用至畫素結構中，而使用此種畫素結構之顯 示器將具有較佳的顯示品質。以下將舉實施例分別說明本1 發明之雙閘極薄膜電晶體與畫素結構及其製造方法° $ 而，以下所述之實施例係用以說明本發明’並非用以限定 1280664 13 523twfl .doc/006 95-10-19 本發明之範圍，因此熟習此技藝者可依照本發明之精神而 針對以下所述之實施例進行適當修改，惟其仍應屬於本發 明所揭露之範圍。 【第一實施例】 圖1A繪示依照本發明第一較佳實施例之畫素結構的 俯視示意圖。圖1B係繪示沿圖1A之I - I ’線的剖面結構 示意圖。圖1C係繪示沿圖1A之Π - Π ’線的剖面結構示意 圖。請同時參照圖1A、圖1B與圖1C，畫素結構100例如 應用於一液晶顯示器或其他顯示器，而配置在一基板Π0 上的畫素結構1〇〇包括一掃瞄配線120、一資料配線、 一雙閘極薄膜電晶體140與一畫素電極154。掃瞄配線120 與資料配線130係配置於基板110上，如圖1A所示。此外， 雙閘極薄膜電晶體140係配置於基板110上，而雙閘極薄 膜電晶體140係與資料配線130與掃瞄配線120電性連接。 另外，畫素電極154係與雙閘極薄膜電晶體140電性連接。 請繼續參照圖1B，雙閘極薄膜電晶體140包括一第一 閘極122、一第一介電層142、一半導體層144、一源極132、 一汲極134、一第二介電層146與一第二閘極1S2，其中第 一閘極122係與掃瞄配線120電性連接。此外，第一介電 層142係配置於基板110上，並覆蓋第一閘極122。另外， 半導體層144係至少配置於第一閘極122上方之第一介電 層142上。再者，源極132與汲極134係配置於半導體層 144上，而源極132係與資料配線130電性連接，且汲極 134係與畫素電極154電性連接。 第二介電層146係配置於第一介電層142上，並覆蓋 1280664 95-10-19 13523twfl.doc/006 源極132與汲極I34。此外，第二閘極152係至少配置於半 導體層144上方之第二介電層M6上，其中第二閘極152 係與第一閘極122電性連接（如圖1C所示），且畫素電極 154係與第二閘極152電性隔離。値得一提的是，雙閘極薄 膜電晶體140例如更包括一接觸窗（contact hoie)l56與接角蜀 窗148，其中接觸窗1%係位於第二介電層M2內，且畫素 電極154係經由接觸窗156與汲極134電性連接。而接觸 窗M8係位於第一介電層142與第二介電層146內，且第 二閘極152係經由接觸窗148電性連接至第一閘極122,如 圖1C所示◦另外，上述之半導體層144例如包括一通道層 (channel layer)144b 與一歐姆接觸層（ohmic contact layer)144a，而歐姆接觸層144a係分別配置於通道層144b 以及源極132與汲極134之間，如圖1B所示。 承上所述，第二閘極152例如是一透明導體層或一金 屬層，而透明導體層之材質例如包括銦錫氧化物（Indium1280664 13523twfl .doc/006 95-10-19 IX. Description of the Invention: [Technical Field] The present invention relates to a pixel structure and a method of fabricating the same, and in particular to a double gate A double gate thin film transistor and a pixel structure and a method of manufacturing the same. [Prior Art] As the demand for displays has increased, the industry is fully committed to the development of related devices. Among them, the cathode ray tube (Cathode Ray Tube) has a superior display quality and technical maturity, so it has dominated the display market for many years. However, the recent rise in green environmental commemoration is not able to meet the market's characteristics of lightness, thinness, shortness, smallness, beauty, and low consumption due to its large energy consumption and large amount of radiation, and limited product flattening space. Market trends in power. Therefore, Thin Film Transistor Liquid Crystal Display (TFT-LCD), which has high image quality, excellent space utilization efficiency, low power consumption, and no radiation, has gradually become the mainstream in the market. The TFT-LCD module is mainly composed of a liquid crystal display panel and a backlight module. The liquid crystal display panel is generally composed of a thin film transistor substrate, a color filter substrate, and a liquid crystal layer disposed between the two substrates, and the backlight module is used for the backlight module. The surface light source required for the liquid crystal display panel is provided to achieve the display effect of the liquid crystal display module. In addition, the thin film transistor array substrate usually includes a plurality of data lines, a plurality of scan lines, a plurality of 1280664 13 523 tw ft. doc / 006 95-10-19 thin film transistors and a plurality of pixels A pixel electrode, wherein the data wiring and the scan wiring are disposed on a substrate, and the data wiring and the scanning wiring are divided into a plurality of pixel regions on the substrate. In addition, the thin film electro-crystal system is disposed on the pixel region, and the thin film electro-crystal system is driven by the data wiring and the scan wiring, and the thin film electro-crystal system is electrically connected to the pixel electrode. The thin film electro-crystal system drives the "on" or "off" state through the control of the scan line and the data wiring to determine whether the pixel electrode electrically connected to the thin film transistor is charged. However, since the conventional thin film transistor is designed as a single gate structure, there is a limit to the charge flow rate of the pixel electrode through the thin film transistor. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a dual gate thin film transistor having a large output current. Further, it is still another object of the present invention to provide a pixel structure having a double gate thin film transistor to improve the display quality of a display using such a pixel structure. Further, it is still another object of the present invention to provide a method of fabricating a pixel structure for fabricating a pixel structure having a double gate thin film transistor. The present invention provides a dual gate thin film transistor comprising a substrate, a first gate, a first dielectric layer, a semiconductor layer, a source, and a drain. A drain, a second dielectric layer and a second gate. The first gate is disposed on the substrate, and the first dielectric layer is disposed on the substrate and covers the first gate. In addition, the semiconductor layer is disposed at least on the first dielectric layer above the first gate, and the source and drain electrodes are arranged on the semiconductor layer 1280664 13523 twfl.doc/006 95-10-19. In addition, the second dielectric layer is disposed on the first dielectric layer and covers the source and the drain. Furthermore, the second gate is disposed on at least the second dielectric layer above the semiconductor layer, and the second gate is electrically connected to the first gate. The present invention provides a pixel structure comprising a substrate, a scan wiring, a solder wiring, a double-electrode transistor and a pixel electrode. The scan wiring and the data wiring system are disposed on the substrate. In addition, a dual gate thin film transistor system is disposed on the substrate. Further, the pixel electrode is disposed on the substrate, and the pixel electrode is electrically connected to the double gate thin film transistor. As described above, the dual gate thin film transistor includes a first gate, a first dielectric layer, a semiconductor layer, a source, a drain, a second dielectric layer and a second gate. The first gate is electrically connected to the scan wiring. In addition, the first dielectric layer covers at least the first gate, and the semiconductor layer is disposed on at least the first dielectric layer above the first gate. Further, the source and the drain are disposed on the semiconductor layer, and the source is electrically connected to the data wiring, and the pixel electrode is electrically connected to the drain. Furthermore, the second dielectric layer is disposed on the first dielectric layer and covers the source and the drain, and the second gate is disposed on at least the second dielectric layer above the semiconductor layer, wherein the second gate The first gate is electrically connected, and the pixel electrode is electrically isolated from the second gate. The present invention proposes a method of fabricating a pixel structure comprising several steps. First, a substrate is provided having an active element region. Then, a scan wiring and a first gate connected to the scan wiring are formed on the substrate. Thereafter, a first dielectric layer is formed on the substrate to cover the scan wiring and the first gate. Subsequently, a semiconductor layer is formed on at least the first dielectric layer above the first gate. Next, a data wiring is formed over the substrate, and a source and a drain are formed on the semiconductor layer at the same time, and the source is electrically connected to the data wiring. Further, a second dielectric layer is formed on the substrate to cover the data wiring, the source, and the drain. A second gate and a pixel electrode are formed on the second dielectric layer, wherein the second gate is electrically connected to the first gate, and the pixel electrode is electrically connected to the drain. Based on the above, the dual gate thin film transistor of the present invention has a second gate disposed on the second dielectric layer above the semiconductor layer, and the second gate is electrically connected to the first gate, through the double gate The pole design can induce a large amount of current in the channel between the source and the drain. In addition, the manufacturing method of the pixel structure of the present invention can produce a pixel structure having a double gate thin film transistor without additional processing steps, and the result is not only increased production cost but also improved use of the pixel. The display quality of the liquid crystal display of the structure. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] The present invention has a second gate disposed on a first dielectric layer above the semiconductor layer and a second gate electrically connected to the first gate to form a double gate transistor film. Through this double gate design, a large amount of current can be induced in the channel between the source and the drain. In addition, such a double gate thin film transistor can be applied to a pixel structure, and a display using such a pixel structure will have better display quality. Hereinafter, the double gate thin film transistor and pixel structure of the present invention and the method of manufacturing the same will be described with reference to the embodiments, and the following embodiments are used to illustrate that the present invention is not intended to limit 1280664 13 523 twfl. Doc/006 95-10-19 The scope of the present invention is to be appropriately modified by those skilled in the art in light of the spirit of the present invention, which is still within the scope of the present invention. [First Embodiment] Fig. 1A is a schematic plan view showing a pixel structure according to a first preferred embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along line I - I of Fig. 1A. Fig. 1C is a schematic cross-sectional view taken along line Π - ’ ' of Fig. 1A. Referring to FIG. 1A, FIG. 1B and FIG. 1C, the pixel structure 100 is applied to, for example, a liquid crystal display or other display, and the pixel structure 1 disposed on a substrate 〇〇0 includes a scan wiring 120 and a data wiring. A pair of gate thin film transistors 140 and a pixel electrode 154. The scan wiring 120 and the data wiring 130 are disposed on the substrate 110 as shown in FIG. 1A. In addition, the double gate thin film transistor 140 is disposed on the substrate 110, and the double gate thin film transistor 140 is electrically connected to the data wiring 130 and the scan wiring 120. In addition, the pixel electrode 154 is electrically connected to the double gate thin film transistor 140. Referring to FIG. 1B , the dual gate thin film transistor 140 includes a first gate 122 , a first dielectric layer 142 , a semiconductor layer 144 , a source 132 , a drain 134 , and a second dielectric layer . 146 and a second gate 1S2, wherein the first gate 122 is electrically connected to the scan wiring 120. In addition, the first dielectric layer 142 is disposed on the substrate 110 and covers the first gate 122. In addition, the semiconductor layer 144 is disposed on at least the first dielectric layer 142 above the first gate 122. Further, the source 132 and the drain 134 are disposed on the semiconductor layer 144, the source 132 is electrically connected to the data line 130, and the drain 134 is electrically connected to the pixel electrode 154. The second dielectric layer 146 is disposed on the first dielectric layer 142 and covers the source electrode 132 and the drain electrode I34 of 1280664 95-10-19 13523 twfl.doc/006. In addition, the second gate 152 is disposed at least on the second dielectric layer M6 above the semiconductor layer 144, wherein the second gate 152 is electrically connected to the first gate 122 (as shown in FIG. 1C), and is drawn. The element electrode 154 is electrically isolated from the second gate 152. It is noted that the dual gate thin film transistor 140 further includes a contact hoie 156 and a gusset 148, wherein the contact window 1% is located in the second dielectric layer M2, and the pixel The electrode 154 is electrically connected to the drain 134 via the contact window 156. The contact window M8 is located in the first dielectric layer 142 and the second dielectric layer 146, and the second gate 152 is electrically connected to the first gate 122 via the contact window 148, as shown in FIG. 1C. The semiconductor layer 144 includes a channel layer 144b and an ohmic contact layer 144a, and the ohmic contact layer 144a is disposed between the channel layer 144b and the source 132 and the drain 134, respectively. As shown in Figure 1B. As described above, the second gate 152 is, for example, a transparent conductor layer or a metal layer, and the material of the transparent conductor layer includes, for example, indium tin oxide (Indium).
Tin Oxide，IT0)或銦鋅氧化物(Indium Zinc Oxide，IZO)。此 外，畫素電極154之材質例如包括銦錫氧化物或銦鋅氧化 物。此外，畫素電極154並不限定藉由接觸窗156與汲極 134電性連接，而畫素電極154亦可以配置在第一介電層 142上，而直接與汲極134之表面接觸，以使兩者電性連接 (未繪示出）。當本發明之畫素結構1〇〇應用於液晶顯、 時，由於雙閘極薄膜電晶體140之雙閘極的設計$以 通道層144b產生較大的電流通道，因此此種雙__薄，電 晶體140能夠提供較大的電流，以改善液晶顯示器 品質。 10 1280664 13523twfl.doc/〇〇6 95-10-19 此外，相較於習知技術所使用之單閘極薄膜電晶體的 尺寸，由於本發明之雙閘極薄膜電晶體14〇能夠提供較大 的電流，因此其尺寸能夠進一步縮小，其結果不僅能夠達 到液晶顯示器所需之充電特性，更可降低訊號失真的程 度。値得一提的是，雙閘極薄膜電晶體14〇並不限定使用 在液晶顯示器的畫素結構100中，而雙閘極薄膜電晶體140 更可使用於其他電子裝置內。再者，對於畫素結構10()之 製造方法，其詳述如後。 阳同時參照圖1A、圖1B與圖1C，畫素結構100的製 ^方法例如包括幾個步驟。首先，提供一基板ιι〇，並在基 一上形成一掃瞄配線120以及與掃瞄配線120連接之 14^，閘^122。之後，在基板U〇上形成一第一介電層 w〜以覆盍知目田配線120與第〜閘極122。隨後，至少在 上方之第—介電層142上形成—半導體層 半導體層144例如包括〜通道層144b與歐姆接觸 :许& ’其中歐姆接觸層144&係形成於通道層144b以及 薈二西1//與源極132之間。接著，在基板UG上方形成一 3〇，並且同時於半導體層144上形成一源極132 汲極134 ’且源極132係與資料配線13〇電性連接。 來，在基板U0上形成一第二介電層^6,以覆蓋資料配 線130、源極m以及汲極134。 封第一介電層146與第一介電層142進行圖案化製 成接觸窗開口 148、156，其分別暴露出第一閘極 邰f表面與汲極134之部分表面。然後，在基板ιι〇 成第一閘極152與一畫素電極1S4，其中第二閘極 1280664 95-10-19 13523twfl.doc/006 152係至少覆蓋於半導體層M4上方之第二介電層146。而 第二閘極152之導電材質係塡入接觸窗148開口內，因而 使第二閘極152與第一閘極122電性連接，如圖1C所示。 同樣的’畫素電極154之導電材質亦塡入接觸窗開口 156 內，因而使畫素電極154與汲極134電性連接。在一較佳 實施例中，形成第二閘極I52以及畫素電極W4之方法例 如是先於第二介電層M6上形成一透明導電層（未繪示 出），再圖案化此透明導電層以形成。 由於第二閘極152與畫素電極154係同時形成，且接 觸窗156與接觸窗148亦同時形成，因此在不增加習知技 術之製程步驟的情況下，本發明之畫素結構100之製造方 法能夠形成雙閘極薄膜電晶體140。値得注意的是，本發明 並不限定第一閘極152與畫素電極15 4必須同時形成，且 亦不限定第二閘極152與畫素電極154需具有相同之材 質。在另一實施例中，畫素電極154可以形成在第一介電 層146上，且之後所形成之汲極134會覆蓋部分的畫素電 極154，以使兩者電性連接。 【第二實施例】 圖2A繪示依照本發明第二較佳實施例之畫素結構的 俯視示意圖。圖2B係繪示沿圖2A之]Π-瓜’線的剖面結構 示意圖。若是第二實施例的標號與第一實施例相同者，其 係表示在第二實施例中所指明的構件係相同於在第一實施 例中所指明的構件，在此不再贅述。 請參照圖2A與圖2B，第二實施例與第一實施例相 似，其不同之處在於：在第二實施例之畫素結構200中， 1280664 13523twfl.doc/006 95-10-19 雙閘極薄膜電晶體240之第二閘極252僅配置於對應汲極 134與源極132之間的第二介電餍146上，而第二閘極252 係藉由接觸窗248電性連接至第一閘極122 (類似圖1C所 示）。値得注意的是，由於第二閘極252僅配置於對應汲 極134與源極132之間的第二介電層上，因此可以減 少第二閘極252與源極132與汲極134之間的所產生的寄 生電容(parasitism capacitance)。 承上所述，第二實施例之製造方式與第一實施例相 似，其不同之處在於：於定義第二閘極252時，僅使第二 閘極252形成於對應汲極134與源極132之間的第二介電 層146上。同樣的，本實施例並不限定畫素電極154與第 二閘極252需同時形成。 綜上所述，本發明之雙閘極薄膜電晶體與畫素結構及 其製造方法具有下列優點： 一、 本發明之雙閘極薄膜電晶體因具有雙重閘極的設 計，透過此種雙重閘極的設計可以誘導源極與汲極之間的 通道產生較大的電流量。 二、 由於本發明之畫素結構採用能夠提供較大電流之 雙閘極薄膜電晶體，因此使用本發明之畫素結構之液晶顯 示器具有較佳的顯示效果。此外，由於本發明之雙閘極薄 膜電晶體能夠提供較大電流量，因此可以縮小雙閘極薄膜 電晶體之尺寸以改善顯示品質。 三、在本發明之雙聞極薄膜電晶體中，第二閘極更可僅 配置於對應源極與汲極之間上方的弟一介電層上’以降低 雙閘極薄膜電晶體之寄生電容。 1280664 13523twfl.doc/006 95-10-19 四、在不增加製程步驟的情況下，本發明之畫素結構的 製造方法能夠製造出具有雙閘極薄膜電晶體之畫素結構， 其結果不僅無須增加生產成本，更可以提高使用此畫素結 _ 構之液晶顯示器的顯示品質。 雖然本發明已以較佳實施例揭露如上，然其並非用以 ~ 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 圖1A繪示依照本發明第一較佳實施例之畫素結構的 - 俯視示意圖。 圖1B係繪不沿圖1A之I - I ’線的剖面結構示意圖。 圖1C係繪示沿圖1A之Π ，線的剖面結構示意圖。 圖2Α繪示依照本發明第二較佳實施例之畫素結構的 俯視示意圖。 圖2Β係繪示沿圖2Α之Π[_ΠΙ，線的剖面結構示意圖。 【圖式標示說明】 100、200 :畫素結構 110 :基板 120 :掃瞄配線 - 122 :第一閘極 _ 130 :資料配線 132 :源極 14 1280664 13523twfl.doc/006 134 :汲極 140、240 :雙閘極薄膜電晶體 142 :第一介電層 144 :半導體層 144a :歐姆接觸層 144b :通道層 146 :第二介電層 148、156、248 ··接觸窗 152、252.:第二閘極 154 :畫素電極 I - I，、Π - Π，、Π - Π，··咅[j面線Tin Oxide, IT0) or Indium Zinc Oxide (IZO). Further, the material of the pixel electrode 154 includes, for example, indium tin oxide or indium zinc oxide. In addition, the pixel electrode 154 is not limited to be electrically connected to the drain 134 through the contact window 156, and the pixel electrode 154 may also be disposed on the first dielectric layer 142 and directly contact the surface of the drain 134 to The two are electrically connected (not shown). When the pixel structure of the present invention is applied to liquid crystal display, since the double gate design of the double gate thin film transistor 140 generates a large current path by the channel layer 144b, the double __ thin The transistor 140 is capable of providing a large current to improve the quality of the liquid crystal display. 10 1280664 13523twfl.doc/〇〇6 95-10-19 Furthermore, the double gate thin film transistor 14 of the present invention can provide a larger size than the single gate thin film transistor used in the prior art. The current can be further reduced in size, and the result is not only the charging characteristics required for the liquid crystal display, but also the degree of signal distortion. It is noted that the dual gate thin film transistor 14 is not limited to use in the pixel structure 100 of the liquid crystal display, and the double gate thin film transistor 140 can be used in other electronic devices. Further, the manufacturing method of the pixel structure 10() will be described in detail later. Referring to Figures 1A, 1B and 1C simultaneously, the method of fabricating the pixel structure 100 includes, for example, several steps. First, a substrate ιι is provided, and a scan wiring 120 and a gate electrode 122 connected to the scan wiring 120 are formed on the substrate. Thereafter, a first dielectric layer w is formed on the substrate U to cover the mesh wiring 120 and the first gate 122. Subsequently, at least on the upper first dielectric layer 142, the semiconductor layer semiconductor layer 144 includes, for example, a channel layer 144b and an ohmic contact: wherein the ohmic contact layer 144 & is formed on the channel layer 144b and the 1 / / and the source 132. Next, a 〇 is formed over the substrate UG, and a source 132 drain 134 ′ is formed on the semiconductor layer 144 and the source 132 is electrically connected to the data wiring 13 . A second dielectric layer 6 is formed on the substrate U0 to cover the data line 130, the source m, and the drain 134. The first dielectric layer 146 and the first dielectric layer 142 are patterned to form contact openings 148, 156 that expose a portion of the surface of the first gate 邰f and the drain 134, respectively. Then, the substrate is multiplexed into a first gate 152 and a pixel electrode 1S4, wherein the second gate 1280664 95-10-19 13523 twfl.doc/006 152 covers at least the second dielectric layer above the semiconductor layer M4. 146. The conductive material of the second gate 152 is inserted into the opening of the contact window 148, thereby electrically connecting the second gate 152 and the first gate 122, as shown in FIG. 1C. The conductive material of the same 'pixel element 154' also enters the contact opening 156, thereby electrically connecting the pixel electrode 154 to the drain 134. In a preferred embodiment, the method of forming the second gate I52 and the pixel electrode W4 is, for example, forming a transparent conductive layer (not shown) on the second dielectric layer M6, and then patterning the transparent conductive layer. Layers are formed. Since the second gate 152 and the pixel electrode 154 are simultaneously formed, and the contact window 156 and the contact window 148 are simultaneously formed, the fabrication of the pixel structure 100 of the present invention is performed without increasing the manufacturing process steps of the prior art. The method enables the formation of a dual gate thin film transistor 140. It should be noted that the present invention does not limit that the first gate 152 and the pixel electrode 15 4 must be formed at the same time, and it is not limited that the second gate 152 and the pixel electrode 154 need to have the same material. In another embodiment, the pixel electrode 154 may be formed on the first dielectric layer 146, and the subsequently formed drain 134 may cover a portion of the pixel electrode 154 to electrically connect the two. [Second Embodiment] Fig. 2A is a schematic plan view showing a pixel structure according to a second preferred embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along line Π-瓜' of Fig. 2A. If the reference numerals of the second embodiment are the same as those of the first embodiment, it means that the components specified in the second embodiment are the same as those specified in the first embodiment, and will not be described again. Referring to FIG. 2A and FIG. 2B, the second embodiment is similar to the first embodiment except that in the pixel structure 200 of the second embodiment, 1280664 13523 twfl.doc/006 95-10-19 double gate The second gate 252 of the ultra-thin film transistor 240 is disposed only on the second dielectric buffer 146 between the corresponding drain 134 and the source 132, and the second gate 252 is electrically connected to the second via the contact window 248. A gate 122 (similar to that shown in Figure 1C). It should be noted that since the second gate 252 is disposed only on the second dielectric layer between the corresponding drain 134 and the source 132, the second gate 252 and the source 132 and the drain 134 can be reduced. The resulting parasitism capacitance. As described above, the manufacturing method of the second embodiment is similar to that of the first embodiment, except that when the second gate 252 is defined, only the second gate 252 is formed on the corresponding drain 134 and the source. On the second dielectric layer 146 between 132. Similarly, this embodiment does not limit the formation of the pixel electrode 154 and the second gate 252 at the same time. In summary, the dual gate thin film transistor and pixel structure of the present invention and the method for fabricating the same have the following advantages: 1. The double gate thin film transistor of the present invention has a double gate design through the double gate The pole design can induce a large amount of current in the channel between the source and the drain. 2. Since the pixel structure of the present invention employs a double gate thin film transistor capable of supplying a large current, the liquid crystal display using the pixel structure of the present invention has a better display effect. Furthermore, since the double gate thin film transistor of the present invention can provide a large current amount, the size of the double gate thin film transistor can be reduced to improve the display quality. 3. In the double-semiconductor thin film transistor of the present invention, the second gate can be disposed only on the dielectric layer above the source and the drain to reduce the parasitics of the double gate thin film transistor. capacitance. 1280664 13523twfl.doc/006 95-10-19 4. The fabrication method of the pixel structure of the present invention can produce a pixel structure having a double gate thin film transistor without increasing the number of process steps, and the result is not only unnecessary Increasing the production cost can also improve the display quality of the liquid crystal display using this pixel. Although the present invention has been described above in terms of the preferred embodiments, it is not intended to limit the invention, and it is to be understood that those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a top plan view showing a pixel structure in accordance with a first preferred embodiment of the present invention. Fig. 1B is a schematic cross-sectional view showing the line I-I' of Fig. 1A. Fig. 1C is a cross-sectional structural view taken along line 图 of Fig. 1A. 2 is a top plan view showing a pixel structure in accordance with a second preferred embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of the line along the line [图] of Fig. 2 . [Graphic indication] 100, 200: pixel structure 110: substrate 120: scan wiring - 122: first gate _ 130: data wiring 132: source 14 1280664 13523twfl.doc / 006 134: bungee 140, 240: double gate thin film transistor 142: first dielectric layer 144: semiconductor layer 144a: ohmic contact layer 144b: channel layer 146: second dielectric layer 148, 156, 248 · contact window 152, 252.: Two gates 154: pixel electrodes I - I, Π - Π, Π - Π, ··咅 [j face line