TWI250654B - Amorphous silicon thin film transistor with dual gate structures and manufacturing method thereof - Google Patents

Abstract

An amorphous silicon thin film transistor (a-Si TFT) with dual gate structures and a manufacturing method thereof are provided. The a-Si TFT comprises a substrate, a first gate, an amorphous silicon channel layer, a source, a drain, and a second gate. The first gate is formed on the substrate. The amorphous silicon channel layer is formed above the first gate. The source and the drain are formed above the amorphous silicon channel layer and correspond to the two ends of the first gate. The source and the drain are contacted with the two ends of the amorphous silicon channel layer. The second gate is formed above the source and the drain and corresponds to the first gate. The second gate is electrically connected to the first gate via a contact hole. The peripheral of the second gate overlaps part of that of the source and the drain. Moreover, the a-Si island is completely located inside the first gate.

Description

1250654

- DIAMOND NUMBER: TW2249PA IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a thin film transistor and a method of fabricating the same, and more particularly to an amorphous germanium thin film transistor having a double gate structure And Manufacturing Method 0 [Prior Art] Referring to FIG. 1, a cross-sectional view of a conventional amorphous thin film transistor (a-Si TFT) is shown. In the first figure, the amorphous slab film transistor 1 is basically an electronic component composed of a gate 5 〇, a source 1 〇, a drain 20 and an amorphous channel layer 30, and the gate 5 The germanium and amorphous germanium channel layers 30 are separated by an insulating layer 40. The source 10 and the drain 2 are not in contact with each other, but are in contact with the amorphous germanium channel layer 30 through the heavily doped N-type (N+) semiconductor layer 2, respectively. When the gate 50 is applied with a voltage, the amorphous germanium channel layer 3 感应 induces a charge near the interface of the insulating layer 40. At this time, if a voltage is applied to the electrode 2, the electrons generated by the source 10 can pass through the amorphous channel layer 3 and flow from the source 1 to the gate 20. Further, the corresponding current flows from the drain 2 向 to the source 1 〇, so that the amorphous germanium thin film transistor 1 is turned on. When the gate 50 is not applied with a voltage, the amorphous germanium channel layer 3 does not induce any charge. Even if the drain 20 is applied with a voltage, no charge flows from the source 1 向 to the gate 20, and the source 10 and the drain 20 are electrically isolated from each other, so that the amorphous film transistor 1 is turned off. Since the amorphous germanium thin film transistor 1 has a function of controlling current conduction, it is used as a liquid crystal display (LCD) or an organic light emitting diode (OLED) display pixel TW2249PA. 1250654

. Sanda number: TW2249PA (pixel) switch. However, the conventional amorphous broken film transistor 1 has a current conducting capability of less than 5, and its amorphous germanium channel layer 30 has an electron mobility of usually less than 1 (cm 2 /V-sec ). To apply amorphous germanium thin film transistor 1 to an active matrix organic light emitting diode (AMOLED) display, compared to poly silicon thin film transistor (poly silicon thin film transistor, poly -Si TFT) requires a larger operating voltage when applied to an AMOLED, and lowers the reliability of the amorphous germanium thin film transistor 1. • Therefore, how to increase the current conduction capability of the amorphous germanium thin film transistor and lower the operating voltage to increase the reliability of the amorphous germanium thin film transistor will become an urgent problem to be solved. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an amorphous germanium thin film transistor having a double gate structure and a method of fabricating the same, wherein the second gate is electrically connected to the first gate, and the second The edge of the gate overlaps the edge of the source and the drain. And the amorphous germanium channel layer is formed corresponding to the first gate, and the distribution area of the amorphous germanium channel layer is smaller than the distribution area of the first gate, the structure can effectively increase between the first gate and the second gate The current conduction capability of the amorphous germanium channel layer. In this way, the amorphous germanium thin film transistor of the present invention is applied to an active matrix organic light emitting diode display or an a-Si related circuit, and can achieve the same operation as a conventional amorphous germanium transistor without requiring a high operating voltage. Turn on the current. In this way, not only the operating voltage of the amorphous germanium thin film transistor is lowered, but the operating speed of the a-Si circuit is increased, and the reliability of the amorphous germanium thin film transistor can be increased. Further, the crystal structure of the present invention can also be applied to a pixel transistor of an active matrix liquid crystal display. According to the object of the present invention, an amorphous thin TW2249PA 7 1250654 having a double gate structure is proposed.

One number · TW2249PA • Membrane transistor, including substrate, first gate, second idle source and drain. The first explanation is more than the total, the day and night, and the first gate is 匕 / 7 7. On the substrate, the amorphous germanium channel layer is formed on the non-H first acoustic pole to correspond to the first idle pole The two ends of the second gate are connected to the first gate of the first gate, and are electrically connected to the first gate. The edges of the square (four) overlap. , non-曰 ";::: edge and source and formation, and non-sexual desire, ... 逞 layer and brother - gate corresponds to the corresponding: Cheng: non-Shi Xitong suppression layer distribution area is smaller than the first question pole distribution area . In addition, the 'amorphous (four) film transistor further includes - (iv) a stop layer, wherein the == between the amorphous track layer and the second idler, and the amorphous track layer has a smaller cloth area than the first The distribution area of the pole. According to a re-purpose of the present invention, a method of manufacturing an amorphous germanium transistor having a double gate structure is proposed. First, it is provided on the substrate. Next, an 'insulative layer' is formed on the substrate, the pole. Then, an amorphous channel layer is formed over the first insulating layer. Then, the opening and the drain are on the amorphous channel layer, and the source and the drain are in contact with the two ends of the first and second y and the (four) channel layer. Then, form the second, second, and second. Then, 'the second gate is formed on the second insulating layer, the side of the second gate is connected to the first gate and electrically connected to the first gate, the side of the second interlayer, the source of the second electrode, and the drain of the drain The edges partially overlap. Dream thin: =:=, Γ, Γ: species have (4) first, provide the substrate, and form the first gate pole, after t become the first - insulating layer on the substrate, and cover the first between the stop and the amorphous The stone layer is on the first insulating layer. Then 'formed a dream in the engraving::. Above the amorphous layer of the knives, the etch stop layer corresponds to the first gate.彡成源极 and recorded (4) above the crystal material, the source and _ correspond to the 1250654

Erda number: TW2249PA The two ends of the gate, the etch stop layer is located between the source and the drain. Next, the source of the source 'dipole and the portion of the contact layer exposed by the stop layer is removed to form: an amorphous channel layer, the source and the drain are correspondingly in contact with the amorphous 11 ^. Then a second insulating layer is formed to cover the source and the drain. Then: shape: first: the gate is on the second insulating layer, the second gate corresponds to the first gate, and the first is: the pole is electrically connected, and the edge of the second secret edge is partially overlapped . The above-mentioned objects, features, and advantages of the present invention will be more apparent and understood from the following description. 2F mesh, which is a process sectional view of an amorphous germanium thin film transistor having a double gate structure according to Embodiment 1 of the present invention. First, a substrate 160 is provided in Fig. 2A, and a first gate 25 is formed on the substrate (10). The substrate 16G includes a glass substrate, a return substrate or an insulating substrate, and the first idler 250 includes a metal or a metal alloy. Next, as shown in Fig. 2B, a first insulating layer 24 is formed on the substrate 16A and covers the first gate 25A. Here, the first insulating layer 24g contains silicon nitride 'SiN, siiic〇n, & (10), nitride, oxynitride or oxide. . Thereafter, as shown in Fig. 2C, an amorphous stone channel layer is formed on the first, 'bar edge layer 24G. Wherein the amorphous austenite channel layer i 3Q is formed corresponding to the first gate electrode, and the distribution area of the amorphous germanium channel layer 13 小于 is smaller than the distribution area of the first gate electrode 25 。. Next, as shown in FIG. 2D, a source 11 〇 and a drain 12 are formed on the amorphous channel layer 130, and the source 11 〇 and the immersion 12 〇 correspond to the first interpole.

TW2249PA 9 1250654

The three ends of the TW2249PA are respectively in contact with both ends of the amorphous germanium channel layer 13〇. The source 110 and the drain 120 include a metal or a metal alloy. In this embodiment, a heavily doped N-type (N+) semiconductor layer 121 is further formed between the source 11 〇 and the drain 12 〇 and the amorphous germanium channel layer 130, heavily doped; ^ (N+) semiconductor Layer 121 is coated with the sidewalls of the amorphous chopped channel layer 130. Then, as shown in Fig. 2E, a second insulating layer 21 is formed to cover the source 110 and the drain 120' and a second contact hole 26 is formed at the drain 12A. Wherein, the second insulating layer 210 comprises cerium nitride, oxynitride, nitride, nitrogen oxide or oxide. Next, as shown in FIG. 2F, one of the second gate 22 and the halogen electrode 230 are electrically isolated from each other on the second insulating layer 21, and the halogen electrode 23 is transmitted through the second contact hole 260 and the chip 120. Electrical connection. The second suspension 22 〇 corresponds to the first interlayer 250 ′ and is electrically connected to the first gate through the first contact hole (not shown). The edge of the second gate 220 partially overlaps the edge of the source 11 〇 and the immersion 12 ,, and the amorphous SiO film transistor 2 〇〇 is completed here. Among them, those having ordinary knowledge in the technical field of the present embodiment can understand that the second #contact hole system can be completed in the first gate 125〇 and the second electrode 22 is completed in the second F The amorphous rock crystal film H 200 having the double interpole structure according to the embodiment includes at least a substrate 16 〇, a first gate 25 〇, a first

Two gates 2 2 0, an amorphous stone 々; sound jg 1, A non-daily 矽 channel layer 130, a source 11 〇 and a 汲 pole i2 〇〇 first gate 250 system point point The -B w amorphous track layer 13G is formed over the gate of the gate 250 and is located within the first p ^ Λττ c 弟 gate 250. The source 110 and the drain 120 are formed in the amorphous channel layer, and are formed in the amorphous channel layer 13 in a manner corresponding to the first epoch; In the first - and in the form of a sister-----------------------------------------------------------

- Sanda number: above TW2249PA, and electrically connected to the first gate 250. The outer edge of the second gate 220 overlaps the inner edge of the source 110 and the drain 120. However, those skilled in the art can understand that the technology of the embodiment is not limited thereto. For example, the materials of the first gate 250 and the second gate 220 may be the same, for example, the second gate 220 includes Metal or metal alloy. The materials of the first gate 250 and the second gate 220 may be different. For example, the second gate 220 includes indium tin oxide (ITO), indium zinc oxide (IZO). ), tin oxide ^ [cadmium tin oxide (CTO), tin oxide (Sn〇2) or zinc oxide (ZnO). Further, the halogen electrode 230 contains a metal or a metal alloy, or contains indium tin oxide, indium zinc oxide, cadmium tin oxide, tin oxide or zinc oxide. If the materials of the second gate 220 and the pixel electrode 230 are the same, the second gate 220 and the pixel electrode 230 can be simultaneously or non-simultaneously completed. If the materials of the second gate 220 and the pixel electrode 230 are different, the second gate 220 can be completed or completed later than the pixel electrode 23 0 . Since the second gate 220 is electrically connected to the first gate 250, and the edge of the second gate repair 220 overlaps the edge of the source 110 and the drain 120, when the first gate 250 and the second gate 220 are When a voltage is applied, the amorphous germanium channel layer 130 induces a charge on the lower two interfaces of the first insulating layer 240 and the second insulating layer 210, as if two currents were formed at the lower surface of the amorphous germanium channel layer 130. aisle. Moreover, the amorphous germanium channel layer 130 is in the first gate. Since the sidewall of the channel is in contact with the heavily doped N-type (N+) semiconductor layer 121, the lower interface charge is provided as a conductive path, and the source 110 and the drain 120 can be lowered. The parasitic resistance greatly increases the electron mobility of the amorphous germanium channel layer 130. Therefore, the amorphous germanium thin film transistor 200 of the present embodiment has higher current conducting capability than the conventional amorphous germanium thin film transistor 1, so the amorphous germanium thin film transistor 200 of the present embodiment is applied to the active TW2249PA 11 1250654.

- Sanda number: TW2249PA Active matrix organic light emitting diode (AMOLED) display or a-Si related circuit, which does not require high operating voltage. As a result, the operating voltage of the amorphous germanium thin film transistor can be greatly reduced, the operating speed of the a-Si circuit can be increased, and the reliability of the amorphous germanium thin film transistor can be increased. Embodiment 2 Referring to Figures 3A to 3H, there is shown a process sectional view of a thin film transistor having a double gate structure according to Embodiment 2 of the present invention. First, as shown in FIG. 3A, a substrate 360 is provided and a first gate 350 is formed on the substrate 360. The substrate 360 includes a glass substrate, a plastic substrate or an insulating substrate, and the first gate 350 includes a metal or a metal alloy. Next, as shown in FIG. 3B, a first insulating layer 340 is formed over the substrate 360 and covers the first gate 350. Wherein, the first insulating layer 340 comprises cerium nitride, oxynitride, nitride, oxynitride or oxide. Then, as shown in Fig. 3C, an amorphous germanium layer 330 is formed on the first insulating layer 34. Next, as shown in FIG. 3D, an etch-stop layer 380 is formed over a portion of the amorphous germanium layer 330, and the etch stop layer 380 corresponds to the first gate 350. Then, as shown in Fig. 3E, the amorphous germanium layer 330 of the portion exposed by the etch stop layer 380 is removed to form an amorphous germanium channel layer 330a. The amorphous germanium channel layer 330a is formed corresponding to the first gate 350 and is located within the first gate 350. Next, as shown in FIG. 3F, a source 310 and a drain 320 are formed on the amorphous germanium channel layer 330a, and the source 310 and the drain 320 correspond to the first TW2249PA 12 1250654, respectively.

, Sanda number: TW2249PA two ends of the two holy Gan, the money stop layer is located at the source 310 and the pole 320 U _ source 3H) and the pole 32 () contains metal or metal alloy. In this embodiment, a more heavily formed N-type (N+) semiconductor layer is cut between the source, the drain and the drain 320 and the amorphous germanium channel layer 33〇a, and the heavily doped N-type semiconductor layer 321 and coated with the side wall of the amorphous channel layer 3, the source training and the pole 320 correspondingly pass through the heavily doped N-type (N+) semiconductor layer &

Both ends of the track layer 330a are in contact. F S Then, as shown in Fig. 3G, a second insulating layer 37 is formed covering the source 310 and the drain 32G, and has a second contact hole 375 of the exposed portion of the drain 32 (). Wherein the second insulating layer 37 contains gasification, oxynitride, nitride, nitrogen oxides or oxides. Next, as shown in FIG. 3H, a second gate 390 and a pixel electrode 395 are electrically isolated from each other on the second insulating layer 37, and the pixel electrode is transparent, and the second contact hole 375 and the drain 320 are connected. Electrical connection. The second gate 39 〇 corresponds to the first gate 350 and is electrically connected to the first gate 350 through a first contact hole (not shown), and the edge of the second gate 390 and the source 310 and the gate The edges of the poles 32 〇 overlap, and the amorphous germanium film transistor 3 〇〇 is completed here. It should be understood by those skilled in the art that the first contact hole can be completed between the first gate 350 completion step and the second gate 39 completion step. In FIG. 3H, the amorphous germanium thin film transistor 300 having the double gate structure according to the embodiment includes at least a substrate 360, a first gate 350, a first gate 390, and an amorphous stone. The channel layer 330a, a residual stop layer 380, a source 310 and a drain 320. The first gate 350 is formed on the substrate 360, and the austenite channel layer 330a is formed on the first gate 350 and within the first gate 35A. The source 310 and the drain 320 are in a direction corresponding to both ends of the first gate 350

TW2249PA 13 1250654

• Sanda number: TW2249PA is formed on the amorphous channel layer 33 as above, and the etch stop layer 38 is located between the source 3i and the drain 320 and the amorphous channel layer 33A, the source 31 and the drain 32〇 is correspondingly in contact with both ends of the amorphous stone channel layer 33〇a. The second idle electrode 39 is formed on the source 31A and the drain 32A in a manner corresponding to the first gate 350, and is electrically connected to the first gate 350. The outer edge of the second gate 39 is partially overlapped with the inner edge of the source 3 10 and the drain 320. However, those skilled in the art to which the present invention pertains can understand that the technology of the present embodiment is not limited thereto. For example, the first questioner 35 and the second gate may be the same material as the second gate. 39〇 contains metal or metal alloys. The materials of the first gate 350 and the second gate 39 may be different. For example, the second gate 390 comprises indium tin oxide, indium zinc oxide, rhodium oxide, tin oxide or zinc oxide. Further, the pixel electrode 395 contains a metal or a metal alloy, or contains indium tin oxide, indium zinc oxide, tin oxide, tin oxide or oxidized. If the materials of the second gate 390 and the halogen electrode 395 are the same, the second interlayer _ and the pixel electrode 395 can be simultaneously or non-simultaneously completed. If the materials of the second gate and the pixel electrode 395 are different, the second closed electrode 39 can be completed or completed later than the halogen electrode 395. As the second gate 390 is electrically connected to the first gate 35, and the edge of the second interlayer 390 partially overlaps the edge of the source 3 1 〇 and the drain 32 ,, when the first gate 350 and the first When a voltage is applied to the second gate 39〇, the amorphous germanium channel layer η is added to the near-first insulating layer 34〇 and the second insulating layer is over the upper surface of the second insulating layer, which is like the amorphous channel layer. A two-current pass is formed at the lower surface of 33()a, and the amorphous channel layer is formed in the first gate, and the channel side is contacted with the heavily doped N-type (N+) semiconductor layer 321 to provide the lower side. Interface charge: The conductive path can reduce the parasitic resistance of the source 310 and the immersed 32 ,, greatly increasing the electron mobility of the amorphous germanium channel layer 330a. Therefore, the TW2249PA i4 and 1250654 of this embodiment

'Sanda number: TW2249PA = thin film transistor is higher than the traditional amorphous (four) film transistor i has a higher electrical power, so the application of the amorphous germanium thin film transistor 3 〇〇 application: active array An organic light-emitting diode display or a heart-related circuit does not require a high voltage. In this way, the voltage can be greatly reduced and the voltage of the door can be increased, and the reliability of the operating speed of the i circuit can be increased. (4) New-non-(four) thin film electro-crystals ★ This is the double gate disclosed in the above-mentioned examples. The amorphous structure of the amorphous thin-film transistor and the manufacturing method thereof, wherein the second gate is electrically connected to the first idle electrode, and the edge of the second gate overlaps the edge of the source and the drain The electron mobility of the amorphous channel layer between the first gate and the second gate can be increased. Therefore, the current conducting capability of the amorphous thin film transistor can be greatly increased. Further, in this embodiment The amorphous austenitic thin film transistor can be applied to an active matrix organic light emitting diode display or an a-Si related circuit, and does not require a high operating voltage. Thus, not only the non-θ曰矽溥 film transistor is reduced. Operating the voltage, and increasing the operating speed of the a_si circuit, can increase the reliability of the amorphous silicon film transistor. In summary, although the present invention has been disclosed above in a preferred embodiment, it is not used. To limit the invention, any familiarity with this technique The scope of protection of the present invention is defined by the scope of the appended claims. TW2249PA 15 1250654 </ RTI> </ RTI> </ RTI> </ RTI>

A three-daed code: TW2249PA [Simple description of the drawing] FIG. 1 is a structural sectional view of a conventional amorphous germanium thin film transistor; and FIGS. 2A to 2F are diagrams showing a double gate of the first embodiment of the present invention. A process sectional view of a structure of an amorphous germanium film transistor; and FIGS. 3A to 3H are cross-sectional views showing a process of a thin film transistor having a double gate structure according to a second embodiment of the present invention. [Description of main component symbols] • 1, 200, 300: Amorphous germanium thin film transistors 2, 121, 321 : heavily doped N-type (N+) semiconductor layers 10, 110, 310: sources 20, 120, 320: 汲Pole 30, 130, 330a: amorphous germanium channel layer 40: insulating layer 50: gate 60, 160, 360: substrate • 210, 370: second insulating layer 220, 390: second gate 230, 395: halogen Electrodes 240, 340: first insulating layer 250, 350: first gate 260, 375: second contact hole 330: amorphous germanium layer 380 · etch stop layer TW2249PA 16

Claims (1)

1250654 Sanda number: TW2249PA X. Patent application scope: Including: 1 · A substrate of amorphous germanium thin film transistor with double gate structure; a first gate formed on the substrate; an amorphous germanium channel layer Formed on the first gate, the upper layer is located in the first gate; the amorphous germanium passes through a source and a drain to correspond to the first gate to form the amorphous On the Shiyue channel layer, correspondingly to the amorphous: the shape touch; and k increasing the two ends connected to a second gate to correspond to the first gate of the square, the: And electrically connected to the first gate, the I gate overlaps the edge of the source and the drain. Edge 2. For special shots, please select the amorphous 7-phase transistor of the third item, including the . The first (four) stop layer is formed in the amorphous material layer and the second interpole-f; the amorphous (four) film transistor of the first item of the second application range, wherein the first gate and the δHaiyi The material of the interpole is the same. The first special alloy is the amorphous Aussie thin film transistor of the first item, wherein the material of the second gate and the second gate of the brother are different. In the t-th order, the amorphous (four) film transistor of the first item is included, which causes the indium tin oxide (indium tin oxide) and the indium zinc oxide (indium zinc oxide ^ Ί7Π^ &gt; ^ ^ ^ cadmium tin oxide (CTO:, tin oxide (stannum di〇xide, Sn〇2) or oxidized (also - ZnO). : 2 patent application scope of the first item of the amorphous stone film a transistor, wherein the first gate comprises a metal or a metal alloy. TW2249PA 17 1250654 - Sanda number: TW2249PA 7 - A method for manufacturing an amorphous germanium thin film transistor having a double gate structure, comprising: providing a substrate; Forming a first gate on the substrate; forming a first insulating layer over the substrate and covering the first gate; forming an amorphous channel layer on the first insulating layer; forming a a source and a drain on the amorphous channel layer, the source and the drain corresponding to both ends of the first gate, and correspondingly contacting the ends of the amorphous channel layer; forming a first a second insulating layer covering the source and the drain; and forming a a gate on the second insulating layer, the second gate corresponding to the first gate, and electrically connected to the first gate, the edge of the second gate and the source and the drain The method of manufacturing the method of claim 7, wherein the first gate and the second gate are made of the same material. 9. The manufacturing method of claim 7, wherein the The method of manufacturing a method according to the seventh aspect of the invention, wherein the second gate comprises indium tin oxide (IT0), copper oxide (zinc oxide ' IZO ), money tin oxide (etomium tin 〇xide, cto), tin oxide (Stannum dioxide, Sn〇2) or zinc oxide (ζ' (10) heart, zn〇). 11 · Patent application scope The manufacturing method of item 7, wherein the second gate comprises a metal or a metal alloy. 12. A method for manufacturing an amorphous germanium thin film transistor having a double gate structure, comprising: providing a substrate; TW2249PA 18 1250654 ” No.: TW2249PA forms a ^6 pole on the base Forming a first ^ @ forming - non-曰 on the substrate and covering the first - idle pole; forming an amorphous layer on the first insulating layer; pole corresponding to the first amorphous layer Above, between the source and the drain; at both ends of the 19, the secret layer is located at the source and the ridge And (4) the pole and the (4) stop layer exposed by the amorphous layer, to open the $ 忐 nk 哕 卜 卜 卜 矽 矽 矽 矽 , , , , , , , , , , , , , , , , , , , , , , 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽Contacting at both ends; forming a two-link layer covering the source and the drain; and *7 into a first gate on the second insulating layer, the second gate corresponding to the H gate 'and the first The gate is electrically connected, and the edge of the second gate partially overlaps the source and the edge of the drain. 13. The manufacturing method of claim 12, wherein the first gate and the third gate are the same material. The manufacturing method of claim 12, wherein the first gate and the second gate are different in material. The manufacturing method of claim 12, wherein the second gate comprises indium tin oxide (IT〇), indium zinc oxide (inc), and tin oxide (cadmium) Tin (10) 丨, CTO), stannum dioxide (Sn02) or zinc oxide (ZnO). The method of manufacturing the invention of claim i, wherein the second gate comprises a metal or a metal alloy. TW2249PA 19