JP2016504751A5 - - Google Patents

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JP2016504751A5
JP2016504751A5 JP2015536868A JP2015536868A JP2016504751A5 JP 2016504751 A5 JP2016504751 A5 JP 2016504751A5 JP 2015536868 A JP2015536868 A JP 2015536868A JP 2015536868 A JP2015536868 A JP 2015536868A JP 2016504751 A5 JP2016504751 A5 JP 2016504751A5
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thin
conductive material
height
chip
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Claims (29)

  1. A)スタンドオフウェル領域を備える基板を備える装置であって、
    前記基板が、可撓性ポリマーの層の上に配設された第1の導電性材料の層を備え、
    前記第1の導電性材料のパターン形成部分が、露出された可撓性ポリマーの一部分と境界を画すスタンドオフを備え、それにより前記スタンドオフウェル領域を形成し、
    装置がさらに、
    B)前記スタンドオフの近位の前記露出された可撓性ポリマーの一部分の上で前記スタンドオフウェル領域の内部に配設された薄型チップを備え、
    前記スタンドオフの高さが、前記薄型チップの高さと同等である
    装置。
  2. 前記スタンドオフの近位の前記露出された可撓性ポリマーの一部分で、前記スタンドオフウェル領域の内部に塗着された接着材を備え、前記薄型チップが、前記スタンドオフの近位の前記接着材の上に配設される請求項1に記載の装置。
  3. 前記接着材が、約8μm、約10μm、約12μm、約15μm、約20μm、約25μm、または約30μmの厚さを有する請求項2に記載の装置。
  4. 前記接着材が、導電性接着剤または非導電性接着剤を含む請求項2に記載の装置。
  5. 前記第1の導電性材料の前記パターン形成部分が、レーザアブレーションまたはエッチングを使用して形成される請求項1に記載の装置。
  6. 前記可撓性ポリマーが、ポリイミドまたは液晶ポリマーである請求項1に記載の装置。
  7. 前記第1の導電性材料が、銅、金、アルミニウム、またはそれらの何らかの組合せを含む請求項1に記載の装置。
  8. 前記基板が、銅−クラッドポリイミドである請求項1に記載の装置。
  9. 前記可撓性ポリマーの層が、約8μm、約10μm、約15μm、約25μm、約35μm、約50μm、約60μm、約75μm、または約85μmの厚さを有する請求項1に記載の装置。
  10. 前記第1の導電性材料の層が、約2μm、約5μm、約8μm、約12μm、約15μm、約25μm、約35μm、約50μm、約60μm、または約70μmの厚さを有する請求項1に記載の装置。
  11. 前記薄型チップが、約2μm、約5μm、約8μm、約12μm、約15μm、約25μm、約35μm、約50μm、約60μm、または約70μmの厚さを有する請求項1に記載の装置。
  12. 前記薄型チップが、薄型化されたチップである請求項1に記載の装置。
  13. 前記薄型化されたチップが、エッチングプロセスまたは研削プロセスを使用して薄型化されたチップから形成される請求項12に記載の装置。
  14. 前記スタンドオフの前記高さが前記薄型チップの前記高さよりも大きくなる、またはほぼ等しくなるように、前記薄型チップが前記スタンドオフウェル領域の内部に配設される請求項1に記載の装置。
  15. 前記スタンドオフの前記高さが前記薄型チップの前記高さよりも小さくなるように、前記薄型チップが前記スタンドオフウェル領域の内部に配設される請求項1に記載の装置。
  16. 前記薄型チップが、約2μm、約5μm、約8μm、約12μm、約15μm、約25μm、約35μm、約50μm、約60μm、または約70μmの厚さを有する第1の導電性材料の層を有する請求項1に記載の装置。
  17. 前記基板の上に配設されたポリマーシートと、
    前記ポリマーシートを通して形成された少なくとも1つのバイアと、
    前記少なくとも1つのバイアの近位の前記ポリマーシートの一部分の上に配設された第2の導電性材料とをさらに備え、それにより、前記第2の導電性材料が、前記薄型チップの電気コンタクトとの電気的連絡を形成する
    請求項1に記載の装置。
  18. 前記第2の導電性材料が、チタン、タングステン、金、ニッケル、クロム、またはそれらの何らかの組合せを含む請求項17に記載の装置。
  19. 前記スタンドオフが、前記薄型チップの一部分を取り囲む請求項1に記載の装置。
  20. 前記スタンドオフが、前記薄型チップを完全に取り囲む請求項1に記載の装置。
  21. 誘電体材料が、前記スタンドオフと前記薄型チップの一部分との間に配設される請求項1に記載の装置。
  22. 前記第1の導電性材料の上または前記可撓性ポリマーの上に配設された少なくとも1つの追加の層をさらに備え、前記少なくとも1つの追加の層が、前記薄型チップを前記装置の中立機械面に位置決めする請求項1に記載の装置。
  23. 薄型チップを埋め込むための方法であって、
    A)スタンドオフウェル領域を備える基板を提供するステップを含み、
    前記基板が、可撓性ポリマーの層の上に配設された第1の導電性材料の層を備え、
    前記第1の導電性材料の少なくとも一部分が、露出された可撓性ポリマーの一部分と境界を画すスタンドオフを形成するようにパターン形成され、それにより前記スタンドオフウェル領域を形成し、
    方法がさらに、
    B)前記スタンドオフの高さが前記薄型チップの高さと同等になるように、前記スタンドオフの近位の前記露出された可撓性ポリマーの一部分の上に薄型チップを配設するステップ
    を含む方法。
  24. ステップB)の前に、前記スタンドオフの近位の前記露出された可撓性ポリマーの一部分に接着材を配設するステップを含み、ステップB)が、前記スタンドオフの近位の前記露出された可撓性ポリマーの前記部分に塗着された接着材上に前記薄型チップを配設するステップを含む請求項23に記載の方法。
  25. 前記スタンドオフの前記高さが、薄型チップの前記高さよりも大きい、またはほぼ等しい請求項23に記載の方法。
  26. ステップB)が、前記スタンドオフの前記高さが前記薄型チップの前記高さよりも大きくなる、またはほぼ等しくなるように、前記スタンドオフの近位の前記可撓性ポリマーの一部分の上に前記薄型チップを配設するステップを含む請求項23に記載の方法。
  27. 前記薄型チップが、薄型化されたチップであり、ステップB)が、前記薄型化されたチップを提供するために、エッチングプロセスまたは研削プロセスを使用してチップを薄型化するステップと、前記スタンドオフの前記高さが前記薄型化されたチップの前記高さと同等になるように、前記スタンドオフの近位の前記露出された可撓性ポリマーの一部分の上に前記薄型化されたチップを配設するステップとを含む請求項23に記載の方法。
  28. 前記基板の上にポリマーシートを配設するステップと、
    前記ポリマーシートを通して少なくとも1つのバイアを形成するステップと、
    前記少なくとも1つのバイアの近位の前記第2のポリマーシートの一部分の上に導電性材料を配設するステップとをさらに含み、それにより、前記導電性材料が、前記薄型チップの電気コンタクトとの電気的連絡を形成する
    請求項23に記載の方法。
  29. 前記第1の導電性材料の上または前記可撓性ポリマーの上に少なくとも1つの追加の層を配設するステップをさらに含み、前記少なくとも1つの追加の層が、前記薄型チップを前記装置の中立機械面に位置決めする請求項23に記載の方法。
JP2015536868A 2012-10-09 2013-10-09 ポリマー内への薄型チップの埋込み Pending JP2016504751A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261711629P 2012-10-09 2012-10-09
US61/711,629 2012-10-09
US13/844,638 US9171794B2 (en) 2012-10-09 2013-03-15 Embedding thin chips in polymer
US13/844,638 2013-03-15
PCT/US2013/064152 WO2014059032A1 (en) 2012-10-09 2013-10-09 Embedding thin chips in polymer

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JP2016504751A JP2016504751A (ja) 2016-02-12
JP2016504751A5 true JP2016504751A5 (ja) 2016-10-13

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US (3) US9171794B2 (ja)
EP (1) EP2907159A4 (ja)
JP (1) JP2016504751A (ja)
KR (1) KR20150067302A (ja)
CN (1) CN104798196A (ja)
WO (1) WO2014059032A1 (ja)

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