CN112436019A - 半导体设备封装和其制造方法 - Google Patents

半导体设备封装和其制造方法 Download PDF

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CN112436019A
CN112436019A CN201910955871.1A CN201910955871A CN112436019A CN 112436019 A CN112436019 A CN 112436019A CN 201910955871 A CN201910955871 A CN 201910955871A CN 112436019 A CN112436019 A CN 112436019A
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Prior art keywords
substrate
layer
buffer layer
conductive
disposed
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陈明宏
陈胜育
叶昶麟
叶勇谊
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN112436019A publication Critical patent/CN112436019A/zh
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    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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Abstract

一种半导体设备封装，其包含第一衬底、介电层、薄膜晶体管(TFT)和电子部件。所述第一衬底具有第一表面和与所述第一表面相对的第二表面。所述介电层安置在所述第一衬底的所述第一表面上。所述介电层具有背对所述第一衬底的第一表面和与所述第一表面相对的第二表面。所述TFT层安置在所述介电层上。所述电子部件安置在所述第一衬底的所述第二表面上。所述介电层的所述第一表面的粗糙度小于所述第一衬底的所述第一表面的粗糙度。

Description

半导体设备封装和其制造方法
技术领域
本公开总体上涉及一种半导体设备封装和其制造方法，并且涉及包含显示设备的半导体设备封装和其制造方法。
背景技术
可穿戴电子部件(例如，电子手表、电子带等)通常具有附接到容纳一些电子部件的外壳的带。一或多个额外功能可能需要集成到手表中(地理信息收集或确定；生物信息收集或确定等)，这意味着更多部件(如全球定位系统(GPS)模块、心率感测模块等)应被引入到外壳中。结果，外壳的大小和重量必然会增加，这可能会不利地影响用户体验。
发明内容
根据本公开的一方面，一种半导体设备封装包含第一衬底、介电层、薄膜晶体管(TFT)和电子部件。所述第一衬底具有第一表面和与所述第一表面相对的第二表面。所述介电层安置在所述第一衬底的所述第一表面上。所述介电层具有背对所述第一衬底的第一表面和与所述第一表面相对的第二表面。所述TFT层安置在所述介电层上。所述电子部件安置在所述第一衬底的所述第二表面上。所述介电层的所述第一表面的粗糙度小于所述第一衬底的所述第一表面的粗糙度。
根据本公开的另一方面，一种半导体设备封装包含第一衬底、缓冲层、TFT和电子部件。所述第一衬底具有第一表面和与所述第一表面相对的第二表面。所述缓冲层安置在所述第一衬底的所述第一表面上。所述缓冲层具有背对所述第一衬底的第一表面。所述TFT层安置在所述缓冲层的所述第一表面上并电连接到所述缓冲层。所述电子部件安置在所述第一衬底的所述第二表面上。
根据本公开的另一方面，一种制造半导体设备封装的方法包含：(a)提供载体；(b)在所述载体上形成缓冲层；(c)在所述缓冲层上形成TFT层；(d)移除所述载体以暴露背对所述TFT层的所述缓冲层的第一表面；(e)在所述缓冲层的所述第一表面上形成第一衬底；以及(f)将电子部件安置在所述第一衬底上。
根据本公开的另一方面，一种制造半导体设备封装的方法包含：(a)提供载体；(b)在所述载体上形成第一衬底，所述第一衬底具有背对所述载体的第一表面和与所述第一表面相对的第二表面；(c)在所述第一衬底的所述第一表面上形成展平介电层；(d)形成穿透所述介电层的开口以暴露所述第一衬底的所述第一表面；(e)在所述介电层上形成导电层并沿着所述开口的侧壁延伸以电连接到所述第一衬底；(f)在所述介电层上形成绝缘层；(g)在所述绝缘层上形成TFT层；(h)移除所述载体以暴露所述第一衬底的所述第二表面；以及(i)将电子部件安置在所述第一衬底的所述第二表面上。
附图说明
图1A示出了根据本公开的一些实施例的半导体设备封装的横截面视图；
图1B示出了根据本公开的一些实施例的如图1A所示的半导体设备封装的一部分的放大视图；
图1C示出了根据本公开的一些实施例的如图1A所示的半导体设备封装的一部分的放大视图；
图1D示出了根据本公开的一些实施例的如图1A所示的半导体设备封装的一部分的放大视图；
图1E示出了根据本公开的一些实施例的如图1A所示的半导体设备封装的一部分的放大视图；
图2示出了根据本公开的一些实施例的半导体设备封装的横截面视图；
图3A、图3A'、图3A”、图3B、图3C、图3D和图3E是根据本公开的一些实施例的半导体设备封装在不同制造阶段的横截面视图；
图4A、图4A'、图4B、图4B'、图4B”、图4C和图4D是根据本公开的一些实施例的半导体设备封装在不同制造阶段的横截面视图；
图5A和图5B是根据本公开的一些实施例的半导体设备封装在不同制造阶段的横截面视图；并且
图6A和图6B是根据本公开的一些实施例的半导体设备封装在不同制造阶段的横截面视图。
贯穿附图和具体实施方式，使用共同的附图标记来指示相同或相似的部件。根据下文结合附图进行的详细描述可以更好地理解本公开。
具体实施方式
以下公开提供了用于实施所提供主题的不同特征的许多不同的实施例或实例。以下描述了部件和布置的具体实例。当然，这些仅仅是实例，并且不旨在是限制性的。在本公开中，在以下描述中提及在第二特征上方或之上形成第一特征可以包含直接接触形成的第一特征和第二特征的实施例，并且还可以包含在第一特征与第二特征之间形成的另外的特征的实施例，使得第一特征和第二特征可以不直接接触。此外，本公开可以在各个实例中重复参考标记和/或字母。这种重复是为了简单和清楚的目的，并且本身并不指定所讨论的各个实施例和/或配置之间的关系。
下面将详细讨论本公开的实施例。然而，应当理解的是，本公开提供了许多可应用的概念，这些概念可以在各种各样的具体背景下实施。所讨论的具体实施例仅仅是说明性的，并且不限制本公开的范围。
图1A示出了根据本公开的一些实施例的半导体设备封装1的横截面视图。半导体设备封装1包含衬底10、薄膜晶体管(TFT)层120、衬底130、发光设备140、包封物150、电子部件220、221、222以及封装体230。在一些实施例中，半导体设备封装1可以在可弯曲或柔性电子部件(例如，电子手表、电子带等)中使用或实施。
衬底10可以包含例如印刷电路板(如纸基铜箔层压板、复合铜箔层压板或聚合物浸渍玻璃纤维基铜箔层压板)。衬底10可以包含互连结构，如再分布层(RDL)或接地元件。衬底10包含表面111和与表面111相对的表面112。
TFT层120安置在衬底110的表面111上。在一些实施例中，如图1A所示，TFT层120可以是或包含电连接到发光设备140的驱动电路。例如，所述驱动电路被配置成向发光设备140发送驱动电流(或电压)，并且发光设备140由驱动电流驱动以发出具有与驱动电流的量级相对应的亮度的光。多种电路可以用作驱动发光设备140的驱动电路。例如，驱动电路可以包含多个晶体管和至少一个存储电容器。例如，驱动电路可以包含指示为5T/1C型、4T/1C型、3T/1C型、2T/1C型等的驱动配置，其中T表示晶体管，而C表示存储电容器。在一些实施例中，如图1A所示，驱动电路的晶体管可以包含绝缘层115、栅极121、栅极绝缘体(例如，介电材料)122、半导体沟道123、漏极124、源极125和钝化层126。在一些实施例中，驱动电路的晶体管的结构可以根据不同的设计要求而改变或调整。
衬底130安置在TFT层120上。衬底130可以包含例如印刷电路板(如纸基铜箔层压板、复合铜箔层压板或聚合物浸渍玻璃纤维基铜箔层压板)。衬底130可以包含互连结构，如RDL或接地元件。衬底130包含用于容纳发光设备140的空腔130c。在一些实施例中，根据不同的设计要求，空腔130c的深度可以大于、等于或小于发光设备140的厚度。
发光设备140安置在衬底130的空腔130c内。发光设备140通过衬底130(例如，通过衬底130的互连结构)电连接到TFT层120。在一些实施例中，发光设备140可以是或包含微型LED。在一些实施例中，发光设备140可以是或包含液晶显示器(LCD)、有机发光二极管(OLED)或任何其它合适的发光单元。
包封物150安置在衬底130上和衬底130的空腔130c内。包封物150覆盖发光设备140以保护发光设备140。在一些实施例中，包封物150由透光材料形成或包含所述透光材料，以允许由发光设备140发出的光穿过。
电子部件220、221和222安置在衬底10的表面112上。电子部件220、221和222可以是或包含有源部件、无源部件和/或其组合。例如，电子部件220可以是包含半导体衬底、一或多个集成电路设备以及其中的一或多个上覆互连结构的芯片或管芯。例如，电子部件221可以是传感器或微机电系统(MEMS)。例如，电子部件222可以是电容器。电子部件220、221和222通过衬底10(例如，所述互连结构)彼此电连接或连接到TFT层120。在一些实施例中，电子部件220、221和222可以通过例如焊球电连接到衬底10的表面112。在一些实施例中，焊球的熔化温度等于或小于约200度。
封装体230安置在衬底10的表面112上，并覆盖电子部件220、221和222。在一些实施例中，封装体230包含环氧树脂，所述环氧树脂具有分散在其中的填料。
图1B示出了根据本公开的一些实施例的由如图1A所示的虚线正方形1A包围的半导体设备封装1的一部分的放大视图。如图1B所示，衬底10可以具有部分110和210。衬底10的部分110(也称为介电层或缓冲层)安置在衬底10的部分210上。导电层116安置在衬底10的部分110的表面(例如，表面111)上并在衬底10的部分110内延伸以电连接到衬底10的部分210的导电衬垫210p。在一些实施例中，导电层116的延伸部分围绕TFT层120的绝缘层115。例如，衬底10的部分110可以包含穿透部分110以暴露导电衬垫210p的开口。导电层116安置在开口的侧壁上，并且绝缘层115安置在开口内以覆盖导电层116。在其它实施例中，开口可以用导电层116完全填充。
在一些实施例中，衬底10的部分110的厚度是衬底10的部分210的厚度的约3到5倍。在一些实施例中，衬底10的部分110的厚度等于或大于20微米。在一些实施例中，衬底10的部分110的表面111的粗糙度小于衬底10的部分110与部分210之间的界面的粗糙度。在一些实施例中，衬底10的部分110的与表面111相对的表面基本上与导电衬垫210的顶表面共面。
图1C示出了根据本公开的一些实施例的由虚线正方形1B包围的半导体设备封装1的一部分的放大视图。如图1C所示，导电通孔110v安置在衬底10的部分110内，并且从衬底10的部分110的表面111朝向衬底10的部分210逐渐变细。导电通孔210v安置在衬底10的部分210内，并朝向衬底10的部分110逐渐变细。例如，导电通孔110v和210v在相反方向上逐渐变细。导电通孔110v连接到导电通孔210v。
图1D示出了根据本公开的一些实施例的由虚线正方形1B包围的半导体设备封装1的一部分的放大视图。如图1D所示，导电通孔110v安置在衬底10的部分110内，并从衬底10的部分210朝向衬底10的部分110的表面111逐渐变细。导电通孔210v安置在衬底10的部分210内，并朝向衬底10的部分110逐渐变细。例如，导电通孔110v和210v在同一方向上逐渐变细。导电通孔110v连接到导电通孔210v。
图1E示出了根据本公开的一些实施例的由虚线正方形1B包围的半导体设备封装1的一部分的放大视图。如图1E所示，导电通孔110v安置在衬底10的部分110内，并从与衬底10的部分110的表面111相对的表面突出。导电通孔210v安置在衬底10的部分210内，并从衬底10的部分210的表面211凹陷。导电通孔110电连接到导电通孔210。导电通孔110v与导电通孔210v之间的界面和衬底10的部分110与衬底10的部分210之间的界面不共面。
图2示出了根据本公开的一些实施例的半导体设备封装2的横截面视图。半导体设备封装2类似于图1A中的半导体设备封装1，并且以下描述了其间的差异。
衬底10的部分110与衬底10的部分210间隔开。衬底10的部分110和衬底10的部分210通过连接层20连接。连接层20包含粘合剂层21(例如，粘合膏)和穿透粘合剂层21以将衬底110的导电衬垫电连接到衬底210对应的导电衬垫的多个导电通孔22。
图3A、图3A'、图3A”、图3B、图3C、图3D和图3E是根据本公开的一些实施例的半导体设备封装在不同制造阶段的横截面视图。为了更好地理解本公开的方面，已经对这些附图中的至少一些进行了简化。在一些实施例中，图3A、图3A'、图3A”、图3B、图3C、图3D和图3E所示的操作可以用于制造如图1A所示的半导体设备封装1。
参考图3A，提供了载体39。在载体39上形成衬底10。在一些实施例中，衬底10可以是柔性衬底。衬底10可以包含互连结构，如RDL或接地元件。然后，在衬底10上形成包含绝缘层115的TFT层120。
图3A'示出了根据本公开的一些实施例的用于形成衬底10的详细操作。
参考图3A'中的操作(a)，在载体39上形成衬底10的一部分210。在一些实施例中，衬底10的部分210包含多个堆叠的RDL。在一些实施例中，由于制造工艺的限制，衬底10的部分210的顶表面211可能不是平面的。例如，衬底10的部分的顶表面211的粗糙度相对较大。在一些实施例中，衬底10的部分210包含从衬底10的部分210的顶表面211暴露的导电衬垫210p。在一些实施例中，衬底10的部分110的热膨胀系数(CTE)为约12ppm。在一些实施例中，衬底10的部分110的玻璃化转变温度(Tg)等于或大于300度。
参考操作(b)，在衬底10的部分210的顶表面211上形成衬底10的另一部分(例如，部分110，其也可以被称为介电层)。在一些实施例中，衬底10的部分110的厚度是衬底10的部分210的厚度的约3到5倍，以提供展平表面，所述展平表面将促进在随后的过程中形成TFT层120。在一些实施例中，衬底10的部分110的厚度等于或大于20微米。在一些实施例中，衬底10的部分110的顶表面的粗糙度小于衬底10的部分210的顶表面211的粗糙度。
参考操作(c)，形成穿透衬底10的部分110的开口110h以暴露导电衬垫210p。在衬底10的部分110的顶表面上形成导电层116，并使所述导电层沿着开口110h的侧壁延伸。在一些实施例中，开口110h未用导电层116完全填充。在一些实施例中，导电层116通过物理气相沉积(PVD)形成。然后，在衬底10的部分110上和开口110h内形成TFT层120的绝缘层115，以覆盖导电层116。
图3A”示出了根据本公开的一些实施例的用于形成衬底10的详细操作。在一些实施例中，图3A”中的操作(a)在图3A'中的操作(a)之后执行。
参考图3A”中的操作(a)，通过例如研磨或任何其它合适的工艺来移除衬底10的部分210的和导电衬垫210p的一部分，以形成平面的顶表面211。
参考图3A”中的操作(b)，在衬底10的部分210的顶表面211上形成衬底10的另一部分(例如，部分110，其也可以被称为介电层)。由于衬底10的部分210的顶表面211已经展平，所以衬底10的部分110可以具有相对较薄的厚度(与图3A'所示的衬底10的部分110相比)。在一些实施例中，面对衬底10的部分210的衬底10的部分110的表面基本上与导电衬垫210p的顶表面共面。
形成穿透衬底10的部分110的开口以暴露导电衬垫210p。在衬底10的部分110的顶表面上形成导电层116，并使所述导电层在开口110h内延伸。在一些实施例中，开口110h用导电层116完全填充。在一些实施例中，导电层116通过电镀形成。
参考图3B，在TFT层120上形成衬底130。衬底130可以包含用于电连接到TFT层120的互连结构(如RDL或接地元件)。在衬底130上形成空腔130c。通过例如放置和拾取技术将发光设备140安置在空腔130c内。然后，在衬底130上和空腔130c内形成包封物150，以覆盖发光设备140。
参考图3C，移除了载体39。在一些实施例中，载体39可以通过紫外(UV)解键合、化学解键合、热解键合、物理密封解键合或任何其它合适的工艺移除。然后，将包封物150放置在载体39'上。
参考图3D，将电子部件220、221和222安置在衬底10上并电连接到衬底10。在一些实施例中，电子部件220、221和222可以通过例如倒装芯片技术、表面安装技术(SMT)、引线键合或任何其它合适的工艺形成。在衬底10上形成封装体230以覆盖电子部件220、221和222。在一些实施例中，封装体230通过模制技术(例如，压缩模制、传递模制等)或任何其它合适的工艺形成。
参考图3E，然后移除载体39'，以形成如图1A所示的半导体设备封装1。在一些实施例中，用于移除载体39的操作适用于移除载体39'。
图4A、图4A'、图4B、图4B'、图4B”、图4C和图4D是根据本公开的一些实施例的半导体设备封装在不同制造阶段的横截面视图。为了更好地理解本公开的方面，已经对这些附图中的至少一些进行了简化。在一些实施例中，图4A、图4A'、图4B、图4B'、图4B”、图4C和图4D所示的操作可以用于制造如图1A所示的半导体设备封装1。
参考图4A，提供了载体49。在载体49上形成缓冲层(例如，衬底10的部分110)。在一些实施例中，缓冲层可以为随后工艺提供支持能力。在一些实施例中，缓冲层可以促进随后工艺中的解键合操作。例如，当在随后的工艺中移除载体49时，缓冲层将避免TFT层120破裂或损坏，这将避免TFT层120的开路问题。在一些实施例中，缓冲层可以包含如图4A所示的图案化导电层(例如，RDL)。在其它实施例中，缓冲层可以包含如图4A'所示的金属板110'。
在缓冲层上形成包含绝缘层125的TFT层120。在TFT层120上形成衬底130。衬底130可以包含用于电连接到TFT层120的互连结构(如RDL或接地元件)。在衬底130上形成空腔130c。通过例如放置和拾取技术将发光设备140安置在空腔130c内。然后，在衬底130上和空腔130c内形成包封物150，以覆盖发光设备140。
参考图4B，移除载体49，并将包封物150放置在载体49”上。在一些实施例中，如果缓冲层包含如图4A'所示的金属板110'，则使金属板110'图案化以形成衬底10的部分110。
图4B'和图4B”示出了根据本公开的一些实施例的由如图4B所示的虚线正方形4B包围的结构的一部分的放大视图。在一些实施例中，图4B'中所示的结构通过图4A和图4B中的操作形成，而图4B”中所示的结构通过图4A'和图4B中的操作形成。
如图4B'所示，将导电通孔110v安置在缓冲层(例如，部分110)内，并且所述导电通孔从绝缘层115朝向背对绝缘层115的缓冲层的表面逐渐变细。将导电通孔115v安置在绝缘层115内，并且所述导电通孔朝向缓冲层逐渐变细。例如，导电通孔110v和115v在同一方向逐渐变细。将导电通孔110v电连接到导电通孔115v。
如图4B”所示，将导电通孔110v安置在缓冲层(例如，部分110)内，并且所述导电通孔朝向绝缘层115逐渐变细。将导电通孔115v安置在绝缘层115内，并且所述导电通孔朝向缓冲层逐渐变细。例如，导电通孔110v和115v在相反方向上逐渐变细。将导电通孔110v电连接到导电通孔115v。
参考图4C，在缓冲层上形成衬底10的部分210。在一些实施例中，衬底10的部分210包含多个相继构建的RDL。
参考图4D，将电子部件220、221和222安置在衬底10的部分210上并电连接到衬底10。在一些实施例中，电子部件220、221和222可以通过例如倒装芯片技术、表面安装技术(SMT)、引线键合或任何其它合适的工艺形成。在衬底10的部分210上形成封装体230以覆盖电子部件220、221和222。在一些实施例中，封装体230通过模制技术(例如，压缩模制、传递模制等)或任何其它合适的工艺形成。然后移除载体49”，以形成如图1A所示的半导体设备封装1。
图5A和图5B是根据本公开的一些实施例的半导体设备封装在不同制造阶段的横截面视图。为了更好地理解本公开的方面，已经对这些附图中的至少一些进行了简化。在一些实施例中，图5A和5B所示的操作可以用于制造如图1A所示的半导体设备封装1。
在一些实施例中，图5A中的操作在图4B中的操作之后执行。参考图5A，衬底10的部分210包含多个RDL，首先相继构建所述多个RDL，并且然后将整个部分210连接到缓冲层(即，部分110)。
图5B示出了根据本公开的一些实施例的由如图5A所示的虚线圆圈包围的结构的一部分的放大视图。如图5B所示，将导电通孔110v安置在衬底10的部分110内，并使所述导电通孔从衬底10的部分110的表面113凹陷。将导电通孔210v安置在衬底10的部分210内，并使所述导电通孔突出衬底10的部分210的表面212。在将导电通孔110与导电通孔210连接之后，导电通孔110v与导电通孔210v之间的界面和衬底10的部分110与衬底10的部分210之间的界面不共面。
在一些实施例中，在图5B中，部分110和210可以通过以下操作连接：(i)在部分110与部分210之间施加等离子体(例如，氢等离子体)；(ii)在约200度的温度下，在导电通孔110v和210v的表面上形成阻挡层(例如，Ti层)；以及(iii)在阻挡层上形成焊料(例如，预焊料)。在一些实施例中，阻挡层的厚度等于或小于10纳米。
在一些实施例中，在图5B中，部分110和210可以通过以下操作连接：(i)向导电通孔110v和210v提供超声振动；(ii)按压部分110和210以使彼此接触；以及(iii)向导电通孔110v和210v提供热量(例如，约100度到约150度)。
图6A和图6B是根据本公开的一些实施例的半导体设备封装在不同制造阶段的横截面视图。为了更好地理解本公开的方面，已经对这些附图中的至少一些进行了简化。在一些实施例中，图6A和6B所示的操作可以用于制造如图2所示的半导体设备封装2。
在一些实施例中，图6A中的操作在图4B中的操作之后执行。参考图6A，将衬底10的部分210通过连接层20(包含粘合剂层21和导电通孔22)连接到衬底10的部分110。
参考图6B，将电子部件220、221和222安置在衬底10的部分210上并电连接到衬底10。在一些实施例中，电子部件220、221和222可以通过例如倒装芯片技术、表面安装技术(SMT)、引线键合或任何其它合适的工艺形成。在衬底10的部分210上形成封装体230以覆盖电子部件220、221和222。在一些实施例中，封装体230通过模制技术(例如，压缩模制、传递模制等)或任何其它合适的工艺形成。然后移除载体59，以形成如图2所示的半导体设备封装2。
如本文所用，术语“基本上(substantially)”、“基本的(substantial)”、“大约(approximately)”和“约(about)”用于表示和说明小的变化。例如，当与数值结合使用时，这些术语可以指小于或等于所述数值的±10％的变化范围，如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％。作为另一个实例，“基本上一致”的膜或层的厚度可以指小于或等于膜或层平均厚度的±10％的标准偏差，如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％。术语“基本上共面”可以指两个平面沿同一平面处于50μm内，如沿同一平面处于40μm内、30μm内、20μm内、10μm内或1μm内。如果例如两个部件重叠或处于200μm内、处于150μm内、处于100μm内、处于50μm内、处于40μm内、处于30μm内、处于20μm内、处于10μm内或处于1μm内，则可以认为这两个部件“基本上对齐”。如果两个表面或部件之间的角为例如90°±10°，如±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°或±0.05°，则可以认为这两个表面或部件“基本上垂直”。当与事件或情况结合使用时，术语“基本上”、“基本的”、“大约”和“约”可以指事件或情况精确发生的实例以及事件或情况接近发生的实例。
在一些实施例的描述中，一个部件提供在另一部件“上”可以涵盖前一部件直接在后一部件上(例如，与后一部件物理接触)的情况以及一或多个中间部件位于前一部件与后一部件之间的情况。
此外，量、比率以及其它数值有时以范围格式呈现在本文中。可以理解的是，此些范围格式是为了方便和简洁而使用的，并且应该灵活地理解为不仅包含明确指定为范围限制的数值，而且还包含所述范围内涵盖的所有单独数值或子范围，就好像每个数值和子范围都被明确指定一样。
虽然已经参照本公开的具体实施例描述和说明了本公开，但是这些描述和说明并不限制本公开。本领域技术人员可以清楚地理解，可以进行各种改变，并且在不脱离如由所附权利要求限定的本公开的真实精神和范围的情况下，可以在实施例中替换等效元件。图示可能不一定按比例绘制。由于制造过程中的变量等原因，本公开中的艺术再现与实际设备之间可能存在区别。可能存在未具体示出的本公开的其它实施例。说明书和附图应被视为说明性的而非限制性的。可以作出修改以使特定情况、材料、物质组成、方法或过程适应本公开的目标、精神和范围。所有此类修改旨在落入所附权利要求的范围内。虽然已经参照以特定顺序执行的特定操作对本文公开的方法进行了描述，但是可以理解的是，在不脱离本公开的教导的情况下，这些操作可以被组合、细分或重新排序以形成等效方法。因此，除非在本文中特别指出，否则这些操作的顺序和分组不受本公开的限制。

Claims (27)

1.一种半导体设备封装，其包括：
第一衬底，所述第一衬底具有第一表面和与所述第一表面相对的第二表面；
介电层，所述介电层安置在所述第一衬底的所述第一表面上，所述介电层具有背对所述第一衬底的第一表面和与所述第一表面相对的第二表面；
薄膜晶体管(TFT)层，所述TFT层安置在所述介电层上；以及
电子部件，所述电子部件安置在所述第一衬底的所述第二表面上，
其中所述介电层的所述第一表面的粗糙度小于所述第一衬底的所述第一表面的粗糙度。
2.根据权利要求1所述的半导体设备封装，其中所述介电层包含用于暴露所述第一衬底的所述第一表面的一部分的开口，并且所述半导体设备封装进一步包括导电层，所述导电层安置在所述介电层上并沿着所述开口的侧壁延伸以电连接到所述第一衬底。
3.根据权利要求1所述的半导体设备封装，其中所述第一衬底包含邻近于所述第一衬底的所述第一表面的导电衬垫，并且所述导电衬垫的顶表面与所述介电层的所述第二表面基本上共面。
4.根据权利要求1所述的半导体设备封装，其中所述电子部件通过焊球电连接到所述第一衬底的所述第二表面，并且所述焊球的熔化温度等于或小于约200度。
5.根据权利要求1所述的半导体设备封装，其进一步包括：
第二衬底，所述第二衬底安置在所述TFT层上，并且所述第二衬底具有空腔；以及
发光设备，所述发光设备安置在所述第二衬底的所述空腔内。
6.根据权利要求1所述的半导体设备封装，其进一步包括封装体，所述封装体安置在所述第一衬底的所述第二表面上并覆盖所述电子部件。
7.一种半导体设备封装，其包括：
第一衬底，所述第一衬底具有第一表面和与所述第一表面相对的第二表面；
缓冲层，所述缓冲层安置在所述第一衬底的所述第一表面上，所述缓冲层具有背对所述第一衬底的第一表面；
薄膜晶体管TFT层，所述TFT层安置在所述缓冲层的所述第一表面上并电连接到所述缓冲层；以及
电子部件，所述电子部件安置在所述第一衬底的所述第二表面上。
8.根据权利要求7所述的半导体设备封装，其进一步包括：
第一导电通孔，所述第一导电通孔处于所述第一衬底内并从所述第一衬底的所述第二表面朝向所述衬底的所述第一表面逐渐变细；以及
第二导电通孔，所述第二导电通孔处于所述缓冲层内并从所述第一表面朝向所述第一衬底逐渐变细，所述第二导电通孔连接到所述第一导电通孔。
9.根据权利要求7所述的半导体设备封装，其进一步包括：
第一导电通孔，所述第一导电通孔处于所述第一衬底内并从所述第一衬底的所述第二表面朝向所述衬底的所述第一表面逐渐变细；以及
第二导电通孔，所述第二导电通孔处于所述缓冲层内并从所述第一衬底朝向所述缓冲层的所述第一表面逐渐变细，所述第二导电通孔连接到所述第一导电通孔。
10.根据权利要求7所述的半导体设备封装，其进一步包括：
第一导电通孔，所述第一导电通孔处于所述第一衬底内；
第二导电通孔，所述第二导电通孔处于所述缓冲层内并电连接到所述第一导电通孔，
其中所述第一导电通孔与所述第二导电通孔之间的界面和所述第一衬底与所述缓冲层之间的界面不共面。
11.根据权利要求7所述的半导体设备封装，其中
所述TFT层包含绝缘层，所述绝缘层安置在所述缓冲层的所述第一表面上；
所述绝缘层具有导电通孔，所述导电通孔朝向所述缓冲层逐渐变细；并且
所述缓冲层具有导电通孔，所述导电通孔朝向所述缓冲层的所述第一表面逐渐变细并与所述绝缘层的所述导电通孔电连接。
12.根据权利要求7所述的半导体设备封装，其中
所述TFT层包含绝缘层，所述绝缘层安置在所述缓冲层的所述第一表面上；
所述绝缘层具有导电通孔，所述导电通孔朝向所述缓冲层逐渐变细；并且
所述缓冲层具有导电通孔，所述导电通孔从所述缓冲层的所述第一表面逐渐变细并与所述绝缘层的所述导电通孔电连接。
13.根据权利要求7所述的半导体设备封装，其进一步包括：
第二衬底，所述第二衬底安置在所述TFT层上，并且所述第二衬底具有空腔；以及
发光设备，所述发光设备安置在所述第二衬底的所述空腔内。
14.根据权利要求7所述的半导体设备封装，其进一步包括封装体，所述封装体安置在所述第一衬底的所述第二表面上并覆盖所述电子部件。
15.一种制造半导体设备封装的方法，其包括：
(a)提供载体；
(b)在所述载体上形成缓冲层；
(c)在所述缓冲层上形成TFT层；
(d)移除所述载体以暴露背对所述TFT层的所述缓冲层的第一表面；
(e)在所述缓冲层的所述第一表面上形成第一衬底；以及
(f)将电子部件安置在所述第一衬底上。
16.根据权利要求15所述的方法，其中在操作(b)中，所述缓冲层包括图案化导电层和覆盖所述图案化导电层的一部分的介电层。
17.根据权利要求15所述的方法，其中在操作(b)中，所述缓冲层包括金属板。
18.根据权利要求17所述的方法，在操作(d)与操作(e)之间进一步包括使所述金属板图案化以限定图案化导电层。
19.根据权利要求17所述的方法，其中操作(e)进一步包括：
提供所述第一衬底，所述第一衬底具有面对所述缓冲层的所述第一表面的第一表面，所述第一衬底具有从所述第一衬底的所述第一表面突出的导电衬垫，所述缓冲层具有从所述缓冲层的所述第一表面凹陷的导电衬垫；以及
将所述第一衬底的所述导电衬垫与所述缓冲层的所述导电衬垫连接。
20.根据权利要求15所述的方法，在操作(c)与操作(d)之间进一步包括：
将第二衬底安置在所述TFT层上，所述第二衬底具有空腔；以及
将发光设备放置在所述空腔内并电连接到所述TFT层。
21.一种制造半导体设备封装的方法，其包括：
(a)提供第一衬底，所述第一衬底具有背对所述载体的第一表面和与所述第一表面相对的第二表面；
(b)在所述第一衬底的所述第一表面上形成展平介电层；
(c)形成穿透所述介电层的开口以暴露所述第一衬底的所述第一表面；
(d)在所述介电层上形成导电层并使所述导电层沿着所述开口的侧壁延伸以电连接到所述第一衬底；
(e)在所述绝缘层上形成TFT层。
22.根据权利要求21所述的方法，在操作(d)与操作(e)之间进一步包括：
在所述介电层上形成绝缘层。
23.根据权利要求22所述的方法，其中所述绝缘层进一步形成在所述开口内并覆盖所述导电层。
24.根据权利要求21所述的方法，在操作(a)与(b)之间进一步包括将所述第一衬底的所述第一表面展平。
25.根据权利要求21所述的方法，其进一步包括：
(f)将第二衬底安置在所述TFT层上，所述第二衬底具有空腔；以及
(g)将发光设备放置在所述空腔内并电连接到所述TFT层。
26.根据权利要求21所述的方法，在操作(a)之前，其进一步包括：
提供载体；以及
在所述载体上形成所述第一衬底。
27.根据权利要求26所述的方法，其进一步包括：
(h)移除所述载体以暴露所述第一衬底的所述第二表面；以及
(i)将电子部件安置在所述第一衬底的所述第二表面上。
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