FR3030112B1 - Assemblage d'une puce de circuits integres et d'une plaque - Google Patents

Assemblage d'une puce de circuits integres et d'une plaque Download PDF

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Publication number
FR3030112B1
FR3030112B1 FR1462372A FR1462372A FR3030112B1 FR 3030112 B1 FR3030112 B1 FR 3030112B1 FR 1462372 A FR1462372 A FR 1462372A FR 1462372 A FR1462372 A FR 1462372A FR 3030112 B1 FR3030112 B1 FR 3030112B1
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France
Prior art keywords
chip
plate
assembling
integrated circuits
edge
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FR1462372A
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FR3030112A1 (fr
Inventor
Louis-Michel Collin
Luc Frechette
Sandrine Lhostis
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SOCPRA Sciences et Genie SEC
STMicroelectronics Crolles 2 SAS
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SOCPRA Sciences et Genie SEC
STMicroelectronics Crolles 2 SAS
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Priority to FR1462372A priority Critical patent/FR3030112B1/fr
Priority to US14/857,041 priority patent/US9589874B2/en
Publication of FR3030112A1 publication Critical patent/FR3030112A1/fr
Priority to US15/414,061 priority patent/US9941188B2/en
Application granted granted Critical
Publication of FR3030112B1 publication Critical patent/FR3030112B1/fr
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37002—Shelf life

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

L'invention concerne un assemblage d'une puce (3) de circuits intégrés et d'une plaque (5), dans lequel au moins un canal (15) disposé entre la puce et la plaque s'étend d'un bord à un autre bord de la plus petite de la puce ou de la plaque, et est délimité par des parois latérales métalliques (17) s'étendant au moins partiellement d'une face de la puce à une face en regard de la plaque.
FR1462372A 2014-12-12 2014-12-12 Assemblage d'une puce de circuits integres et d'une plaque Active FR3030112B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1462372A FR3030112B1 (fr) 2014-12-12 2014-12-12 Assemblage d'une puce de circuits integres et d'une plaque
US14/857,041 US9589874B2 (en) 2014-12-12 2015-09-17 Assembly of an integrated circuit chip and of a plate
US15/414,061 US9941188B2 (en) 2014-12-12 2017-01-24 Assembly of an integrated circuit chip and of a plate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1462372 2014-12-12
FR1462372A FR3030112B1 (fr) 2014-12-12 2014-12-12 Assemblage d'une puce de circuits integres et d'une plaque

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FR3030112A1 FR3030112A1 (fr) 2016-06-17
FR3030112B1 true FR3030112B1 (fr) 2018-02-02

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FR (1) FR3030112B1 (fr)

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US20190357386A1 (en) * 2018-05-16 2019-11-21 GM Global Technology Operations LLC Vascular polymeric assembly
CN109297608B (zh) * 2018-09-19 2019-09-10 北京科技大学 基于掺杂钛酸锶基氧化物的微区热扰动双向锁定探测方法
FR3088109A1 (fr) 2018-11-07 2020-05-08 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d'un circuit de refroidissement
US11735495B2 (en) * 2019-02-27 2023-08-22 Intel Corporation Active package cooling structures using molded substrate packaging technology
EP4030476A1 (fr) * 2021-01-15 2022-07-20 Mitsubishi Electric R & D Centre Europe B.V. Cavité de liquide de refroidissement intégrée dans une carte de circuit imprimé et son procédé de fabrication
JP7391407B2 (ja) 2022-02-08 2023-12-05 健治 大沢 薄型ヒートパイプ

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US4513942A (en) * 1983-05-25 1985-04-30 Bourns, Inc. Plate molding apparatus with interlocking cavity plates
US4748495A (en) * 1985-08-08 1988-05-31 Dypax Systems Corporation High density multi-chip interconnection and cooling package
JPH1064956A (ja) * 1996-08-20 1998-03-06 Fujitsu Ltd フェースダウンボンディング半導体装置
US6548895B1 (en) * 2001-02-21 2003-04-15 Sandia Corporation Packaging of electro-microfluidic devices
TWI290365B (en) * 2002-10-15 2007-11-21 United Test Ct Inc Stacked flip-chip package
US6903929B2 (en) * 2003-03-31 2005-06-07 Intel Corporation Two-phase cooling utilizing microchannel heat exchangers and channeled heat sink
JP3842759B2 (ja) * 2003-06-12 2006-11-08 株式会社東芝 三次元実装半導体モジュール及び三次元実装半導体システム
US7012017B2 (en) * 2004-01-29 2006-03-14 3M Innovative Properties Company Partially etched dielectric film with conductive features
US7364684B2 (en) * 2004-08-16 2008-04-29 Delphi Technologies, Inc. Method of making an encapsulated microelectronic package having fluid carrying encapsulant channels
US7427566B2 (en) * 2005-12-09 2008-09-23 General Electric Company Method of making an electronic device cooling system
TW200735308A (en) * 2005-12-23 2007-09-16 Koninkl Philips Electronics Nv On-chip interconnect-stack cooling using sacrificial interconnect segments
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JP2010161184A (ja) * 2009-01-08 2010-07-22 Hitachi Ltd 半導体装置
US8604603B2 (en) * 2009-02-20 2013-12-10 The Hong Kong University Of Science And Technology Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers
JP5818889B2 (ja) * 2010-07-07 2015-11-18 クラー ハルクKULAH, Haluk 電子冷却用のｃｍｏｓ互換性マイクロチャネルヒートシンクの製造方法
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Also Published As

Publication number Publication date
US20160172278A1 (en) 2016-06-16
US20170133297A1 (en) 2017-05-11
US9589874B2 (en) 2017-03-07
FR3030112A1 (fr) 2016-06-17
US9941188B2 (en) 2018-04-10

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