JP2006060842A - 遅延ロック・ループ - Google Patents
遅延ロック・ループ Download PDFInfo
- Publication number
- JP2006060842A JP2006060842A JP2005253696A JP2005253696A JP2006060842A JP 2006060842 A JP2006060842 A JP 2006060842A JP 2005253696 A JP2005253696 A JP 2005253696A JP 2005253696 A JP2005253696 A JP 2005253696A JP 2006060842 A JP2006060842 A JP 2006060842A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- output
- signal
- transistor
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010363 phase shift Effects 0.000 claims abstract description 12
- 230000006698 induction Effects 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 72
- 230000003071 parasitic effect Effects 0.000 description 37
- 101100102627 Oscarella pearsei VIN1 gene Proteins 0.000 description 25
- 238000012937 correction Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 12
- 238000001514 detection method Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 230000000737 periodic effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 239000013598 vector Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Tests Of Electronic Circuits (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dram (AREA)
- Pulse Circuits (AREA)
Abstract
【解決手段】位相比較器の出力は、位相比較器出力信号を経時時に積分するように機能する差動チャージ・ポンプを駆動する。チャージ・ポンプ出力は、位相比較器の出力が平均で50%の時間だけハイになるようにDLL出力の位相を調整する無限範囲を有するフェーズ・シフタを制御する。DLLが、位相検出器の出力が平均で50%の時間だけハイになるまでフェーズ・シフタを調整するので、DLL出力クロックの入力基準クロックとの関係は、使用される位相検出器のタイプにしか依存しない。さらに、DLLは、ディザ・ジッタを最小限に抑え、同時に獲得時間を最小限に抑えるように制御される。また、デューティ・サイクル補正増幅器を使用して、所望のデューティ・サイクル、たとえば50%を有するDLL出力クロックが生成される。
【選択図】図2
Description
Claims (1)
- 入力信号との所定のタイミング関係で出力信号を生成する回路であって、
前記入力信号と前記出力信号を受けるように結合され、その出力信号の位相が入力信号の位相よりも進んでいるか、それとも遅れているかを示す出力信号を生成する位相検出器と、
前記位相検出器の出力を受けるように結合され、出力電流を生成するチャージ・ポンプと、
チャージ・ポンプに結合され、回路が入力信号と出力信号との間の所望のタイミング関係を得るように機能する獲得モードであることを示すととともに、回路がその獲得モードであることを示す第1の状態であるときに、前記チャージ・ポンプがより大きな出力電流を生成するブースト制御信号と、
入力信号、位相検出器からの出力信号、チャージ・ポンプからの出力電流を受けるように結合され、入力信号の移相を位相検出器によって示される移相方向へ実行して出力信号を生成し、チャージ・ポンプの出力電流によって駆動されるフェーズ・シフタと
を備え、
回路が獲得モードであるときにはチャージ・ポンプによって出力される電流を増加させ、回路が獲得モードでないときには電流出力をより低いレベルに維持することによって、回路中のジッタが最小限に抑えられることを特徴とする回路。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US19658394A | 1994-02-15 | 1994-02-15 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52136695A Division JP3754070B2 (ja) | 1994-02-15 | 1995-02-09 | 遅延ロック・ループ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006060842A true JP2006060842A (ja) | 2006-03-02 |
JP4188349B2 JP4188349B2 (ja) | 2008-11-26 |
Family
ID=22725972
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52136695A Expired - Fee Related JP3754070B2 (ja) | 1994-02-15 | 1995-02-09 | 遅延ロック・ループ |
JP2005253696A Expired - Fee Related JP4188349B2 (ja) | 1994-02-15 | 2005-09-01 | 遅延ロック・ループ |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52136695A Expired - Fee Related JP3754070B2 (ja) | 1994-02-15 | 1995-02-09 | 遅延ロック・ループ |
Country Status (5)
Country | Link |
---|---|
US (1) | US5614855A (ja) |
JP (2) | JP3754070B2 (ja) |
KR (1) | KR100393317B1 (ja) |
AU (1) | AU1841895A (ja) |
WO (1) | WO1995022206A1 (ja) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7548100B2 (en) | 2006-04-24 | 2009-06-16 | Hynix Semiconductor Inc. | Delay locked loop |
KR100910785B1 (ko) | 2007-09-27 | 2009-08-04 | 인하대학교 산학협력단 | Dll 기반의 듀티사이클 보정회로 |
US7593285B2 (en) | 2006-08-31 | 2009-09-22 | Hynix Semiconductor, Inc. | Semiconductor memory device with delay locked loop |
US7633832B2 (en) | 2006-12-22 | 2009-12-15 | Hynix Semiconductor Inc. | Circuit for outputting data of semiconductor memory apparatus |
US7652514B2 (en) | 2007-06-11 | 2010-01-26 | Hynix Semiconductor Inc. | Internal clock driver circuit |
US7843743B2 (en) | 2007-04-13 | 2010-11-30 | Hynix Semiconductor Inc. | Data output circuit for semiconductor memory apparatus |
US7911251B2 (en) | 2009-05-11 | 2011-03-22 | Hynix Semiconductor Inc. | Clock signal generating circuit and semiconductor memory apparatus including the same |
CN102055436A (zh) * | 2009-10-30 | 2011-05-11 | 海力士半导体有限公司 | 用于校正时钟信号的占空比的装置和方法 |
US8120403B2 (en) | 2008-05-21 | 2012-02-21 | Elpida Memory, Inc. | Duty detection circuit |
US8154331B2 (en) | 2009-11-30 | 2012-04-10 | Hynix Semiconductor Inc. | Duty correction circuit |
US8222938B2 (en) | 2010-02-24 | 2012-07-17 | Hynix Semiconductor Inc. | Delay locked loop semiconductor apparatus that models a delay of an internal clock path |
US8242821B2 (en) | 2009-06-17 | 2012-08-14 | Samsung Electronics Co., Ltd. | Delay-locked loop for correcting duty ratio of input clock signal and output clock signal and electronic device including the same |
US8487671B2 (en) | 2010-03-16 | 2013-07-16 | Elpida Memory, Inc. | Internal-clock adjusting circuit |
Families Citing this family (224)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5796673A (en) | 1994-10-06 | 1998-08-18 | Mosaid Technologies Incorporated | Delay locked loop implementation in a synchronous dynamic random access memory |
US5764091A (en) * | 1995-01-25 | 1998-06-09 | Matsushita Electric Industrial Co., Ltd. | Method and system for clock-signal waveform correction |
JP3639000B2 (ja) * | 1995-06-13 | 2005-04-13 | 富士通株式会社 | 位相合わせ装置及び遅延制御回路 |
JP3355894B2 (ja) * | 1995-09-27 | 2002-12-09 | 安藤電気株式会社 | 可変遅延回路 |
US6642746B2 (en) * | 1996-01-02 | 2003-11-04 | Rambus Inc. | Phase detector with minimized phase detection error |
JP3695833B2 (ja) * | 1996-04-05 | 2005-09-14 | 株式会社ルネサステクノロジ | Pll回路 |
US5943382A (en) * | 1996-08-21 | 1999-08-24 | Neomagic Corp. | Dual-loop spread-spectrum clock generator with master PLL and slave voltage-modulation-locked loop |
US6115318A (en) * | 1996-12-03 | 2000-09-05 | Micron Technology, Inc. | Clock vernier adjustment |
US5978379A (en) | 1997-01-23 | 1999-11-02 | Gadzoox Networks, Inc. | Fiber channel learning bridge, learning half bridge, and protocol |
US6125157A (en) * | 1997-02-06 | 2000-09-26 | Rambus, Inc. | Delay-locked loop circuitry for clock delay adjustment |
US5920518A (en) * | 1997-02-11 | 1999-07-06 | Micron Technology, Inc. | Synchronous clock generator including delay-locked loop |
US5940608A (en) | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US5825209A (en) * | 1997-02-27 | 1998-10-20 | Rambus Inc. | Quadrature phase detector |
US5946244A (en) | 1997-03-05 | 1999-08-31 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US6369626B1 (en) | 1997-03-21 | 2002-04-09 | Rambus Inc. | Low pass filter for a delay locked loop circuit |
KR100215889B1 (ko) * | 1997-05-06 | 1999-08-16 | 구본준 | 클럭 동기 회로 |
US6100736A (en) * | 1997-06-05 | 2000-08-08 | Cirrus Logic, Inc | Frequency doubler using digital delay lock loop |
US6173432B1 (en) * | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
US6194929B1 (en) * | 1997-06-25 | 2001-02-27 | Sun Microsystems, Inc. | Delay locking using multiple control signals |
US5953284A (en) * | 1997-07-09 | 1999-09-14 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same |
JP3039464B2 (ja) * | 1997-07-31 | 2000-05-08 | 日本電気株式会社 | クロック発生回路 |
US6011732A (en) * | 1997-08-20 | 2000-01-04 | Micron Technology, Inc. | Synchronous clock generator including a compound delay-locked loop |
US5926047A (en) * | 1997-08-29 | 1999-07-20 | Micron Technology, Inc. | Synchronous clock generator including a delay-locked loop signal loss detector |
US5940609A (en) * | 1997-08-29 | 1999-08-17 | Micorn Technology, Inc. | Synchronous clock generator including a false lock detector |
US6101197A (en) * | 1997-09-18 | 2000-08-08 | Micron Technology, Inc. | Method and apparatus for adjusting the timing of signals over fine and coarse ranges |
US6513103B1 (en) | 1997-10-10 | 2003-01-28 | Rambus Inc. | Method and apparatus for adjusting the performance of a synchronous memory system |
US6133773A (en) * | 1997-10-10 | 2000-10-17 | Rambus Inc | Variable delay element |
KR100261964B1 (ko) | 1997-11-21 | 2000-07-15 | 김영환 | 전하펌프회로 |
US5907253A (en) * | 1997-11-24 | 1999-05-25 | National Semiconductor Corporation | Fractional-N phase-lock loop with delay line loop having self-calibrating fractional delay element |
SE511323C2 (sv) * | 1997-12-23 | 1999-09-13 | Ericsson Telefon Ab L M | Metod och anordning för fasreglering |
KR100511892B1 (ko) * | 1997-12-31 | 2005-11-25 | 매그나칩 반도체 유한회사 | 디엘엘장치 |
JP3678570B2 (ja) * | 1998-01-17 | 2005-08-03 | 日本電気株式会社 | 半導体集積回路 |
US6111445A (en) | 1998-01-30 | 2000-08-29 | Rambus Inc. | Phase interpolator with noise immunity |
US6047346A (en) * | 1998-02-02 | 2000-04-04 | Rambus Inc. | System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers |
US6014042A (en) * | 1998-02-19 | 2000-01-11 | Rambus Incorporated | Phase detector using switched capacitors |
US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
US6111446A (en) | 1998-03-20 | 2000-08-29 | Micron Technology, Inc. | Integrated circuit data latch driver circuit |
DE69914652T2 (de) * | 1998-03-27 | 2004-10-07 | Zarlink Semiconductor Ab Jaerf | Differentieller Impulsverstärker mit konstantem Tastverhältnis |
CA2233527C (en) | 1998-03-30 | 2002-01-22 | Mitel Semiconductor Ab | Pulse amplifier with low-duty cycle errors |
US6069506A (en) * | 1998-05-20 | 2000-05-30 | Micron Technology, Inc. | Method and apparatus for improving the performance of digital delay locked loop circuits |
US6016282A (en) * | 1998-05-28 | 2000-01-18 | Micron Technology, Inc. | Clock vernier adjustment |
US6094727A (en) | 1998-06-23 | 2000-07-25 | Micron Technology, Inc. | Method and apparatus for controlling the data rate of a clocking circuit |
US6084452A (en) * | 1998-06-30 | 2000-07-04 | Sun Microsystems, Inc | Clock duty cycle control technique |
KR100281898B1 (ko) | 1998-07-21 | 2001-02-15 | 윤종용 | 데이터의 듀티 사이클을 보정하는 듀티 사이클 보정회로 및 그방법 |
US6307427B1 (en) * | 1998-08-06 | 2001-10-23 | Fujitsu Limited | Filter characteristic regulating apparatus and regulating method therefor |
US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US6279090B1 (en) | 1998-09-03 | 2001-08-21 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device |
US6029250A (en) * | 1998-09-09 | 2000-02-22 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same |
US7430171B2 (en) | 1998-11-19 | 2008-09-30 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6415008B1 (en) * | 1998-12-15 | 2002-07-02 | BéCHADE ROLAND ALBERT | Digital signal multiplier |
US6072337A (en) | 1998-12-18 | 2000-06-06 | Cypress Semiconductor Corp. | Phase detector |
KR100295056B1 (ko) | 1999-01-27 | 2001-07-12 | 윤종용 | 지연동기루프 및 방법 |
US6470060B1 (en) | 1999-03-01 | 2002-10-22 | Micron Technology, Inc. | Method and apparatus for generating a phase dependent control signal |
CA2270516C (en) * | 1999-04-30 | 2009-11-17 | Mosaid Technologies Incorporated | Frequency-doubling delay locked loop |
US6928128B1 (en) | 1999-05-03 | 2005-08-09 | Rambus Inc. | Clock alignment circuit having a self regulating voltage supply |
US6421801B1 (en) | 1999-06-08 | 2002-07-16 | Intel Corporation | Testing IO timing in a delay locked system using separate transmit and receive loops |
US6381722B1 (en) | 1999-06-08 | 2002-04-30 | Intel Corporation | Method and apparatus for testing high speed input paths |
KR100340863B1 (ko) * | 1999-06-29 | 2002-06-15 | 박종섭 | 딜레이 록 루프 회로 |
US6839393B1 (en) * | 1999-07-14 | 2005-01-04 | Rambus Inc. | Apparatus and method for controlling a master/slave system via master device synchronization |
US6553529B1 (en) * | 1999-07-23 | 2003-04-22 | Teradyne, Inc. | Low cost timing system for highly accurate multi-modal semiconductor testing |
US6191613B1 (en) | 1999-07-29 | 2001-02-20 | Xilinx, Inc. | Programmable logic device with delay-locked loop |
US6643787B1 (en) * | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
US6646953B1 (en) * | 2000-07-06 | 2003-11-11 | Rambus Inc. | Single-clock, strobeless signaling system |
JP3671782B2 (ja) * | 1999-12-10 | 2005-07-13 | 富士通株式会社 | 信号位相調整回路 |
KR100345074B1 (ko) * | 1999-12-16 | 2002-07-20 | 주식회사 하이닉스반도체 | 딜레이 록 루프의 듀티 사이클 보정 회로 |
US6404660B1 (en) * | 1999-12-23 | 2002-06-11 | Rambus, Inc. | Semiconductor package with a controlled impedance bus and method of forming same |
IT1311463B1 (it) * | 1999-12-31 | 2002-03-12 | Cit Alcatel | Metodo di recupero del segnale d'orologio in un sistema ditelecomunicazioni e relativo circuito. |
KR100540176B1 (ko) * | 2000-01-24 | 2006-01-10 | 브이케이 주식회사 | 위상 동기 루프의 고속 저전압 전하펌프 |
US6987823B1 (en) * | 2000-02-07 | 2006-01-17 | Rambus Inc. | System and method for aligning internal transmit and receive clocks |
US6323706B1 (en) * | 2000-02-24 | 2001-11-27 | Rambus Inc. | Apparatus and method for edge based duty cycle conversion |
KR100640568B1 (ko) | 2000-03-16 | 2006-10-31 | 삼성전자주식회사 | 마스터-슬레이브 구조를 갖는 지연동기루프 회로 |
KR100366618B1 (ko) | 2000-03-31 | 2003-01-09 | 삼성전자 주식회사 | 클럭 신호의 듀티 사이클을 보정하는 지연 동기 루프 회로및 지연 동기 방법 |
KR100360403B1 (ko) | 2000-04-10 | 2002-11-13 | 삼성전자 주식회사 | 듀티 싸이클 보정회로 및 방법 |
JP4392678B2 (ja) | 2000-04-18 | 2010-01-06 | エルピーダメモリ株式会社 | Dll回路 |
US6654900B1 (en) * | 2000-04-19 | 2003-11-25 | Sigmatel, Inc. | Method and apparatus for producing multiple clock signals having controlled duty cycles by controlling clock multiplier delay elements |
JP3498069B2 (ja) * | 2000-04-27 | 2004-02-16 | Necエレクトロニクス株式会社 | クロック制御回路および方法 |
WO2001084724A2 (en) * | 2000-04-28 | 2001-11-08 | Broadcom Corporation | Methods and systems for adaptive receiver equalization |
US6384637B1 (en) | 2000-06-06 | 2002-05-07 | Rambus | Differential amplifier with selectable hysteresis and buffered filter |
FR2810009B1 (fr) * | 2000-06-09 | 2002-09-27 | Otico | Dispositif d'entrainement a chenille pour vehicule tout terrain |
DE10034899C1 (de) * | 2000-07-18 | 2002-07-04 | Infineon Technologies Ag | System zum Test schneller synchroner Halbleiterschaltungen |
US7245638B2 (en) | 2000-07-21 | 2007-07-17 | Broadcom Corporation | Methods and systems for DSP-based receivers |
US7564866B2 (en) * | 2000-07-21 | 2009-07-21 | Broadcom Corporation | Methods and systems for digitally processing optical data signals |
JP4454810B2 (ja) | 2000-08-04 | 2010-04-21 | Necエレクトロニクス株式会社 | デジタル位相制御方法及びデジタル位相制御回路 |
US6320438B1 (en) | 2000-08-17 | 2001-11-20 | Pericom Semiconductor Corp. | Duty-cycle correction driver with dual-filter feedback loop |
US6384652B1 (en) | 2000-08-17 | 2002-05-07 | Vanguard International Semiconductor Corporation | Clock duty cycle correction circuit |
US6373293B1 (en) | 2000-10-02 | 2002-04-16 | Rambus Inc. | Self-synchronized, multi-sample, quadrature phase detector |
KR100393206B1 (ko) * | 2000-10-23 | 2003-07-31 | 삼성전자주식회사 | 고주파 특성과 수율 향상을 위한 지연동기회로 |
US6621312B2 (en) * | 2000-11-13 | 2003-09-16 | Primarion, Inc. | High bandwidth multi-phase clock selector with continuous phase output |
DE10061167B4 (de) * | 2000-11-30 | 2005-12-15 | Infineon Technologies Ag | Verfahren zur Erzeugung von Taktsignalen in einem Datenverarbeitungssystem mit einer Vielzahl von Datenkanälen und Anordnung zur Durchführung des Verfahrens |
KR100384781B1 (ko) * | 2000-12-29 | 2003-05-22 | 주식회사 하이닉스반도체 | 듀티 사이클 보정 회로 |
US6832325B2 (en) * | 2000-12-29 | 2004-12-14 | Intel Corporation | Device on a source synchronous bus sending data in quadrature phase relationship and receiving data in phase with the bus clock signal |
KR20020064158A (ko) * | 2001-01-31 | 2002-08-07 | 로무 가부시키가이샤 | 샘플링 클록 발생기 회로 및 이를 이용한 데이터 수신기 |
US6889304B2 (en) * | 2001-02-28 | 2005-05-03 | Rambus Inc. | Memory device supporting a dynamically configurable core organization |
US6895522B2 (en) * | 2001-03-15 | 2005-05-17 | Micron Technology, Inc. | Method and apparatus for compensating duty cycle distortion in a data output signal from a memory device by delaying and distorting a reference clock |
US6750689B2 (en) * | 2001-03-29 | 2004-06-15 | Intel Corporation | Method and apparatus for correcting a clock duty cycle in a clock distribution network |
US7500075B1 (en) | 2001-04-17 | 2009-03-03 | Rambus Inc. | Mechanism for enabling full data bus utilization without increasing data granularity |
US6573779B2 (en) * | 2001-05-25 | 2003-06-03 | Rambus Inc. | Duty cycle integrator with tracking common mode feedback control |
US20020194518A1 (en) * | 2001-06-06 | 2002-12-19 | Chang Kun-Yung Ken | Apparatus and method for generating a skip signal |
US6801989B2 (en) | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
DE10132232C1 (de) * | 2001-06-29 | 2002-11-21 | Infineon Technologies Ag | Phasendetektorschaltung für einen Phasenregelkreis |
DE10132230C2 (de) * | 2001-06-29 | 2003-08-28 | Infineon Technologies Ag | Verfahren und Vorrichtung zur Erzeugung eines Taktausgangssignales |
US6825841B2 (en) * | 2001-09-07 | 2004-11-30 | Rambus Inc. | Granularity memory column access |
US6504438B1 (en) | 2001-09-17 | 2003-01-07 | Rambus, Inc. | Dual loop phase lock loops using dual voltage supply regulators |
KR100401522B1 (ko) | 2001-09-20 | 2003-10-17 | 주식회사 하이닉스반도체 | 듀티 보정 회로 |
EP1446910B1 (en) | 2001-10-22 | 2010-08-11 | Rambus Inc. | Phase adjustment apparatus and method for a memory device signaling system |
US6608530B1 (en) | 2001-12-14 | 2003-08-19 | Cypress Semiconductor Corp. | Enhanced ZDB feedback methodology utilizing binary weighted techniques |
US7058120B1 (en) * | 2002-01-18 | 2006-06-06 | Xilinx, Inc. | Integrated high-speed serial-to-parallel and parallel-to-serial transceiver |
EP1335520B1 (en) * | 2002-02-11 | 2018-05-30 | Semiconductor Components Industries, LLC | Multiplex bus system with duty cycle correction |
US6922091B2 (en) | 2002-09-03 | 2005-07-26 | Rambus Inc. | Locked loop circuit with clock hold function |
US6911853B2 (en) * | 2002-03-22 | 2005-06-28 | Rambus Inc. | Locked loop with dual rail regulation |
US7135903B2 (en) * | 2002-09-03 | 2006-11-14 | Rambus Inc. | Phase jumping locked loop circuit |
US6952123B2 (en) | 2002-03-22 | 2005-10-04 | Rambus Inc. | System with dual rail regulated locked loop |
US6759881B2 (en) * | 2002-03-22 | 2004-07-06 | Rambus Inc. | System with phase jumping locked loop circuit |
US6580304B1 (en) | 2002-03-28 | 2003-06-17 | M/A-Com, Inc. | Apparatus and method for introducing signal delay |
US6642760B1 (en) | 2002-03-29 | 2003-11-04 | Rambus, Inc. | Apparatus and method for a digital delay locked loop |
JP3762988B2 (ja) | 2002-07-09 | 2006-04-05 | 独立行政法人産業技術総合研究所 | クロック信号タイミング調整のための遅延回路を有するデジタル回路 |
US6944091B2 (en) * | 2002-07-10 | 2005-09-13 | Samsung Electronics Co., Ltd. | Latency control circuit and method of latency control |
US7298667B2 (en) * | 2002-07-10 | 2007-11-20 | Samsung Electronic Co., Ltd. | Latency control circuit and method of latency control |
KR100486250B1 (ko) * | 2002-07-10 | 2005-05-03 | 삼성전자주식회사 | 고주파수 동작을 위한 동기식 반도체 장치의 레이턴시제어 회로 및 그 방법 |
US6650594B1 (en) | 2002-07-12 | 2003-11-18 | Samsung Electronics Co., Ltd. | Device and method for selecting power down exit |
US6897699B1 (en) * | 2002-07-19 | 2005-05-24 | Rambus Inc. | Clock distribution network with process, supply-voltage, and temperature compensation |
US6981185B1 (en) * | 2002-08-09 | 2005-12-27 | Adaptec, Inc. | Methods and apparatus to correct duty cycle |
US6940328B2 (en) | 2002-08-28 | 2005-09-06 | Micron Technology, Inc. | Methods and apparatus for duty cycle control |
US6856558B1 (en) | 2002-09-20 | 2005-02-15 | Integrated Device Technology, Inc. | Integrated circuit devices having high precision digital delay lines therein |
KR100486268B1 (ko) * | 2002-10-05 | 2005-05-03 | 삼성전자주식회사 | 내부에서 자체적으로 듀티싸이클 보정을 수행하는지연동기루프 회로 및 이의 듀티싸이클 보정방법 |
KR20040034985A (ko) * | 2002-10-18 | 2004-04-29 | 엘지전자 주식회사 | 클럭신호 생성회로 |
KR100499305B1 (ko) * | 2002-10-18 | 2005-07-04 | 엘지전자 주식회사 | 이중 지연루프를 이용한 클럭신호의 듀티 팩터 보상회로 |
KR100490655B1 (ko) * | 2002-10-30 | 2005-05-24 | 주식회사 하이닉스반도체 | 듀티 사이클 보정 회로 및 그를 구비한 지연고정루프 |
KR100532415B1 (ko) * | 2003-01-10 | 2005-12-02 | 삼성전자주식회사 | 돌발지터 정보를 차단할 수 있는 동기루프 회로 및 이의돌발지터 정보 차단방법 |
KR100510515B1 (ko) * | 2003-01-17 | 2005-08-26 | 삼성전자주식회사 | 공정의 변화에 따라서 클럭신호의 듀티 사이클을 보정하는듀티 사이클 보정회로를 구비하는 반도체 장치 |
JP4121863B2 (ja) * | 2003-01-29 | 2008-07-23 | 富士通株式会社 | タイミング信号発生回路および受信回路 |
US20040169539A1 (en) * | 2003-02-28 | 2004-09-02 | Gauthier Claude R. | Miller effect compensation technique for DLL phase interpolator design |
US20040222832A1 (en) * | 2003-05-09 | 2004-11-11 | Chaiyuth Chansungsan | Interpolator circuit |
KR100543910B1 (ko) * | 2003-05-30 | 2006-01-23 | 주식회사 하이닉스반도체 | 디지털 지연고정루프 및 그의 제어 방법 |
US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
US7477716B2 (en) * | 2003-06-25 | 2009-01-13 | Mosaid Technologies, Inc. | Start up circuit for delay locked loop |
KR100529037B1 (ko) * | 2003-07-29 | 2005-11-17 | 주식회사 하이닉스반도체 | 개선된 지터 특성을 갖는 지연고정루프 및 그의 클럭 지연보상 방법 |
KR100546368B1 (ko) * | 2003-08-22 | 2006-01-26 | 삼성전자주식회사 | 센터링 에러를 일으키는 클럭 스큐를 자체적으로 보상하는메모리 장치 및 그 클럭 스큐 보상 방법 |
US6977539B1 (en) | 2003-08-26 | 2005-12-20 | Integrated Device Technology, Inc. | Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skews |
US7196562B1 (en) | 2003-08-26 | 2007-03-27 | Integrated Device Technology, Inc. | Programmable clock drivers that support CRC error checking of configuration data during program restore operations |
US7151398B2 (en) * | 2003-08-26 | 2006-12-19 | Integrated Device Technology, Inc. | Clock signal generators having programmable full-period clock skew control |
US7046093B1 (en) | 2003-08-27 | 2006-05-16 | Intergrated Device Technology, Inc. | Dynamic phase-locked loop circuits and methods of operation thereof |
US6960952B2 (en) * | 2003-09-11 | 2005-11-01 | Rambus, Inc. | Configuring and selecting a duty cycle for an output driver |
US6867627B1 (en) | 2003-09-16 | 2005-03-15 | Integrated Device Technology, Inc. | Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics |
US7046058B1 (en) | 2003-09-24 | 2006-05-16 | Integrated Device Technology, Ltd. | Delayed-locked loop with fine and coarse control using cascaded phase interpolator and variable delay circuit |
US7234070B2 (en) * | 2003-10-27 | 2007-06-19 | Micron Technology, Inc. | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
KR100605604B1 (ko) * | 2003-10-29 | 2006-07-28 | 주식회사 하이닉스반도체 | 지연 고정 루프 및 그 제어 방법 |
KR100578232B1 (ko) * | 2003-10-30 | 2006-05-12 | 주식회사 하이닉스반도체 | 지연 고정 루프 |
KR100542696B1 (ko) * | 2003-11-13 | 2006-01-11 | 주식회사 하이닉스반도체 | 반도체 장치의 리페어 퓨즈 박스 |
KR100514414B1 (ko) * | 2003-11-20 | 2005-09-09 | 주식회사 하이닉스반도체 | 지연 동기 루프 |
KR100554981B1 (ko) * | 2003-11-20 | 2006-03-03 | 주식회사 하이닉스반도체 | 지연 고정 루프 |
US6943608B2 (en) * | 2003-12-01 | 2005-09-13 | International Business Machines Corporation | Wide frequency range voltage-controlled oscillators (VCO) |
KR100553833B1 (ko) * | 2003-12-24 | 2006-02-24 | 삼성전자주식회사 | 지연동기회로의 인버젼 제어회로 및 방법과, 이를 이용한지연동기회로 및 반도체 메모리 장치 |
US7109760B1 (en) | 2004-01-05 | 2006-09-19 | Integrated Device Technology, Inc. | Delay-locked loop (DLL) integrated circuits that support efficient phase locking of clock signals having non-unity duty cycles |
US7279938B1 (en) | 2004-01-05 | 2007-10-09 | Integrated Device Technology, Inc. | Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein |
US6995622B2 (en) | 2004-01-09 | 2006-02-07 | Robert Bosh Gmbh | Frequency and/or phase compensated microelectromechanical oscillator |
KR100673885B1 (ko) * | 2004-04-27 | 2007-01-26 | 주식회사 하이닉스반도체 | 반도체 기억 소자의 듀티 싸이클 교정 장치 및 그 방법 |
US7894563B2 (en) * | 2004-05-27 | 2011-02-22 | Virtensys Limited | Clock recovery circuit and a method of generating a recovered clock signal |
US8190808B2 (en) * | 2004-08-17 | 2012-05-29 | Rambus Inc. | Memory device having staggered memory operations |
US20060062340A1 (en) * | 2004-09-20 | 2006-03-23 | Intersil Americas, Inc. | Phase adjuster |
US7280428B2 (en) | 2004-09-30 | 2007-10-09 | Rambus Inc. | Multi-column addressing mode memory system including an integrated circuit memory device |
US7254075B2 (en) * | 2004-09-30 | 2007-08-07 | Rambus Inc. | Integrated circuit memory system having dynamic memory bank count and page size |
US7310704B1 (en) * | 2004-11-02 | 2007-12-18 | Symantec Operating Corporation | System and method for performing online backup and restore of volume configuration information |
US8595459B2 (en) | 2004-11-29 | 2013-11-26 | Rambus Inc. | Micro-threaded memory |
US7230465B2 (en) * | 2005-01-10 | 2007-06-12 | Infineon Technologies Ag | Duty cycle corrector |
US7221204B2 (en) * | 2005-02-01 | 2007-05-22 | Infineon Technologies Ag | Duty cycle corrector |
US7190201B2 (en) * | 2005-02-03 | 2007-03-13 | Mosaid Technologies, Inc. | Method and apparatus for initializing a delay locked loop |
KR100713082B1 (ko) * | 2005-03-02 | 2007-05-02 | 주식회사 하이닉스반도체 | 클럭의 듀티 비율을 조정할 수 있는 지연 고정 루프 |
US20060248305A1 (en) * | 2005-04-13 | 2006-11-02 | Wayne Fang | Memory device having width-dependent output latency |
US7170323B1 (en) * | 2005-05-09 | 2007-01-30 | Pixelworks, Inc. | Delay locked loop harmonic detector and associated method |
US7332950B2 (en) * | 2005-06-14 | 2008-02-19 | Micron Technology, Inc. | DLL measure initialization circuit for high frequency operation |
US7330059B2 (en) * | 2005-08-24 | 2008-02-12 | Micrel, Incorporated | In-loop duty corrector delay-locked loop for multiphase clock generation |
US7250801B2 (en) * | 2005-08-25 | 2007-07-31 | Infineon Technologies Ag | Differential duty cycle restoration |
US7403055B2 (en) * | 2005-08-31 | 2008-07-22 | Infineon Technologies Ag | Duty cycle detector with first and second oscillating signals |
US7920665B1 (en) | 2005-09-28 | 2011-04-05 | Cypress Semiconductor Corporation | Symmetrical range controller circuit and method |
JP2007097019A (ja) * | 2005-09-30 | 2007-04-12 | Sanyo Electric Co Ltd | 遅延回路及びそれを用いた映像信号処理回路 |
JP3968450B2 (ja) * | 2005-09-30 | 2007-08-29 | ザインエレクトロニクス株式会社 | ステレオ変調器およびそれを用いたfmステレオ変調器 |
US7227809B2 (en) * | 2005-10-14 | 2007-06-05 | Micron Technology, Inc. | Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration |
US7423465B2 (en) * | 2006-01-27 | 2008-09-09 | Micron Technology, Inc. | Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit |
US8073890B2 (en) * | 2006-02-22 | 2011-12-06 | Micron Technology, Inc. | Continuous high-frequency event filter |
US7728675B1 (en) | 2006-03-31 | 2010-06-01 | Cypress Semiconductor Corporation | Fast lock circuit for a phase lock loop |
US7301380B2 (en) * | 2006-04-12 | 2007-11-27 | International Business Machines Corporation | Delay locked loop having charge pump gain independent of operating frequency |
US20070260841A1 (en) | 2006-05-02 | 2007-11-08 | Hampel Craig E | Memory module with reduced access granularity |
KR100809692B1 (ko) * | 2006-08-01 | 2008-03-06 | 삼성전자주식회사 | 작은 지터를 갖는 지연동기 루프 회로 및 이의 지터감소방법 |
US7323918B1 (en) | 2006-08-08 | 2008-01-29 | Micrel, Incorporated | Mutual-interpolating delay-locked loop for high-frequency multiphase clock generation |
CN101145779B (zh) * | 2006-09-12 | 2010-07-07 | 盛群半导体股份有限公司 | 相角产生器 |
JP4908161B2 (ja) * | 2006-11-16 | 2012-04-04 | 株式会社東芝 | 電源回路および半導体記憶装置 |
US7558980B2 (en) * | 2007-01-04 | 2009-07-07 | Montage Technology Group Limited | Systems and methods for the distribution of differential clock signals to a plurality of low impedance receivers |
KR100857436B1 (ko) * | 2007-01-24 | 2008-09-10 | 주식회사 하이닉스반도체 | Dll 회로 및 그 제어 방법 |
US7936087B2 (en) * | 2007-03-12 | 2011-05-03 | System General Corp. | Switching controller for parallel power converters |
US7817750B2 (en) * | 2007-05-21 | 2010-10-19 | Seiko Epson Corporation | Radio receiver including a delay-locked loop (DLL) for phase adjustment |
US7831416B2 (en) * | 2007-07-17 | 2010-11-09 | Caterpillar Inc | Probabilistic modeling system for product design |
US8169241B2 (en) | 2008-01-15 | 2012-05-01 | Atmel Rousset S.A.S. | Proportional phase comparator and method for phase-aligning digital signals |
US8161313B2 (en) * | 2008-09-30 | 2012-04-17 | Mosaid Technologies Incorporated | Serial-connected memory system with duty cycle correction |
US8181056B2 (en) * | 2008-09-30 | 2012-05-15 | Mosaid Technologies Incorporated | Serial-connected memory system with output delay adjustment |
KR20100037427A (ko) * | 2008-10-01 | 2010-04-09 | 삼성전자주식회사 | Ac 커플링 위상 보간기 및 이 장치를 이용하는 지연 고정루프 |
KR101564282B1 (ko) * | 2008-10-22 | 2015-10-29 | 삼성전자주식회사 | 듀티 보정회로 |
US7782104B2 (en) * | 2008-12-23 | 2010-08-24 | Intel Corporation | Delay element array for time-to-digital converters |
WO2011008356A2 (en) * | 2009-06-30 | 2011-01-20 | Rambus Inc. | Techniques for adjusting clock signals to compensate for noise |
US8217696B2 (en) * | 2009-12-17 | 2012-07-10 | Intel Corporation | Adaptive digital phase locked loop |
CN102771077B (zh) * | 2010-02-17 | 2014-12-31 | 模式转换系统有限公司 | 数字时钟再生器 |
US8461889B2 (en) * | 2010-04-09 | 2013-06-11 | Micron Technology, Inc. | Clock signal generators having a reduced power feedback clock path and methods for generating clocks |
KR101710669B1 (ko) | 2010-09-15 | 2017-02-27 | 삼성전자주식회사 | 클록 지연 회로, 지연 동기 회로, 및 그것을 포함하는 반도체 메모리 장치 |
KR101095010B1 (ko) | 2010-09-30 | 2011-12-20 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 dll 회로 |
US8729941B2 (en) | 2010-10-06 | 2014-05-20 | Micron Technology, Inc. | Differential amplifiers, clock generator circuits, delay lines and methods |
US9268719B2 (en) | 2011-08-05 | 2016-02-23 | Rambus Inc. | Memory signal buffers and modules supporting variable access granularity |
TWI448081B (zh) * | 2012-01-20 | 2014-08-01 | Nat Univ Chung Cheng | All-digital clock correction circuit and method thereof |
US8742807B1 (en) * | 2012-05-24 | 2014-06-03 | Ambarella, Inc. | Low supply voltage analog phase interpolator |
JP5900171B2 (ja) * | 2012-06-07 | 2016-04-06 | 富士通株式会社 | デューティ比補正回路、ダブルエッジ装置及びデューティ比補正方法 |
CN103795375B (zh) * | 2012-10-30 | 2016-12-21 | 瑞昱半导体股份有限公司 | 占空比调整电路及其方法 |
US9106230B1 (en) * | 2013-03-14 | 2015-08-11 | Altera Corporation | Input-output circuitry for integrated circuits |
US9453906B2 (en) | 2014-07-31 | 2016-09-27 | North Carolina State University | Phase calibration circuit and method for multi-channel radar receiver |
JP6445286B2 (ja) * | 2014-09-08 | 2018-12-26 | 旭化成エレクトロニクス株式会社 | 位相検出器、位相調整回路、受信器及び送信器 |
US9369263B1 (en) | 2015-06-30 | 2016-06-14 | International Business Machines Corporation | Calibration of sampling phase and aperature errors in multi-phase sampling systems |
CN106452393A (zh) * | 2015-08-11 | 2017-02-22 | 纽艾吉科技有限公司 | 数位式自适应去抖动装置及其方法 |
CN105061729B (zh) * | 2015-08-18 | 2017-07-11 | 天津大学 | 可室温固化水性环氧树脂的水性超支化聚合物固化剂 |
US10425091B2 (en) * | 2017-10-31 | 2019-09-24 | Texas Instruments Incorporated | Fractional clock generator |
US10707879B2 (en) * | 2018-04-13 | 2020-07-07 | KaiKuTek Inc. | Frequency-modulated continuous-wave radar system and frequency tracking method for calibrating frequency gains of a radio frequency signal to approach wideband flatness frequency responses |
EP3648348B1 (en) | 2018-10-29 | 2022-09-28 | NXP USA, Inc. | Duty cycle monitor circuit and method for duty cycle monitoring |
US11171584B1 (en) * | 2020-05-11 | 2021-11-09 | Pix Art Imaging Inc. | Interpolation circuit and motor driving circuit |
CN117526932B (zh) * | 2024-01-08 | 2024-05-10 | 芯耀辉科技有限公司 | 一种时钟信号生成方法及装置 |
Family Cites Families (114)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3296517A (en) * | 1963-03-15 | 1967-01-03 | Claude C Routh | Passive broadband frequency multiplier |
US3546604A (en) * | 1964-06-09 | 1970-12-08 | Marathon Oil Co | Phase shifters |
FR1508340A (fr) * | 1966-11-24 | 1968-01-05 | Csf | Générateur de bandes latérales |
GB1335211A (en) * | 1970-01-14 | 1973-10-24 | Plessey Co Ltd | Demodulation systems |
US3617855A (en) * | 1970-04-24 | 1971-11-02 | Nippon Oceanics Inst Ltd | Phase-detecting circuits |
US3771063A (en) * | 1972-03-13 | 1973-11-06 | Calnor El Paso Inc | Bi-polar phase detector |
US3825768A (en) * | 1973-02-15 | 1974-07-23 | Eaton Corp | Phase sequence and power loss detector |
US3863080A (en) * | 1973-10-18 | 1975-01-28 | Rca Corp | Current output frequency and phase comparator |
US3911368A (en) * | 1974-06-20 | 1975-10-07 | Tarczy Hornoch Zoltan | Phase interpolating apparatus and method |
JPS5141945A (en) * | 1974-10-07 | 1976-04-08 | Sony Corp | Isohenchoshingono isoatsushukuhoho |
US3965433A (en) * | 1975-03-27 | 1976-06-22 | Bell Telephone Laboratories, Incorporated | Phase equalizer useable in a LIND amplifier |
US3982190A (en) * | 1975-07-31 | 1976-09-21 | Rockwell International Corporation | Phaselock circuitry with lock indication |
US3997772A (en) * | 1975-09-05 | 1976-12-14 | Bell Telephone Laboratories, Incorporated | Digital phase shifter |
JPS5953515B2 (ja) * | 1976-10-25 | 1984-12-25 | 株式会社日立製作所 | 時間差検出回路 |
US4110641A (en) * | 1977-06-27 | 1978-08-29 | Honeywell Inc. | CMOS voltage comparator with internal hysteresis |
NL185379C (nl) * | 1977-07-22 | 1990-03-16 | Mitsubishi Electric Corp | Geestopheffingsschakeling voor televisiesignalen. |
US4156851A (en) * | 1977-10-25 | 1979-05-29 | Winters Paul N | Constant-phase delay network |
US4151463A (en) * | 1978-02-02 | 1979-04-24 | Bell Telephone Laboratories, Incorporated | Phase locked loop indicator |
US4291274A (en) * | 1978-11-22 | 1981-09-22 | Tokyo Shibaura Denki Kabushiki Kaisha | Phase detector circuit using logic gates |
US4249095A (en) * | 1979-02-26 | 1981-02-03 | Rca Corporation | Comparator, sense amplifier |
US4283682A (en) * | 1979-04-06 | 1981-08-11 | Ricoh Company, Ltd. | Erasure zone decision feedback phase lock loop for carrier recovery in data modems |
JPS56128083A (en) * | 1980-03-12 | 1981-10-07 | Hitachi Ltd | Phase detection circuit |
JPS5772429A (en) * | 1980-10-22 | 1982-05-06 | Toshiba Corp | Semiconductor integrated circuit device |
US4383216A (en) * | 1981-01-29 | 1983-05-10 | International Business Machines Corporation | AC Measurement means for use with power control means for eliminating circuit to circuit delay differences |
US4373204A (en) * | 1981-02-02 | 1983-02-08 | Bell Telephone Laboratories, Incorporated | Phase locked loop timing recovery circuit |
US4394587A (en) * | 1981-05-27 | 1983-07-19 | Motorola, Inc. | CMOS Differential comparator with hysteresis |
JPS5860888A (ja) * | 1981-10-08 | 1983-04-11 | Toshiba Corp | 色分離回路 |
JPS5892963A (ja) * | 1981-11-30 | 1983-06-02 | Anritsu Corp | 位相検出器 |
JPS58197920A (ja) * | 1982-05-13 | 1983-11-17 | Toshiba Corp | 論理回路 |
US4506175A (en) * | 1982-08-18 | 1985-03-19 | Rca Corporation | Digital phase comparator circuit producing sign and magnitude outputs |
US4494021A (en) * | 1982-08-30 | 1985-01-15 | Xerox Corporation | Self-calibrated clock and timing signal generator for MOS/VLSI circuitry |
US4789799A (en) * | 1983-04-05 | 1988-12-06 | Tektronix, Inc. | Limiting circuit |
JPS59218036A (ja) | 1983-05-25 | 1984-12-08 | Sony Corp | 位相比較回路 |
US4547685A (en) * | 1983-10-21 | 1985-10-15 | Advanced Micro Devices, Inc. | Sense amplifier circuit for semiconductor memories |
KR890003415B1 (ko) * | 1983-12-17 | 1989-09-20 | 가부시끼 가이샤 도오시바 | 반도체 집적회로 |
JPS60132412A (ja) * | 1983-12-21 | 1985-07-15 | Toshiba Corp | 可変移相回路 |
JPS60143017A (ja) * | 1983-12-29 | 1985-07-29 | Advantest Corp | クロツク同期式論理装置 |
JPS60170075A (ja) * | 1984-02-14 | 1985-09-03 | Sony Corp | デイジタルビデオ信号処理装置 |
US4641048A (en) * | 1984-08-24 | 1987-02-03 | Tektronix, Inc. | Digital integrated circuit propagation delay time controller |
US4623805A (en) * | 1984-08-29 | 1986-11-18 | Burroughs Corporation | Automatic signal delay adjustment apparatus |
US4721904A (en) * | 1984-12-25 | 1988-01-26 | Victor Company Of Japan, Ltd. | Digital phase difference detecting circuit |
US4644196A (en) * | 1985-01-28 | 1987-02-17 | Motorola, Inc. | Tri-state differential amplifier |
FR2577081B1 (fr) * | 1985-02-01 | 1991-01-11 | Enertec | Procede et dispositif de calage en phase rapide d'un signal d'horloge |
JPS61224607A (ja) * | 1985-03-29 | 1986-10-06 | Toshiba Corp | 自動利得制御用検波回路 |
US4638190A (en) * | 1985-05-20 | 1987-01-20 | General Electric Company | Digitally controlled wideband phase shifter |
JPS628614A (ja) * | 1985-07-05 | 1987-01-16 | Nec Corp | 入力インバ−タ回路 |
JPS62136915A (ja) * | 1985-12-10 | 1987-06-19 | Victor Co Of Japan Ltd | パルス移相回路 |
JPS62205597A (ja) * | 1986-03-05 | 1987-09-10 | Toshiba Corp | 半導体感知増幅回路 |
US4806888A (en) * | 1986-04-14 | 1989-02-21 | Harris Corp. | Monolithic vector modulator/complex weight using all-pass network |
US4691124A (en) * | 1986-05-16 | 1987-09-01 | Motorola, Inc. | Self-compensating, maximum speed integrated circuit |
JP2718664B2 (ja) * | 1986-05-23 | 1998-02-25 | 株式会社日立製作所 | 位相同期検出回路 |
GB2193406B (en) * | 1986-08-02 | 1990-04-25 | Marconi Instruments Ltd | Phase detector |
ES2021268B3 (es) * | 1986-10-21 | 1991-11-01 | Ibm | Procedimiento para la regulacion digital del declive de flancos de las señales de salida de amplificadores de rendimiento de los chips semiconductores de ordenadores, con conexiones altamente integradas. |
US4739194A (en) * | 1986-11-25 | 1988-04-19 | Tektronix, Inc. | Supergate for high speed transmission of signals |
JP2608555B2 (ja) * | 1987-03-19 | 1997-05-07 | 富士通株式会社 | 位相比較回路 |
US4813005A (en) * | 1987-06-24 | 1989-03-14 | Hewlett-Packard Company | Device for synchronizing the output pulses of a circuit with an input clock |
US4818901A (en) * | 1987-07-20 | 1989-04-04 | Harris Corporation | Controlled switching CMOS output buffer |
CA1289199C (en) * | 1987-09-19 | 1991-09-17 | Masaaki Kawai | Phase shift circuit |
US4814648A (en) * | 1987-09-24 | 1989-03-21 | Texas Instruments Incorporated | Low 1/f noise amplifier for CCD imagers |
US4845675A (en) * | 1988-01-22 | 1989-07-04 | Texas Instruments Incorporated | High-speed data latch with zero data hold time |
JPH01231430A (ja) * | 1988-03-10 | 1989-09-14 | Nec Corp | Pllロック検出回路 |
US4866397A (en) * | 1988-04-07 | 1989-09-12 | Exar Corporation | Wideband 0-90 degrees adjustable phase shifter |
JP2571096B2 (ja) * | 1988-04-18 | 1997-01-16 | ファナック株式会社 | エンコーダ |
US4870303A (en) * | 1988-06-03 | 1989-09-26 | Motorola, Inc. | Phase detector |
US4937476A (en) * | 1988-06-16 | 1990-06-26 | Intel Corporation | Self-biased, high-gain differential amplifier with feedback |
JP2642421B2 (ja) * | 1988-06-28 | 1997-08-20 | 富士通株式会社 | デジタル位相差検出回路及び位相差検出方法 |
EP0349715B1 (de) * | 1988-07-06 | 1994-01-05 | ANT Nachrichtentechnik GmbH | Verfahren und Schaltungsanordnung zur Erzeugung eines phasenverschobenen Taktsignales |
JPH0727717B2 (ja) * | 1988-07-13 | 1995-03-29 | 株式会社東芝 | センス回路 |
JPH0287810A (ja) * | 1988-09-26 | 1990-03-28 | Nec Corp | 差動増幅回路 |
WO1990004286A1 (en) | 1988-10-11 | 1990-04-19 | Oki Electric Industry Co., Ltd. | Differential amplifier circuit |
US4994773A (en) * | 1988-10-13 | 1991-02-19 | Chen Tzu H | Digitally controlled monolithic active phase shifter apparatus having a cascode configuration |
JPH0722380B2 (ja) * | 1988-10-27 | 1995-03-08 | 富士通株式会社 | 映像信号用位相ロツク回路 |
US5253187A (en) * | 1988-11-11 | 1993-10-12 | Canon Kabushiki Kaisha | Coordinate input apparatus |
US4893094A (en) * | 1989-03-13 | 1990-01-09 | Motorola, Inc. | Frequency synthesizer with control of start-up battery saving operations |
JPH0773255B2 (ja) * | 1989-03-17 | 1995-08-02 | 富士通株式会社 | ビット照合制御方式 |
JPH0770935B2 (ja) * | 1989-10-06 | 1995-07-31 | 株式会社東芝 | 差動電流増幅回路 |
JPH03123210A (ja) * | 1989-10-06 | 1991-05-27 | Alps Electric Co Ltd | 2段縦続差動増幅器 |
US4958133A (en) * | 1989-11-13 | 1990-09-18 | Intel Corporation | CMOS complementary self-biased differential amplifier with rail-to-rail common-mode input-voltage range |
IT1236879B (it) * | 1989-11-22 | 1993-04-26 | Sgs Thomson Microelectronics | Circuito elettronico comparatore |
JP2999508B2 (ja) * | 1990-04-18 | 2000-01-17 | パイオニア株式会社 | 時間軸誤差信号発生装置 |
EP0595787B1 (en) * | 1990-05-21 | 1998-08-05 | Nec Corporation | Phase-locked loop circuit |
US5281865A (en) * | 1990-11-28 | 1994-01-25 | Hitachi, Ltd. | Flip-flop circuit |
US5148113A (en) * | 1990-11-29 | 1992-09-15 | Northern Telecom Ltd. | Clock phase alignment |
JPH04214297A (ja) * | 1990-12-13 | 1992-08-05 | Mitsubishi Electric Corp | 増幅回路 |
JPH04220094A (ja) * | 1990-12-19 | 1992-08-11 | Sony Corp | バースト位相検出回路 |
US5223755A (en) * | 1990-12-26 | 1993-06-29 | Xerox Corporation | Extended frequency range variable delay locked loop for clock synchronization |
US5121010A (en) * | 1991-02-14 | 1992-06-09 | Motorola, Inc. | Phase detector with deadzone window |
US5079519A (en) * | 1991-02-14 | 1992-01-07 | Notorola, Inc. | Digital phase lock loop for a gate array |
US5128554A (en) * | 1991-02-14 | 1992-07-07 | Motorola, Inc. | Opposite phase clock generator circuit |
US5095233A (en) * | 1991-02-14 | 1992-03-10 | Motorola, Inc. | Digital delay line with inverter tap resolution |
US5132567A (en) * | 1991-04-18 | 1992-07-21 | International Business Machines Corporation | Low threshold BiCMOS circuit |
US5175879A (en) * | 1991-04-25 | 1992-12-29 | Motorola, Inc. | Linear amplifier with feedback path and phase error compensation |
KR940001816B1 (ko) * | 1991-07-26 | 1994-03-09 | 삼성전자 주식회사 | 슬루우레이트 스피드엎 회로 |
US5182476A (en) * | 1991-07-29 | 1993-01-26 | Motorola, Inc. | Offset cancellation circuit and method of reducing pulse pairing |
US5126693A (en) * | 1991-09-09 | 1992-06-30 | Motorola, Inc. | Circuit and method of reducing phase jitter in a phase lock loop |
US5157276A (en) * | 1991-09-26 | 1992-10-20 | Tektronix, Inc. | Low jitter clock phase adjust system |
US5179303A (en) * | 1991-10-24 | 1993-01-12 | Northern Telecom Limited | Signal delay apparatus employing a phase locked loop |
DE4139117C1 (ja) | 1991-11-28 | 1993-06-09 | Texas Instruments Deutschland Gmbh, 8050 Freising, De | |
JP2594483B2 (ja) * | 1991-12-10 | 1997-03-26 | 新日本製鐵株式会社 | 自動追尾式衛星放送受信アンテナ装置 |
US5448200A (en) | 1991-12-18 | 1995-09-05 | At&T Corp. | Differential comparator with differential threshold for local area networks or the like |
US5187448A (en) * | 1992-02-03 | 1993-02-16 | Motorola, Inc. | Differential amplifier with common-mode stability enhancement |
US5309047A (en) * | 1992-02-21 | 1994-05-03 | Simtek Corporation | Differential sense amplifier with cross connected reference circuits |
US5289054A (en) * | 1992-03-24 | 1994-02-22 | Intel Corporation | Fast electronic comparator |
JPH05312850A (ja) | 1992-05-12 | 1993-11-26 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
US5317202A (en) | 1992-05-28 | 1994-05-31 | Intel Corporation | Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle |
US5317288A (en) * | 1992-12-15 | 1994-05-31 | Space Systems/Loral, Inc. | Continuously variable electronically controlled phase shift circuit |
US5394024A (en) | 1992-12-17 | 1995-02-28 | Vlsi Technology, Inc. | Circuit for eliminating off-chip to on-chip clock skew |
US5488321A (en) | 1993-04-07 | 1996-01-30 | Rambus, Inc. | Static high speed comparator |
US5432480A (en) | 1993-04-08 | 1995-07-11 | Northern Telecom Limited | Phase alignment methods and apparatus |
JP2740113B2 (ja) | 1993-06-30 | 1998-04-15 | 株式会社東芝 | クロマノイズリダクション装置 |
US5334953A (en) | 1993-07-22 | 1994-08-02 | Motorola, Inc. | Charge pump bias control in a phase lock loop |
US5351000A (en) | 1993-07-30 | 1994-09-27 | Hughes Aircraft Company | Method of cancelling offset errors in phase detectors |
US5422918A (en) | 1993-12-09 | 1995-06-06 | Unisys Corporation | Clock phase detecting system for detecting the phase difference between two clock phases regardless of which of the two clock phases leads the other |
US5422529A (en) | 1993-12-10 | 1995-06-06 | Rambus, Inc. | Differential charge pump circuit with high differential and low common mode impedance |
-
1995
- 1995-02-09 WO PCT/US1995/001726 patent/WO1995022206A1/en active Application Filing
- 1995-02-09 KR KR1019960704469A patent/KR100393317B1/ko not_active IP Right Cessation
- 1995-02-09 JP JP52136695A patent/JP3754070B2/ja not_active Expired - Fee Related
- 1995-02-09 AU AU18418/95A patent/AU1841895A/en not_active Abandoned
- 1995-08-21 US US08/512,597 patent/US5614855A/en not_active Expired - Fee Related
-
2005
- 2005-09-01 JP JP2005253696A patent/JP4188349B2/ja not_active Expired - Fee Related
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7671646B2 (en) | 2006-04-24 | 2010-03-02 | Hynix Semiconductor, Inc. | Delay locked loop |
US7548100B2 (en) | 2006-04-24 | 2009-06-16 | Hynix Semiconductor Inc. | Delay locked loop |
US7593285B2 (en) | 2006-08-31 | 2009-09-22 | Hynix Semiconductor, Inc. | Semiconductor memory device with delay locked loop |
US7633832B2 (en) | 2006-12-22 | 2009-12-15 | Hynix Semiconductor Inc. | Circuit for outputting data of semiconductor memory apparatus |
US7843743B2 (en) | 2007-04-13 | 2010-11-30 | Hynix Semiconductor Inc. | Data output circuit for semiconductor memory apparatus |
US7652514B2 (en) | 2007-06-11 | 2010-01-26 | Hynix Semiconductor Inc. | Internal clock driver circuit |
US7990197B2 (en) | 2007-06-11 | 2011-08-02 | Hynix Semiconductor Inc. | Internal clock driver circuit |
KR100910785B1 (ko) | 2007-09-27 | 2009-08-04 | 인하대학교 산학협력단 | Dll 기반의 듀티사이클 보정회로 |
US8120403B2 (en) | 2008-05-21 | 2012-02-21 | Elpida Memory, Inc. | Duty detection circuit |
US7911251B2 (en) | 2009-05-11 | 2011-03-22 | Hynix Semiconductor Inc. | Clock signal generating circuit and semiconductor memory apparatus including the same |
US8242821B2 (en) | 2009-06-17 | 2012-08-14 | Samsung Electronics Co., Ltd. | Delay-locked loop for correcting duty ratio of input clock signal and output clock signal and electronic device including the same |
CN102055436A (zh) * | 2009-10-30 | 2011-05-11 | 海力士半导体有限公司 | 用于校正时钟信号的占空比的装置和方法 |
US8154331B2 (en) | 2009-11-30 | 2012-04-10 | Hynix Semiconductor Inc. | Duty correction circuit |
US8222938B2 (en) | 2010-02-24 | 2012-07-17 | Hynix Semiconductor Inc. | Delay locked loop semiconductor apparatus that models a delay of an internal clock path |
US8373480B2 (en) | 2010-02-24 | 2013-02-12 | Hynix Semiconductor Inc. | Delay locked loop semiconductor apparatus that models a delay of an internal clock path |
US8487671B2 (en) | 2010-03-16 | 2013-07-16 | Elpida Memory, Inc. | Internal-clock adjusting circuit |
Also Published As
Publication number | Publication date |
---|---|
WO1995022206A1 (en) | 1995-08-17 |
JP4188349B2 (ja) | 2008-11-26 |
KR970701453A (ko) | 1997-03-17 |
KR100393317B1 (ko) | 2003-10-23 |
JP3754070B2 (ja) | 2006-03-08 |
US5614855A (en) | 1997-03-25 |
AU1841895A (en) | 1995-08-29 |
JPH09512966A (ja) | 1997-12-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4188349B2 (ja) | 遅延ロック・ループ | |
US5808498A (en) | At frequency phase shifting circuit for use in a quadrature clock generator | |
US6111445A (en) | Phase interpolator with noise immunity | |
US6643790B1 (en) | Duty cycle correction circuit with frequency-dependent bias generator | |
US7868808B2 (en) | Phase-locked loop circuitry using charge pumps with current mirror circuitry | |
US7180352B2 (en) | Clock recovery using clock phase interpolator | |
US6710665B2 (en) | Phase-locked loop with conditioned charge pump output | |
US6385265B1 (en) | Differential charge pump | |
US7323918B1 (en) | Mutual-interpolating delay-locked loop for high-frequency multiphase clock generation | |
US8248130B2 (en) | Duty cycle correction circuit | |
US7292106B2 (en) | Phase-locked loop with conditioned charge pump output | |
US20080284529A1 (en) | Method and apparatus of a ring oscillator for phase locked loop (pll) | |
WO2000060740A1 (en) | Differential charge pump with common mode feedback | |
WO2005099094A2 (en) | Charge pump for a low-voltage wide-tuning range phase-locked loop | |
US7256636B2 (en) | Voltage controlled delay line (VCDL) having embedded multiplexer and interpolation functions | |
JP2001223579A (ja) | プロセスから独立した極小電荷ポンプ | |
US7439783B2 (en) | Phase-locked loop systems and methods | |
US6894569B2 (en) | High-performance charge pump for self-biased phase-locked loop | |
US6504439B1 (en) | Voltage controlled oscillation circuit having oscillation frequency variable control units inserted between inversion circuit elements | |
US6058033A (en) | Voltage to current converter with minimal noise sensitivity | |
US20230318552A1 (en) | Four-phase generation circuit with feedback | |
KR100424174B1 (ko) | 페이스 락 루프 회로 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060406 |
|
A072 | Dismissal of procedure [no reply to invitation to correct request for examination] |
Free format text: JAPANESE INTERMEDIATE CODE: A072 Effective date: 20060720 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071121 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20080221 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20080226 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20080321 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20080326 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20080421 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20080424 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080521 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080822 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080910 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110919 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110919 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120919 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130919 Year of fee payment: 5 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |