CN101809726A - 金属氧化物半导体场效应晶体管有源区和边缘终止区电荷平衡 - Google Patents

金属氧化物半导体场效应晶体管有源区和边缘终止区电荷平衡 Download PDF

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CN101809726A
CN101809726A CN200880109079A CN200880109079A CN101809726A CN 101809726 A CN101809726 A CN 101809726A CN 200880109079 A CN200880109079 A CN 200880109079A CN 200880109079 A CN200880109079 A CN 200880109079A CN 101809726 A CN101809726 A CN 101809726A
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陈曲飞
凯尔·特里尔
沙伦·石
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Vishay Siliconix Inc
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Abstract

公开了一种制造具有有源区和边缘终止区的MOSFET的方法。本方法包括在位于有源区和边缘终止区中的沟槽的底部形成第一多个注入物。在位于有源区的沟槽的底部形成第二多个注入物。在位于有源区的沟槽底部形成第二多个注入物，使得在位于有源区的沟槽的底部形成的注入物达到预定的浓度。这样，有源区和边缘终止区的击穿电压可以变得相似，并因此得到优化，同时还能维持有利的RDson。

Description

金属氧化物半导体场效应晶体管有源区和边缘终止区电荷平衡
相关申请的交叉引用
本专利申请要求2007年10月5日提交的序列号为60/997,945、题为“MOSFET ACTIVE AREA AND EDGE TERMINATION AREA CHARGEBALANCE”，的共同待审的临时专利申请的权益，该申请被转让给本发明的申请人，并且其全部内容通过参考被并入本文中。
技术领域
本发明涉及MOSFET有源区和边缘终止区(edge termination area)电荷平衡。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)是一种场效应晶体管，其通过用电子学方法改变电荷载体沿着流动的MOSFET沟道(channel)的宽度来起作用。MOSFET沟道越宽，MOSFET的传导性越好。MOSFET包括栅极、漏极和源极等部件。电荷载体经由源极进入沟道，并经由漏极出来。可通过改变施加于栅电极的电压，来控制MOSFET沟道的宽度。在传统的MOSFET中，栅电极通常通过氧化物薄层与沟道绝缘。
MOSFET工作参数影响MOSFET的工作和性能。MOSFET工作参数包括漏极-源极击穿电压(BVds)以及漏极-源极导通电阻(RDSon)。
MOSFET的BVds是使绝缘部分变得电气导通的最小电压。因此，通常而言，希望得到高的BVds。重要的是，当超出BVds时，将出现电流流动，这会阻碍MOSFET正常地关断。RDSon是在特定的漏极电流和栅极-源极电压下的栅极-源极电阻。在很多应用中，希望得到低的RDSon，这种低的RDSon与提高的MOSFET电流承载能力相关联。
MOSFET设计者常常在BVds与RDSon之间进行权衡。例如，通过包括更厚更低的掺杂漂移区来增加BVds，会导致RDSon升高。然而，通过包括更薄更高的掺杂漂移区来降低RDSon，会降低BVds。于是，通过考虑权衡，设计者希望找到对于MOSFET最优的BVds和RDSon。由于在有源区和沟槽(trench)边缘终止区中使用的不同沟槽宽度，很难在有源区和边缘终止区上实现类似的BVds。
图1A示出了常规的MOSFET，其包括有源区101和边缘终止区103。如图1A所示，电流流动的期望方向是垂直通过MOSFET(参见表示与有源区沟槽107相邻的垂直沟道105的虚线)。然而，如果超过了BVds，则在加衬着器件沟槽拐角的氧化物中可能发生击穿，并且在MOSFET中可能出现不期望的电流流动。这是因为很多常规的MOSFET表现出不均衡的电场，而电场强度可能在MOSFET沟槽拐角处最大。
图1B示出沟槽位置111、113和115，在这些位置对于加衬图1A所示的常规MOSFET的边缘终止区沟槽109壁的氧化物中的击穿很脆弱。如上所述，这样的电流可能会阻碍MOSFET正常关断。重要的是，很多常规的MOSFET没有配备足够应对边缘终止区电压击穿的保护措施，容易受到这些电流的不利影响。
发明内容
于是，需要一种方法更好地为MOSFET提供应对电压击穿和非期望电流流动的保护措施。本发明提供了一种方法实现此需要。
本发明的实施例通过在MOSFET的有源区和边缘终止区中的沟槽底部构造已调谐的注入物以产生电荷平衡的注入区域，从而优化有源区和边缘终止区中的击穿电压(BVds)。电荷平衡导致注入区域中的电场是平缓的，因此能支持更高的击穿电压(BVds)。并且，有源区中构造的注入物产生的更高的掺杂浓度(doping concentration)有利地降低了MOSFET的器件导通电阻(RDSon)。
作为为MOSFET提供电荷平衡的有源区和边缘终止区的公开方法的一部分，在位于MOSFET的有源区和边缘终止区的沟槽的底部形成第一多个注入物。随后，仅在位于有源区的沟槽的底部形成第二多个注入物。在位于MOSFET有源区的沟槽的底部形成的第二多个注入物致使在位于有源区的沟槽的底部形成的注入物达到期望的浓度。
在一种实施例中，一种用于制造具有有源区和边缘终止区的MOSFET的公开方法包括：在衬底上形成第一和第二外延层，在外延层的顶部中的有源区和边缘终止区形成沟槽，以及在有源区和边缘终止区中形成的沟槽的底部形成多个注入物。并且，此方法包括掩蔽边缘终止区，在有源区形成的沟槽的底部形成多个注入物，以及在边缘终止区上形成厚的氧化物层。在位于边缘终止区中的沟槽中形成的氧化物层比在位于有源区中的沟槽中形成的氧化物层更厚。
并且还公开了一种MOSFET，其包括具有相似的BVds的有源区和边缘终止区。在一种实施例中，有源区包括多个有源区沟槽、与多个沟槽的一个或多个侧壁相邻的源极区、与源极区相邻并位于源极区的竖直下方的栅极区，以及与栅极区相邻并位于栅极区的竖直下方的漏极区。边缘终止区包括栅极拾取沟槽(gate pickup trench)以及多个终结沟槽。在位于有源区和边缘终止区的沟槽的底部提供第一多个注入物。在位于有源区的沟槽的底部形成第二多个注入物，该第二多个注入物导致在位于有源区的沟槽的底部形成的注入物达到预定的期望浓度。有利地，MOSFET可在有源和边缘终止区都具有优化的BVds。
在阅读了以下参考附图详细描述的优选实施例之后，对于本领域普通技术人员，本发明的这些和其它优点无疑地将变得更加明显。
公开了一种用于制造具有有源区和边缘终止区的MOSFET的方法。该方法包括：在位于有源区和边缘终止区中的沟槽的底部形成第一多个注入物。在位于有源区的沟槽的底部形成第二多个注入物。在位于有源区的沟槽的底部形成的第二多个注入物致使在位于有源区的沟槽的底部形成的注入物达到预定的浓度。因为这样操作，可使有源区和边缘终止区的击穿电压变得类似，并因此被优化，同时还能维持有利的RDson。
附图说明
参考附图以及以下描述，将能更好地理解本发明及其进一步的优点。这些附图中：
图1A示出常规的金属氧化物半导体场效应晶体管(MOSFET)器件，其包括有源区和边缘终止区；
图1B示出加衬图1A所示的常规MOSFET的边缘终止区沟槽的壁的氧化物中易受影响的位置；
图2A示出根据本发明的一种实施例形成的MOSFET的横截面；
图2B示出根据本发明的一种实施例为在有源区和边缘终止区之间实现电荷平衡的注入处理的调谐操作；
图3A示出根据本发明的一种实施例在N+衬底上形成的N外延层和P外延层；
图3B示出根据本发明的一种实施例在P外延层中形成的有源区和边缘终止区沟槽；
图3C示出根据本发明的一种实施例在有源区和边缘终止区沟槽的底部处形成的第一组N型的多个注入物；
图3D示出根据本发明的一种实施例在有源区沟槽的底部处形成的第二组N型的多个注入物；
图3E示出根据本发明的一种实施例的在终止沟槽区长出的利用掩模形成的厚氧化物层和在有源区长出的栅极氧化物层；
图3F示出根据本发明的一种实施例在有源区和边缘终止区形成的多晶硅沉积物；
图3G示出根据本发明的一种实施例的阈值电压(Vt)调整注入物和源极注入物；
图3H示出根据本发明的一种实施例在进行了低热氧化物(LTO：LowThermal Oxide)和硼磷硅玻璃(BPSG)沉积之后的器件横截面；
图3I示出根据本发明的一种实施例在形成接触注入物以及金属化和钝化层之后的器件横截面。
可注意到，附图中，类似的参考标号表示类似的元件。
具体实施方式
现在将参考如附图所述的各种实施例详细描述本发明。在以下描述中，为了提供对本发明的更透彻的理解，将阐明具体细节。然而，对于本领域技术人员来说，很明显，无需使用本文详细阐释的一些实施细节，也可以实施本发明。同样可以理解，为了不使本发明变得模糊，此处不对一些众所周知的操作进行详细描述。
根据本发明一种实施例的MOSFET有源区和边缘终止区电荷平衡
图2A示出根据本发明的一种实施例形成的MOSFET 200的横截面。根据本发明的实施例，为MOSFET 200的有源区200a和边缘终止区200b沟槽底部形成了多个注入物，以在这些区域之间实现电荷平衡。在一种实施例中，这种电荷平衡为MOSFET 200提供了在各区域中类似的击穿电压(BVds)，并且，可以优化两个区域中的BVds。此外，注入物提供的较高的掺杂浓度导致MOSFET 200导通电阻(RDSon)降低。此外，电荷平衡导致注入物区域中的电场变得平缓，相比没有电荷平衡注入区特征的MOSFET，这样可为MOSFET 200实现更高的BVds。
在图2A的实施例中，MOSFET 200包括衬底201、外延(epi)层203、外延层205、多个有源区注入物207、多个边缘终止区注入物209、源极注入物211、P型体区阱(P body well)213、栅极区215、漏极区217、有源区沟槽219、有源区沟槽221、栅极拾取沟槽(gate pickup trench)223、边缘终止区沟槽225a-225c、氧化物层227、有源区沟槽氧化物229、边缘终止区沟槽氧化物231、栅极多晶硅(gate poly)233、源极电极235、栅极电极237、漏极电极239，钝化层241和划片线243。
参考图2A，根据本文描述的处理(参见参考图3A-图3H做出的讨论)，在有源区200a和边缘终止区200b沟槽219、221，223和225a-225c的底部形成多个注入物207和209。在图2A的实施例中，在有源区沟槽219和221的底部形成的注入物形成MOSFET 200的漏极区部分。在一种实施例中，可以通过两次注入操作完成这些注入物的形成。初始时，在有源区沟槽219和221以及边缘终止区沟槽223和225a-225c的底部形成多个注入物。之后，在有源区沟槽219和221的底部处形成第二多个注入物。
在一种实施例中，将有源区沟槽219和221的底部处形成的第二多个注入物添加到第一注入操作中在有源区沟槽219和221的底部处形成的第一多个注入物中。第二多个注入物用于有利地“调谐”或调整在第一多重注入操作中在有源区沟槽219和221的底部处形成的注入物，以实现所期望的掺杂浓度。在一种实施例中，对注入物进行调谐，以在器件200的有源区200a和边缘终止区200b之间实现电荷平衡。在有源区200a和边缘终止区200b之间这样实现的电荷平衡，支持更高的BVds。如此，可以在区域200a和200b中优化BVds。
图2B示出根据本发明的一种实施例为实现上述电荷平衡进行的注入处理的调谐操作。参考图2B，在A处，当在位于有源区200a和边缘终止区200b中的沟槽的底部处形成第一多个注入物时，位于这些沟槽底部的注入物的掺杂浓度达到对于边缘终止区沟槽223和225a-225c的最优水平。在B处，当在有源区沟槽219和221的底部处形成第二多个注入物时，第二多个注入物用于将位于有源区沟槽219和221的底部的注入物的掺杂浓度“调谐”到对于有源区沟槽最优的浓度，同时，不干扰终止区的沟槽。
可选择用于形成注入物的注入能量(implantation energy)，以便为注入物实现所期望的掺杂浓度。在一种实施例中，对于8千埃的硬掩模厚度而言(参见以下讨论)，注入能量可包括但不限于一个实例中的150、350和450电子伏特。在其它实施例中，可采用其它注入能量。
再次参考图2A，为MOSFET 200配备了包括边缘终止沟槽225a-225c的边缘终止结构。在一种实施例中，提供此结构是为了防止经由当在划片线243处切断MOSFET 200芯片时生成的路径出现电压击穿或电流泄漏。作为边缘终止结构一部分的多个沟槽225a-225c分摊了或逐渐降低了源极到漏极的电压，从而降低了电压击穿的风险。
在一种实施例中，边缘终止沟槽氧化物231被形成为具有比有源区沟槽氧化物229的厚度更厚的厚度。边缘终止区沟槽氧化物231的厚度使得相比于较薄的氧化物层，可以在关断状态下支持更大的反向偏压电压。在一种实施例中，在形成此氧化物层时可采用1.5千埃的厚度。在其它实施例中，可采用其它厚度。通过允许支持更大的反向偏压电压，这种厚氧化物层提供了防止电压击穿的保护措施。
在操作中，当将导通电压施加到栅极电极237时，该电压通过栅极拾取沟槽(gate pickup trench)223耦合到有源区沟槽219和221，并使电流流经邻近有源区沟槽219形成的沟道。当将关断电压施加到栅极电极237时，围绕边缘终止区沟槽225a-225c的厚氧化物231坚强地支持高的关断电压差。如上讨论，这种厚的氧化物有助于防止在可能发生诸如突然的电流流动等非期望传导情况时出现的击穿。
在一种实施例中，多个注入物提供的高掺杂浓度降低了电子流的电阻，因此降低了RDSon。并且，由多个注入物提供的被电荷平衡的有源区和边缘终止区200a和200b允许在关断状态下从注入区完全放电，这在关断状态下可支持较高的电压条件。相反，在导通状态下，由多个有源区注入物207提供的MOSFET漂移区的较高掺杂使载流子(carrier)能更容易流动，从而有利地降低了RDSon。
本发明的经调谐的注入方法允许将所形成的注入物被调谐到所用的特定宽度的沟槽所需要的精确掺杂浓度。可以理解，通过这样，尽管器件中存在不同宽度的沟槽，也可以实现电荷平衡。并且，在一种实施例中，在有源区200a中可维持垂直的电流，同时，可避免在边缘终止区200b中出现不期望的电流和电压击穿。
在一种实施例中，可以利用用于N沟道器件的P外延层/N外延层/N+衬底以及用于P沟道器件的N外延层/P外延层/P+衬底来制造MOSFET 200。为了实现所期望的RDSon和较高的BVds，以对于整个沟槽底部中所期望的BVds为最优的标准来形成MOSFET 200的多个注入物207和209，从而在器件的整个注入物区中实现如以上讨论的电荷平衡。在示例性实施例中，在有源区200a沟槽底部和边缘终止区200b沟槽底部之间的分离的多个注入物在两个区域上提供了优化的BVds。
MOSFET有源区和边缘终止区电荷平衡的处理流程
图3A-图3I示出了一系列横截面，这些横截面阐释了根据本发明的一种实施例利用多个注入物提供MOSFET有源区和边缘终止区电荷平衡的示例性处理。与图2A所示的相类似的结构在图3A-图3I中以相类似的标号来标记。
如图3A所示，在初始操作中，在N+衬底201上形成了N外延层203和P外延层205。如图3B所示，在进行了导致产生图3A所示横截面的一个或多个操作之后，在P型外延层205中形成有源区和边缘终止区沟槽219、221、223和225a-225c。在一种实施例中，使用硬掩模(hard mask)301来限定沟槽的位置。在一种实施例中，硬掩模301可由低温氧化物、LTO、SiO2形成。在其它实施例中，可以采用其它衬底形成硬掩模301。在一种实施例中，可以利用光致抗蚀剂(未示出)限定硬掩模301中的开口位置，该开口位置限定有源区200a和边缘终止区200b沟槽的位置。在一种实施例中，通过等离子蚀刻处理形成沟槽。在另一种实施例中，可以采用其它处理。沟槽的厚度可由采用等离子蚀刻时使用的注入能量的数量来控制。
并且，再次参考图3B，在沟槽的底部和侧壁上形成氧化物层303。在一种实施例中，在沟槽底部和侧壁上形成的氧化物层303可以由SiO2形成。在一种实施例中，该氧化物可利用低温氧化物(LTO：Low Thermal Oxide)处理形成。
如图3C所示，在进行了导致产生图3B所示横截面的一个或多个操作之后，采用第一组N型的多重注入操作305在有源区和边缘终止区沟槽(例如，207和209)的底部处形成第一组N型的多个注入物。参考图3C，尽管可以平行于器件表面以覆盖方式(blanket manner)提供注入物，硬掩模301(通过选择性阻挡注入物)确保在沟槽(例如，207和209)底部的期望位置注入注入物。在一种实施例中，第一N型多重注入操作305可使用磷注入物(phosphorous implant)。在其它实施例中，可使用其它物质。
在一种实施例中，用来在沟槽底部形成注入物的注入能量取决于所期望的击穿电压。并且，注入物的用量取决于相关沟槽的宽度。在一种实施例中，对于8千埃的硬掩模而言，注入能量可包括但不限于，例如，150、350和450电子伏特。
如图3D所示，在执行了导致产生图3C所示的横截面的一个或多个操作之后，采用第二组N型的多重注入操作307在有源区沟槽(例如，207)的底部形成第二组N型的多个注入物。在一种实施例中，使用第二组N型的多个注入物调谐已经在有源区沟槽219和221的底部制作的注入物，以实现所期望的浓度。在一种实施例中，在注入第二组N型的多个注入物307之前，可以使用光致抗蚀剂掩模309覆盖边缘终止区200b，从而防止第二组N型的多个注入物307被注入到边缘终止区沟槽223、225a、225b和225c的底部。
在一种实施例中，第二组N型的多重注入操作307可使用磷注入物。在其它实施例中，可以在第二组N型的多重注入操作307中使用其它物质。在一种实施例中，可以形成光致抗蚀剂掩模309来覆盖除了有源区沟槽219和221之外的各个沟槽。在一种实施例中，注入能量取决于所期望的击穿电压，而用量取决于沟槽宽度。
如图3E所示，在执行了导致产生图3D所示的横截面的一个或多个操作之后，利用掩模(未示出)在边缘终止沟槽区长出厚的氧化物311，并且在有源区长出栅极氧化物。在一种实施例中，这可以通过如下步骤实现：(1)在器件的整个表面以及沟槽中长出厚的氧化物层；(2)掩蔽器件表面和边缘终止区中的沟槽，然后从剩余的表面和沟槽去除厚氧化物层；以及(3)之后，再次将薄氧化物层施加到剩余的表面和沟槽。在其它实施例中，可以使用其它技术形成厚氧化物层311和薄氧化物层313。
在一种实施例中，厚氧化物层311可长到1.5千埃的厚度。在其它实施例中，厚氧化物层311可长到其它厚度。在一种实施例中，薄氧化物层313可长到100埃的厚度。在其它实施例中，薄氧化物层313可长到其它厚度。
如图3F所示，在执行了导致产生图3E所示横截面的一个或多个操作之后，将多晶硅315沉积到有源区200a和边缘终止区200b沟槽219、221、223和225a-225c中。此后，对所沉积的多晶硅315进行掺杂。接着，对已沉积的多晶硅315进行多晶硅回蚀(etch-back)或化学机械抛光(chemicalmechanical polishing)(CMP)。
如图3G所示，在执行了导致产生图3F所示的横截面的一个或多个操作之后，形成阈值电压(Vt)调整注入物317和源极注入物211。在一种实施例中，可以使用源极掩模(未示出)形成Vt调整注入物317和源极注入物211。在一种实施例中，Vt调整注入物317可包括P型注入物，该P型注入物被形成为P型外延层205中形成的P型体区阱(P body well)213。此注入物用于通过加入到已存在的P型杂质来将位于此区域的P型杂质调谐到所期望的水平。在一种实施例中，通过形成调整此区域中的掺杂浓度的调谐P型注入物，可将阈值电压调整到所期望的水平。
如图3H所示，在执行了导致产生图3G所示的横截面的一个或多个操作之后，进行低温氧化物(LTO)和硼磷硅玻璃(BPSG：borophosphosilicateglass)沉积。之后，形成平面触点(contact)323和沟槽触点321。平面触点323是使得可接触器件的表面的触点。沟槽触点321是使得可通过在器件表面中制造的沟槽进行接触的触点。
如图3I所示，在执行了导致产生图3H所示的横截面的一个或多个操作之后，进行触点注入、金属化以及钝化操作。这些操作提供了源极、栅极和漏极电极，使得可施加电压、接地等。并且，得到了如图3I所示的完整结构。
参考示例性实施例，公开了一种用于制造具有有源区和边缘终止区的MOSFET的方法。该方法包括在位于有源区和边缘终止区中的沟槽的底部形成第一多个注入物。在位于有源区的沟槽的底部形成第二多个注入物。在位于有源区的沟槽的底部形成的第二多个注入物，使得在位于有源区的沟槽的底部形成的注入物达到预定的浓度。
尽管以上为方便起见以单数形式描述了很多组件和处理，本领域普通技术人员可以理解，也可以使用多个组件和重复处理来实施本发明的技术。进一步，尽管已经参考特定实施例具体展示并描述了本发明，本领域普通技术人员可以理解，无需脱离本发明的精神或范围，可以改变所公开的实施例的形式或细节。例如，可以以各种部件部署本发明，而不应该局限于以上提到的那些部件。因此，需要理解的是，本发明包含属于本发明实质精神和范围之内的各种变化等。

Claims (28)

1.一种制造具有有源区和边缘终止区的半导体器件的方法，所述方法包括：
在位于所述有源区的沟槽的底部以及位于边缘终止区的沟槽的底部形成第一多个注入物；以及
在位于所述有源区的所述沟槽的底部形成第二多个注入物，同时不干涉位于所述边缘终止区的所述第一多个注入物，其中，在位于所述有源区的所述沟槽的底部形成的所述第二多个注入物致使在位于所述有源区的所述沟槽的底部形成的所述注入物达到预定的浓度。
2.如权利要求1所述的方法，进一步包括：
在位于所述有源区的所述沟槽的所述底部形成所述第二多个注入物之前，掩蔽所述边缘终止区。
3.如权利要求1所述的方法，进一步包括：
在位于所述有源区的所述沟槽的壁上形成一层氧化物；以及
在位于所述边缘终止区的所述沟槽的壁上形成一层氧化物，其中，在位于所述边缘终止区的所述沟槽的壁上的所述一层氧化物比在位于所述有源区的所述沟槽的壁上形成的所述一层氧化物更厚。
4.如权利要求1所述的方法，进一步包括：
在所述边缘终止区中形成多个边缘终止触点。
5.如权利要求3所述的方法，其中，在位于所述有源区的所述沟槽的壁上形成一层氧化物的操作，是在位于所述边缘终止区的所述沟槽的壁上形成一层氧化物之后进行的。
6.如权利要求1所述的方法，其中，所述第一多个注入物和所述第二多个注入物导致所述有源区内部和所述边缘终止区内部同时达到电荷平衡。
7.如权利要求2所述的方法，其中，所述第一多个注入物是在掩蔽所述边缘终止区之前形成的。
8.如权利要求2所述的方法，其中，所述第二多个注入物是在掩蔽所述边缘终止区之后形成的。
9.如权利要求1所述的方法，其中，所述第一多个注入物和所述第二多个注入物是用于N沟道器件的磷注入物和用于P沟道器件的硼注入物。
10.如权利要求1所述的方法，其中，在位于所述有源区的所述沟槽的壁上以及在位于所述边缘终止区的所述沟槽的壁上形成氧化物的操作是利用低温氧化物(LTO)处理实现的。
11.一种用于制造具有有源区和边缘终止区的MOSFET的方法，所述方法包括：
在衬底上形成第一和第二半导体层；
在所述半导体层的顶部中的所述有源区和所述边缘终止区中形成沟槽；
在所述有源区和所述边缘终止区中形成的所述沟槽的底部形成第一多个注入物；
掩蔽所述边缘终止区；
在所述有源区中形成的所述沟槽的底部形成第二多个注入物；以及
在所述边缘终止区中形成的所述沟槽中形成氧化物层，并且在所述有源区中形成的所述沟槽中形成氧化物层，其中，在所述边缘终止区的所述沟槽中形成的所述氧化物层比在所述有源区中的所述沟槽中形成的所述氧化物层更厚。
12.如权利要求11所述的方法，进一步包括：
形成填充所述沟槽的多晶硅层，并对所述多晶硅层进行多晶硅掺杂以及多晶硅回蚀；
形成源极注入物以及阈值电压调整注入物；
形成平面和沟槽触点；以及
在所述触点中形成触点注入物和金属化层，并在所述金属化层上形成钝化层。
13.如权利要求11所述的方法，进一步包括：
在所述边缘终止区中形成多个边缘终止触点。
14.如权利要求11所述的方法，其中，在所述有源区中形成的所述沟槽中形成所述氧化物层的操作在所述边缘终止区中形成的所述沟槽中形成所述氧化物层之后执行。
15.如权利要求11所述的方法，其中，所述第一多个注入物和所述第二多个注入物导致所述有源区内部和所述边缘终止区内部同时达到电荷平衡。
16.如权利要求11所述的方法，其中，所述第一多个注入物是在掩蔽所述边缘终止区之前形成的。
17.如权利要求11所述的方法，其中，所述第二多个注入物是在掩蔽所述边缘终止区之后形成的。
18.如权利要求11所述的方法，其中，所述第一多个注入物和所述第二多个注入物是用于N沟道器件的磷注入物和用于P沟道器件的硼注入物。
19.如权利要求11所述的方法，其中，在所述有源区中形成的所述沟槽中以及在所述边缘终止区中形成的所述沟槽中形成的所述氧化物层是利用低温氧化物(LTO)处理形成的。
20.一种半导体器件，其包括：
有源区，包括：
多个有源区沟槽；
与所述多个有源区沟槽的一个或多个侧壁相邻的源极区；
邻近于所述源极区并位于所述源极区的竖直下方的栅极区；以及
邻近于所述栅极区并位于所述栅极区的竖直下方的漏极区；
以及
边缘终止区，包括：
栅极拾取沟槽；以及
多个边缘终止区沟槽，
其中，第一多个注入物被形成在所述有源区和所述边缘终止区中形成的沟槽的底部，并且，第二多个注入物被形成在所述有源区中形成的所述沟槽的底部，并使得在所述有源区中形成的所述沟槽的底部形成的所述注入物达到预定浓度。
21.如权利要求20所述的器件，进一步包括：
在所述多个有源区沟槽中形成的一层氧化物；以及
在所述多个边缘终止区沟槽中形成的一层氧化物，其中，在所述多个边缘终止区沟槽中形成的所述一层氧化物比在所述多个有源区沟槽中形成的所述一层氧化物更厚。
22.如权利要求21所述的器件，进一步包括：
所述边缘终止区中的多个边缘终止触点。
23.如权利要求20所述的器件，其中，所述第一多个注入物和所述第二多个注入物导致所述有源区内部和所述边缘终止区内部同时达到电荷平衡。
24.如权利要求20所述的器件，其中，所述第一多个注入物和所述第二多个注入物是用于N沟道器件的磷注入物和用于P沟道器件的硼注入物。
25.如权利要求21所述的器件，其中，在所述有源区沟槽和所述边缘终止区沟槽中形成的所述一层氧化物是利用低温氧化物(LTO)处理形成的。
26.如权利要求21所述的器件，其中，所述有源区沟槽和所述边缘终止区沟槽被填充以经掺杂的多晶体。
27.如权利要求20所述的器件，其中，在包括电压调整注入物的体区阱上形成所述源极。
28.如权利要求20所述的器件，进一步包括平面触点和沟槽触点，所述平面触点和沟槽触点中充满金属。
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US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices

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CN102280485A (zh) * 2011-08-12 2011-12-14 淄博美林电子有限公司 一种小体积高耐压mosfet
CN102280485B (zh) * 2011-08-12 2013-07-10 淄博美林电子有限公司 一种小体积高耐压mosfet
CN103219395A (zh) * 2012-01-20 2013-07-24 英属维京群岛商节能元件股份有限公司 用于半导体元件的多沟渠终端结构及其制作方法
CN105679756A (zh) * 2015-11-25 2016-06-15 杭州立昂微电子股份有限公司 一种半导体器件顶层金属的终端结构及其制造方法
CN105679756B (zh) * 2015-11-25 2018-08-10 杭州立昂微电子股份有限公司 一种半导体器件顶层金属的终端结构及其制造方法
CN106024866A (zh) * 2016-07-25 2016-10-12 电子科技大学 一种功率半导体器件的沟槽型终端结构
CN106024866B (zh) * 2016-07-25 2019-03-29 电子科技大学 一种功率半导体器件的沟槽型终端结构
CN113646897A (zh) * 2018-12-21 2021-11-12 通用电气公司 用于碳化硅电荷平衡功率器件中的终端的系统和方法
CN110335895A (zh) * 2019-07-31 2019-10-15 上海昱率科技有限公司 功率器件及其制造方法

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US20090090967A1 (en) 2009-04-09
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