US20190096861A1 - Microelectronic package for wafer-level chip scale packaging with fan-out - Google Patents
Microelectronic package for wafer-level chip scale packaging with fan-out Download PDFInfo
- Publication number
- US20190096861A1 US20190096861A1 US16/201,569 US201816201569A US2019096861A1 US 20190096861 A1 US20190096861 A1 US 20190096861A1 US 201816201569 A US201816201569 A US 201816201569A US 2019096861 A1 US2019096861 A1 US 2019096861A1
- Authority
- US
- United States
- Prior art keywords
- wire bond
- microelectronic
- microelectronic package
- bond wires
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004377 microelectronic Methods 0.000 title claims abstract description 184
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 88
- 239000012778 molding material Substances 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 230000008878 coupling Effects 0.000 claims description 10
- 238000010168 coupling process Methods 0.000 claims description 10
- 238000005859 coupling reaction Methods 0.000 claims description 10
- 238000000465 moulding Methods 0.000 claims description 9
- 230000007704 transition Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 37
- 239000010410 layer Substances 0.000 description 94
- 239000000853 adhesive Substances 0.000 description 22
- 230000001070 adhesive effect Effects 0.000 description 22
- 238000010586 diagram Methods 0.000 description 21
- 238000000227 grinding Methods 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 238000001465 metallisation Methods 0.000 description 9
- 239000011888 foil Substances 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 208000029523 Interstitial Lung disease Diseases 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000012876 carrier material Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910006990 Si1-xGex Inorganic materials 0.000 description 1
- 229910007020 Si1−xGex Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H01L2021/60—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1416—Random layout, i.e. layout with no symmetry
- H01L2224/14163—Random layout, i.e. layout with no symmetry with a staggered arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/14177—Combinations of arrays with different layouts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Definitions
- the following description relates to integrated circuit (“IC”) packaging. More particularly, the following description relates to microelectronic packages for wafer-level chip scale packaging with fan-out.
- IC integrated circuit
- Microelectronic assemblies generally include one or more ICs, such as for example one or more packaged dies (“chips”) or one or more dies.
- ICs such as for example one or more packaged dies (“chips”) or one or more dies.
- One or more of such ICs may be mounted on a circuit platform, such as a wafer such as in wafer-level-packaging (“WLP”), printed board (“PB”), a printed wiring board (“PWB”), a printed circuit board (“PCB”), a printed wiring assembly (“PWA”), a printed circuit assembly (“PCA”), a package substrate, an interposer, or a chip carrier.
- WLP wafer-level-packaging
- PB printed board
- PWB printed wiring board
- PCB printed circuit board
- PWA printed wiring assembly
- PCA printed circuit assembly
- package substrate an interposer
- interposer or a chip carrier
- An interposer may be an IC, and an interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device. Furthermore, an interposer may be formed like a PWB, namely without any circuit elements such as capacitors, resistors, or active devices. Additionally, an interposer includes at least one through-substrate-via.
- An IC may include conductive elements, such as pathways, traces, tracks, vias, contacts, pads such as contact pads and bond pads, plugs, nodes, or terminals for example, that may be used for making electrical interconnections with a circuit platform. These arrangements may facilitate electrical connections used to provide functionality of ICs.
- An IC may be coupled to a circuit platform by bonding, such as bonding traces or terminals, for example, of such circuit platform to bond pads or exposed ends of pins or posts or the like of an IC.
- a redistribution layer (“RDL”) may be part of an IC to facilitate a flip-chip configuration, die stacking, or more convenient or accessible position of bond pads for example.
- fan-out wafer-level chip scale packaging (“FO-WCSP”) has been used to reduce costs.
- Semiconductor dies are formed, such as in their smallest configurations, and these dies or a combination of different dies may then be molded together in what is known as a reconstituted wafer.
- This reconstituted wafer provides more surface area for interconnects using WCSP in combination with a fan-out technology, such as a lead frame, ball grid array, or other fan-out technology. This allows for a larger pitch for interconnection to a PCB or other circuit board.
- FO-WCSP package-on-package
- An apparatus relates generally to a microelectronic package for wafer-level chip scale packaging with fan-out.
- a substrate having an upper surface and a lower surface opposite the upper surface.
- a microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation.
- Wire bond wires are coupled to and extending away from a face of the microelectronic device facing away from the substrate.
- Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate.
- a method relates generally to forming a microelectronic package for wafer-level chip scale packaging with fan-out.
- a substrate having an upper surface and a lower surface opposite the upper surface.
- a microelectronic device having posts is coupled in a face-up orientation to the upper surface of the substrate.
- Wire bond wires are bonded to the upper surface of the substrate for extending away therefrom to a height above the posts.
- the substrate, the microelectronic device and the wire bond wires in combination is molded with a molding material layer. An uppermost portion of the wire bond wires and an uppermost portion of the molding material layer is removed to upper ends of the posts.
- Conductive pads are formed in the substrate. The conductive pads are for the wire bond wires for electrical conductivity between the wire bond wires and the conductive pads associated therewith.
- An apparatus relates generally to another microelectronic package for wafer-level chip scale packaging with fan-out.
- a substrate has an upper surface and a lower surface opposite the upper surface.
- the substrate includes conductive pads formed therein.
- Wire bond wires are coupled to and extend away from a first portion of the conductive pads along the upper surface for electrical conductivity between the wire bond wires and the first portion of the conductive pads associated therewith.
- a microelectronic device is coupled to a second portion of the conductive pads along the upper surface with the microelectronic device in a face-down orientation.
- a method relates generally to another microelectronic package for wafer-level chip scale packaging with fan-out.
- a substrate having an upper surface and a lower surface opposite the upper surface.
- Conductive pads are formed in the substrate.
- Wire bond wires are bonded to the conductive pads along the upper surface of the substrate for extending away therefrom.
- the conductive pads are for the wire bond wires for electrical conductivity between the wire bond wires and the conductive pads associated therewith.
- a microelectronic device is coupled in a face-down orientation to the upper surface of the substrate with interconnects.
- the substrate, the microelectronic device and the wire bond wires in combination is molded with a molding material layer.
- FIGS. 1-1 through 1-9 are a progression of block diagrams of a cross-sectional side view depicting formation of an exemplary in-process microelectronic package for wafer-level chip scale package (“WCSP”) with fan-out (“FO”).
- WCSP wafer-level chip scale package
- FO fan-out
- FIG. 2 is a block diagram of a top view depicting an exemplary in-process microelectronic package.
- FIG. 3 is a block diagram of a top view depicting an exemplary in-process microelectronic package after forming balls on a redistribution layer (“RDL”).
- RDL redistribution layer
- FIG. 4 is a block diagram of a cross-sectional side view depicting an exemplary package-on-package (“PoP”) microelectronic package.
- PoP package-on-package
- FIG. 5 is a block diagram of a cross-sectional side view depicting another exemplary PoP microelectronic package.
- FIG. 6 is a flow diagram depicting an exemplary process flow for forming a microelectronic package for WCSP with FO.
- FIGS. 7-1 through 7-6 are a progression of block diagrams of a cross-sectional side view depicting formation of another exemplary in-process microelectronic package for WCSP with fan-out FO.
- FIG. 8 is a flow diagram depicting an exemplary process flow for forming another microelectronic package for WCSP with fan-out FO.
- FIG. 9 is a block diagram of a cross-sectional side view depicting an exemplary PoP microelectronic package.
- FIG. 10 is a block diagram of a cross-sectional side view depicting another exemplary PoP microelectronic package.
- an integrated circuit die includes a substrate of a semiconductor material such as silicon (Si), gallium arsenide (GaAs), polymeric, ceramic, carbon-based substrates such as diamond, a silicon carbon (SiC), germanium (Ge), Si 1-x Ge x , or the like.
- a semiconductor substrate as provided from an in-process wafer is generally described below, any sheet or layer semiconductor material or dielectric material, such as ceramic or glass for example, may be used as a substrate.
- a substrate includes an upper surface and a lower surface that extend in lateral directions and are generally parallel to each other at a thickness thereof.
- Use of terms such as “upper” and “lower” or other directional terms is made with respect to the reference frame of the figures and is not meant to be limiting with respect to potential alternative orientations, such as in further assemblies or as used in various systems.
- An upper surface may generally be associated with what is referred to as a “front side” of an in-process wafer, and a lower surface may generally be associated with what is referred to as a “back side” of an in-process wafer.
- a front-side of an in-process wafer may be used for forming what is referred to as front-end-of-line (“FEOL”) structures and back-end-of-line (“BEOL”) structures.
- FEOL front-end-of-line
- BEOL back-end-of-line
- FEOL structures may include shallow trench isolations (“STI”), transistor gates, transistor source/drain regions (not shown), transistor gate dielectrics (not shown), contact etch stop layer (“CESL”; not shown), a pre-metallization dielectric or pre-metal dielectric (“PMD”), and contact plugs, among other FEOL structures.
- a PMD may be composed of one or more layers.
- BEOL structures may include one or more inter-level dielectrics (“ILDs”) and one or more levels of metallization (“M”). Each ILD may be composed of one or more dielectric layers, and each metal or metallization level may be composed of one or more metal layers, as well as one or more barrier and/or liner layers.
- metal from a metallization level may extend through one or more ILDs, as is known.
- a passivation level may be formed on a last metallization layer.
- Such passivation level may include one or more dielectric layers, and further may include an anti-reflective coating (“ARC”).
- ARC anti-reflective coating
- RDL redistribution layer
- an RDL may include: a dielectric layer, such as a polyimide layer for example; another metal layer on such dielectric layer connected to a bond pad of a metal layer of a last metallization level; and another dielectric layer, such as another polyimide layer for example, over such RDL metal layer while leaving a portion thereof exposed to provide another bond pad.
- a terminal opening may expose such other bond pad of such RDL metal layer.
- a solder bump or wire bond may be conventionally coupled to such bond pad.
- Balls or other discrete interconnects may be respectively formed on bonding pads, where such pads may be formed on or as part of metal layer. Balls may be formed of a bonding material, such as solder or other bonding material. Balls may be microbumps, C4 bumps, ball grid array (“BGA”) balls, or some other die interconnect structure. In some applications, metal layer may be referred to as a landing pad. BGA, lead frame, and other types of interconnects may be used as fan-out technologies.
- wire bond wires are used for interconnection with an upper package of a PoP device.
- Use of wire bond wires as described below may eliminate a substrate and/or corresponding through substrate vias used in a conventionally manufactured PoP device with fan-out.
- a lower cost and thinner PoP device with fan-out may be manufactured using wire bond wires as described hereinbelow.
- a PoP device with fan-out using wire bond wires such as of a BVATM technology, may be used in mobile devices and other small form factor applications.
- FIGS. 1-1 through 1-9 are a progression of block diagrams of a cross-sectional side view depicting formation of an exemplary in-process microelectronic package 100 for wafer-level chip scale package (“WCSP”) with fan-out (“FO”).
- FIGS. 1, 4 and 5 hereof are described with simultaneous reference to FIG. 6 , where there is shown a flow diagram depicting an exemplary process flow 600 for forming a microelectronic package 100 for WCSP with FO.
- in-process microelectronic package 100 includes a carrier 101 coupled to a foil substrate layer 103 with a releasable adhesive 102 .
- carrier 101 is a copper carrier
- foil substrate layer 103 is copper foil layer.
- carrier 101 may be silicon, glass, laminate, or other dielectric and/or metal carrier material.
- Carrier 101 may or may not be opaque, such as with respect to UV rays for example.
- releasable adhesive 102 may be a thermal or UV released adhesive for example.
- foil substrate layer 103 may be another electrical conductor, such as gold, platinum or other thin film metal for example.
- Foil substrate layer (“substrate”) 103 has an upper surface 104 and a lower surface 105 opposite such upper surface 104 .
- wire bond wires may be bonded to the upper surface of the substrate for extending away therefrom to a height above posts of a microelectronic device.
- wire bond wires 110 are coupled to and extend away from upper surface 104 .
- copper wire bond wires 110 are used.
- another form of wire bond wires 110 may be used, such as aluminum, silver, gold, palladium-coated copper (“PCC”), core wires, or other forms of wire bond wire.
- Wire bond wires 110 may be BVATM bonded wires. Columns and/or rows (“rows”) 112 of wire bond wires 110 may be spaced apart from one another to define a region 111 and may be coupled to upper surface 104 .
- wire bond wires 110 are ball bonded with corresponding ball bonds 113 to upper surface 104 .
- stitch, wedge, compliant, or other forms of BVA bonding may be used.
- copper wire bond wires 110 may be attached with ball bonds to upper surface 104 of substrate 103 for substrate-to-upper package routing.
- a “wired-arch” or “wired-loop” wire bond wire 114 may be formed on upper surface 104 such that a first bond, such as a ball bond 113 for example, is formed at a first location on upper surface 104 and a second bond, such as a wedge or stitch bond 144 , is formed at a second location on upper surface 104 spaced apart from such first location by at least approximately 10-400 microns for example.
- An upper surface 134 of such a “wired-arch” wire bond wire 114 may be used for interconnection, as described elsewhere herein. However, for purposes of clarity by way of example and not limitation, generally only wire bond wires 110 , and not wired-arch wire bond wires 114 , are further described.
- Ball bonds 113 may be spaced apart from one another. Even though only single rows 112 spaced apart from one another are illustratively depicted in FIG. 1-2 , in other implementations one or more rows 112 may be on one or more sides of region 111 defined by such rows 112 . However, for purposes of clarity by way of example and not limitation, it shall be assumed that a single row 112 is located on each side of region 111 for defining such region for receipt of a microelectronic device. Moreover, wire bond wires 110 may extend to a height above posts of such a microelectronic device, as described below in additional detail.
- a microelectronic device having posts may be coupled in a face-up orientation to the upper surface of the substrate.
- operations at 602 and 603 may be in reverse order.
- a microelectronic device 115 may be coupled to upper surface 104 with an adhesive or an underfill 116 in region 111 .
- Microelectronic device 115 may be spaced apart from ball bonds 113 after coupling to upper surface 104 .
- Adhesive 116 may be a compliant material after curing, such as a polyimide (“PI”) or a polybenzoxazole (“PBO”) for example, with a modulus of elasticity of less than approximately 4 gigapascals (“GPa”).
- PI polyimide
- PBO polybenzoxazole
- Microelectronic device 115 may be coupled to upper surface 104 in a face-up or front side up orientation. Generally, a face of microelectronic device 115 having posts extending away therefrom, such a face may be facing away from such substrate to which microelectronic device 115 is coupled in this implementation. Even though wire bond wires 110 are attached to upper surface 104 in this example prior to coupling microelectronic device 115 , this order may be reversed in this or another implementation. Microelectronic device 115 may be a packaged or bare integrated circuit die formed using a Si, GaAs, or other semiconductor wafer. Optionally, microelectronic device 115 may be a passive device.
- conductive posts or pads 117 of microelectronic device 115 extend away from a front side or face thereof, namely upper surface 118 .
- upper ends 122 of electrically conductive posts or pads 117 are over and above an upper surface 118 of microelectronic device 115 .
- copper posts or pads 117 are used.
- another type of electrically conductive material may be used for posts or pads 117 .
- a structure other than posts or pads 117 such as stud bumps for example, may be attached along upper surface 118 of microelectronic device 115 .
- Stud bumps may be a ball bonds, such as a ball bond-only portion of wire bonds.
- posts or pads 117 may be formed with a metalization layer used in forming microelectronic device 115 .
- a metalization layer used in forming microelectronic device 115 .
- copper posts 117 are used for interconnects.
- in-process microelectronic package 100 may be a portion of a reconstituted wafer having multiple in-process microelectronic packages 100 .
- a reconstituted wafer typically consist of dies coupled to one another by a molding material in-between them to form a wafer or substrate.
- the substrate, the microelectronic device and the wire bond wires assemblage or combination may be molded with a molding material layer, which may include grinding or polishing of a surface of such molding material layer.
- a molding material layer 120 may be formed over upper surface 104 , microelectronic device 115 and wire bond wires 110 .
- tips or upper ends 123 of wire bond wires 110 are above an upper surface 124 of molding material layer 120 .
- an upper surface 134 of such a wire arch 114 may be embedded or protrude above an upper surface 124 of molding material layer 120 .
- wire bond wires 110 may extend above upper ends 122 of posts 117 .
- tips 123 of wire bond wires 110 , or upper surface 134 of wired-arch wire bond wires 114 may be exposed after forming molding material layer 120
- upper ends 122 of post 117 are covered by molding material layer 120 .
- molding layer 120 may cover tips 123 , or upper surfaces 134 , as generally indicated by dashed line 121 .
- it shall be assumed that tips 123 are exposed after forming molding material layer 120 .
- Molding material layer 120 may be for forming a reconstituted wafer having multiple in-process microelectronic packages 100 .
- carrier 101 may be removed along with adhesive 102 .
- adhesive 102 may be a releasable adhesive using temperature, UV rays, and/or other releasing agent.
- molding material layer 120 may be ground or polished down to expose upper ends 122 . Removal of material such as by grinding may occur before or after removal of carrier 101 . After grinding, upper ends 130 of wire bond wires 110 , as well as upper ends 122 of posts 117 , may be exposed for interconnections respectively thereto. However, after grinding, molding material layer 120 may be left in place around posts 117 and remaining portions of wire bond wires 110 .
- first and second bonds thereof may be electrically disconnected from one another for example by grinding a protruding upper surface 134 to cause a break in such wire arch 114 leaving two at least temporarily exposed upper ends along upper surface 134 .
- grinding may effectively form two separate wire bonds with different bond types, for example a ball bond 113 and a wedge or stitch bond 144 .
- upper surface 124 may be generally co-planar with upper ends 122 and 130 after grinding.
- Posts 117 may be in region 111 defined by rows and columns of wire bond wires 110 surrounding microelectronic device 115 .
- a redistribution layer (“RDL”) 135 may be formed with a bottom surface thereof interconnected to upper ends 122 of posts 117 and upper ends 130 of wire bond wires 110 for interconnecting at least a portion of wire bond wires 110 with at least a portion of posts 117 .
- RDL 135 may include one or more dielectric and conductive layers.
- an integrated circuit die may be interconnected to conductive pads on a lower surface of a substrate, as described below in additional detail.
- RDL 135 may be entirely formed on upper surface 124 of molding material layer 120 , as well as being interconnect to upper ends 130 of wire bond wires 110 and to upper ends 122 of posts 117 .
- an RDL is formed on top of a Si substrate and then surrounded with molding material, and so a large stress field is developed around a transition area or “triple point” where such RDL, Si substrate and molding material intersect.
- RDL 135 avoids a conventional “triple point.”
- wire bond wires 110 may provide “vertical interconnects” along sides of a microelectronic device for interconnecting substrate 103 and RDL 135 . Such wire bond wires 110 may additionally be interconnected to corresponding posts 117 of microelectronic device 115 .
- conductive pads may be formed in the substrate electrically isolated from a remainder of the substrate, where the conductive pads correspond to the wire bond wires for electrical conductivity between the wire bond wires and the conductive pads corresponding thereto.
- in-process microelectronic package 100 may be flipped for patterning and etching a lower surface 105 of substrate 103 , namely a back side of microelectronic package 100 .
- a direct write etch may be used on lower surface 105 .
- Through substrate channels 142 may be formed from lower surface 105 to upper surface 104 with a stop molding layer 120 for example.
- Through substrate channels 142 may be at least partially, if not completely, filled with a dielectric material 143 , such as a polyimide for example.
- Conductive pads 140 may be defined by such through substrate channels 142 in copper substrate 103 for this example implementation. Conductive pads or conductive islands 140 may have previously been coupled to wire bond wires 110 , as previously described with reference to bonding to upper surface 104 of substrate 103 .
- Conductive pads 140 may be defined in substrate 103 as respective islands of a material of such substrate.
- conductive pads 140 are illustratively depicted near an outer edge of microelectronic package 100 , conductive pads 140 may be formed in generally a middle region (“remainder”) 141 , such as directly below microelectronic device 115 for example.
- Conductive pads 140 may be formed using substrate 103 material for electrical isolation from a remainder 141 of substrate 103 . Such remainder 141 may be used as a ground plane. In some instances, no conductive pad 140 may be associated with a wire bond wire 110 for coupling to a ground plane, or other voltage plane. Conductive pads 140 corresponding to wire bond wires 110 for electrical conductivity therebetween may be used for electrical communication with microelectronic package 100 and/or another microelectronic package as described below in additional detail. Although not illustratively depicted in FIG. 1 , another redistribution layer RDL may be formed on a top surface of substrate 103 . This RDL, like RDL 135 , may include one or more dielectric and conductive layers.
- first interconnects may be attached to a top surface of the redistribution layer for electrical conductivity with the posts and the wire bond wires.
- balls or bumps 145 may be formed on exposed surfaces of traces or pads 169 of conductive layer 136 . Such balls or bumps 145 may be mechanically isolated from electrical conductivity by one or more dielectric layers 137 of an RDL 135 . However, such conductive traces or pads 169 of conductive layer 136 may be coupled for electrical conductivity with wire bond wires 110 , as well as one or more posts 117 , as previously described. Balls or bumps 145 for interconnection with posts 117 and not wire bond wires 110 are not illustratively depicted in this figure for purposes of clarity and not limitation.
- FIG. 3 where there is shown a block diagram of a top view depicting an exemplary in-process microelectronic package 100 after forming balls 145 on RDL 135 .
- balls 145 may be associated with pads or traces 169 of conductive layer 136 for coupling to wire bond wires.
- Others of balls 145 may be associated with pads or traces 169 of conductive layer 136 not associated with wire bond wires 110 and associated with posts 117 .
- wire bond wires 110 may be interconnected to more than one post 117 . In one or more instances, there may not be a direct coupling for an electrical connection between at least one wire bond wire 110 and at least one post 117 .
- Pitch 148 of pads 169 of conductive layer 136 for balls 145 associated with wire bond wires 110 may be in a range of approximately 350 to 600 microns or less for correspondence with pitch of contacts on a PCB or other circuit board.
- minimum pitch of posts 117 and wire bond wires 110 may be as small as 5 microns and as small as 20 microns, respectively.
- An RDL 135 may effectively cause pitch 148 to be at least approximately the same as for example a BGA pitch of a circuit board, such as approximately 350 microns.
- second interconnects of another microelectronic device may be coupled to the conductive pads for electrical conductivity with the wire bond wires.
- FIG. 4 there is shown a block diagram of a cross-sectional side view depicting an exemplary PoP microelectronic package 300 .
- a microelectronic package 100 which may still be in a reconstituted wafer or may be diced therefrom, has coupled on the back side thereof another microelectronic package 200 .
- PoP microelectronic package 300 may be package-to-package assembled, package-to reconstituted wafer assembled, or wafer/reconstituted wafer to reconstituted wafer assembled, with the last three involving subsequent dicing.
- microelectronic devices 115 and 201 are respective packaged integrated circuit dies; however, in another example either or both microelectronic devices 115 and 201 may be bare integrated circuit dies.
- microelectronic package 100 may be an applications processor or a baseband processor or any other logic device
- microelectronic package 200 may be a memory device, such as with one or more types of memory die including NAND, DRAM, memory controller, and/or the like.
- Bumps or balls 155 of microelectronic package 200 may be physically coupled to conductive pads 140 of microelectronic package 100 for electrical conductivity between microelectronic packages 100 and 200 .
- PoP microelectronic package 300 may be coupled to a PCB or other circuit board 160 which is not part of PoP microelectronic package 300 .
- Overall height 400 of PoP microelectronic package 300 may be approximately 1.5 mm or less.
- an underfill (not shown) may be injected between microelectronic packages 100 and 200 .
- FIG. 5 there is shown a block diagram of a cross-sectional side view depicting another exemplary PoP microelectronic package 300 .
- a microelectronic package 100 which may still be in a reconstituted wafer or may be diced therefrom, has formed on a back side thereof another RDL 165 .
- Another microelectronic package 200 may be coupled to an optional RDL 165 .
- a bottom surface of RDL 165 may be interconnected to conductive pads 140 of microelectronic package 100 for electrical conductivity therewith.
- Either or both of RDLs 135 and/or 165 may have one or more metal layers and/or one or more dielectric layers.
- Bumps or balls 155 of microelectronic package 200 may be physically coupled to conductive pads 164 of RDL 165 of microelectronic package 100 for electrical conductivity between microelectronic packages 100 and 200 .
- PoP microelectronic package 300 may be coupled to a PCB or other circuit board 160 not part of PoP microelectronic package 300 .
- Overall height 400 of PoP microelectronic package 300 may be approximately 1.5 mm or less.
- Wire bond wires 110 may be disposed around a perimeter of microelectronic device 115 , which may be packaged integrated circuit die or a bare integrated circuit die.
- FIGS. 7-1 through 7-6 are a progression of block diagrams of a cross-sectional side view depicting formation of another exemplary in-process microelectronic package 100 for WCSP with fan-out FO.
- FIGS. 7, 9 and 10 are hereafter described with simultaneous reference to FIG. 8 , where there is shown a flow diagram depicting an exemplary process flow 800 for forming such other microelectronic package 100 for WCSP with fan-out FO.
- in-process microelectronic package 100 includes a carrier 101 coupled to a foil substrate layer 103 with a releasable adhesive 102 .
- carrier 101 is a copper carrier
- foil substrate layer 103 is copper foil layer.
- carrier 101 may be silicon, glass, laminate, or other metal and/or dielectric carrier material.
- Carrier 101 may or may not be opaque, such as with respect to UV rays for example.
- releasable adhesive 102 may be a thermal or UV released adhesive for example.
- foil substrate layer 103 may be another electrical conductor, such as gold, platinum or other thin film metal for example.
- Foil substrate layer (“substrate”) 103 has an upper surface 104 and a lower surface 105 opposite such upper surface 104 .
- conductive pads or conductive islands may be formed in the substrate electrically isolated from a remainder of the substrate.
- the conductive pads may correspond to the wire bond wires for electrical conductivity between the wire bond wires and the conductive pads corresponding thereto as described below in additional detail.
- in-process microelectronic package 100 may have an upper surface 104 of substrate 103 directly written with a laser drill. In another implementation, patterning and etching may be used on upper surface 104 . Through substrate channels 142 may be formed from upper surface 104 down to lower surface 105 .
- Through substrate channels 142 may be at least partially, if not completely, be filled with a dielectric material 143 , such as a polyimide for example.
- Conductive pads 140 may be defined by such through substrate channels 142 in copper substrate 103 for this example implementation.
- Conductive pads 140 may be defined in substrate 103 as respective islands of a material of such substrate.
- substrate channels 142 may not be filled with any material, and conductive pads 140 may only be attached to carrier 101 via adhesive 102 .
- Conductive pads 140 may be formed using substrate 103 material for electrical isolation from a remainder of substrate 103 , and such remainder of substrate 103 not used for conductive pads 140 may be used as a ground plane (not shown in this figure). However, for a face-down configuration as described with reference to FIG. 7 for example, conductive pads 140 may be formed for interconnection with posts or pads 117 of a microelectronic device 115 , as described below in additional detail.
- wire bond wires may be bonded to the upper surface of the substrate for extending away therefrom to a height above a microelectronic device, as described below in additional detail.
- wire bond wires 110 are coupled to and extend away from upper surface 104 .
- copper wire bond wires 110 are used.
- another form of wire bond wires 110 may be used, such as aluminum, silver, gold, palladium-coated copper (“PCC”), core wires, or other forms of wire bond wire.
- Wire bond wires 110 may be BVATM bonded wires.
- a “wired-arch” or “wired-loop” wire bond wire 114 may be formed on upper surface 104 such that a first bond, such as a ball bond 113 for example, is formed at a first location on upper surface 104 and a second bond, such as a wedge or stitch bond 144 , is formed at a second location on upper surface 104 spaced apart from such first location by at least approximately 10 microns for example.
- An upper surface 134 of such a “wired-arch” wire bond wire 114 may be used for interconnection, as described elsewhere herein. However, for purposes of clarity by way of example and not limitation, generally only wire bond wires 110 , and not wired-arch wire bond wires 114 , are further described.
- Rows 112 of wire bond wires 110 may be spaced apart from one another to define a region 111 and may be coupled to upper surface 104 .
- Such spacing between wire bond wires 110 may, though need not be uniform.
- a denser spacing may be used in some locations as compared with other locations, as may vary from application to application depending on routing.
- routing, including via RDL may be denser in some areas as compare with other areas corresponding to layout of an integrated circuit die. Having the flexibility to have wire bond wires 110 use different spacings may be useful to accommodate shorter path distances and/or pin layout of a package.
- wire bond wires 110 are ball bonded with corresponding ball bonds 113 to conductive pads 140 along upper surface 104 .
- stitch, wedge, compliant, or other forms of BVA bonding may be used.
- copper wire bond wires 110 may be attached with ball bonds to upper surface 104 of substrate 103 for substrate-to-upper package routing.
- no conductive pad 140 may be associated with a wire bond wire 110 , such as for coupling to a ground plane or other voltage plane.
- Conductive pads 140 corresponding to wire bond wires 110 for electrical conductivity therebetween may be used for electrical communication with microelectronic package 100 and/or another microelectronic package as described below in additional detail.
- Ball bonds 113 may be spaced apart from one another. Even though only single rows 112 spaced apart from one another are illustratively depicted in FIG. 7-2 , in other implementations one or more rows 112 may be on one or more sides of region 111 defined by such rows 112 . However, for purposes of clarity by way of example and not limitation, it shall be assumed that a single row 112 is located on each side of region 111 for defining such region for receipt of a microelectronic device. Moreover, wire bond wires 110 may extend to a height above a back side surface of such a microelectronic device, as described below in additional detail.
- a microelectronic device having posts may be coupled in a face-down orientation to the upper surface of the substrate with first interconnects.
- operations at 803 and 804 may be in reverse order.
- microelectronic device 115 may be coupled to an upper surface 104 by injecting an underfill 168 prior to molding.
- a microelectronic device 115 may be coupled to upper surface 104 in region 111 .
- a microelectronic device 115 may be a bare IC or a packaged IC. Even though a single instance of an exemplary in-process microelectronic package 100 is illustratively depicted, two or more such in-process microelectronic packages 100 may be used. In another example, such in-process microelectronic package 100 may be a portion of a reconstituted wafer having multiple in-process microelectronic packages 100 .
- Microelectronic device 115 may be spaced apart from ball bonds 113 after coupling to upper surface 104 .
- Posts or pads 117 may be coupled to corresponding conductive pads 140 by bonding, such as copper-to-copper as in this example. Accordingly, soldering may be avoided for this interconnection by having copper conductive pads 140 aligned with lower surfaces of posts 117 .
- a copper-to-copper bond is illustratively depicted in FIG. 7 , in another implementation a conventional reflow bond using a solder material may be used.
- conductive posts or pads 117 may extend away therefrom.
- lower ends of electrically conductive posts or pads 117 are over and above conductive pads 140 of microelectronic device 100 .
- copper posts or pads 117 are used.
- another type of electrically conductive material may be used for posts or pads 117 .
- posts or pads 117 may be formed with a metalization layer used in forming microelectronic device 115 .
- microelectronic device 115 may be further coupled to upper surface 104 in a face-down or front side down orientation with an adhesive 716 .
- Adhesive 716 may be injected between posts or pads 117 underneath microelectronic device 115 . Additionally, adhesive 716 may extend into gaps between near surfaces of wire bond wires 110 and sidewalls of microelectronic device 115 . Adhesive 716 may be deposited on a back side surface 724 of a packaged die or bare die integrated circuit of microelectronic device 115 . Tips 123 of wire bond wires 110 may be above (i.e., higher than) an upper surface 725 of adhesive 716 , or at least higher than back side surface 724 .
- adhesive 716 may be an epoxy mold compound.
- adhesive 716 may be an underfill material which may extend into gaps between near surfaces of wire bond wires 110 and sidewalls of microelectronic device 115 .
- the substrate, the microelectronic device and the wire bond wires assemblage or combination may be molded with a molding material layer, which may include grinding or polishing such molding material layer.
- a molding material layer 120 is formed over upper surface 104 , microelectronic device 115 , and wire bond wires 110 .
- tips or upper ends 123 of wire bond wires 110 are above an upper surface 124 of molding material layer 120 .
- tips 123 of wire bond wires 110 may be exposed after forming molding material layer 120 .
- Surfaces 724 or 725 may or may not be covered by molding material layer 120 .
- molding layer 120 may cover tips 123 followed by a grind or etch back to reveal upper ends of wire bond wires 110 .
- tips 123 are exposed after forming molding material layer 120 .
- Molding material layer 120 may be for forming a reconstituted wafer having multiple in-process microelectronic packages 100 .
- an upper surface 134 of such a wire arch 114 may be embedded or protrude above an upper surface 124 of molding material layer 120 .
- carrier 101 may be removed along with adhesive 102 .
- adhesive 102 may be a releasable adhesive with temperature, UV rays, and/or other releasing agent.
- molding material layer 120 may be ground or polished down to an upper surface 724 or 725 . Removal of material such as by grinding may occur before or after removal of carrier 101 . After grinding, upper ends 130 , such as in FIG. 1-6 , of wire bond wires 110 may be exposed for interconnections respectively thereto in such an implementation. After grinding, molding material layer 120 may be left in place around posts 117 and remaining portions of wire bond wires 110 . However, for purposes of clarity by way of example and not limitation, it shall be assumed that tips 123 extend above an upper surface 124 of molding material layer 120 , and that grinding of tips 123 is not used.
- first and second bonds thereof may be electrically disconnected from one another for example by grinding a protruding upper surface 134 to cause a break in such wire arch 114 leaving two at least temporarily exposed upper ends along upper surface 134 .
- grinding may effectively form two separate wire bonds with different bond types, for example a ball bond 113 and a wedge or stitch bond 144 .
- the wire bond wires and the first interconnects may be interconnected via the conductive pads with a redistribution layer, where the redistribution layer has a first surface in contact with the conductive pads for the interconnecting.
- an RDL 135 may be formed with a bottom surface thereof interconnected to upper surfaces of conductive pads 140 for interconnecting at least a portion of wire bond wires 110 with at least a portion of posts 117 .
- RDL 135 may include one or more dielectric and conductive layers.
- a PCB or other circuit board may be interconnected to RDL 135 , as described below in additional detail.
- Traces or pads 169 of conductive layer 136 may interconnect upper surfaces of conductive pads 140 for coupling upper ends of wire bond wires 110 and posts 117 to one another. Accordingly, wire bond wires 110 may provide “vertical interconnects” along sides of a microelectronic device 115 for interconnecting substrate 103 and RDL 135 .
- second interconnects may be attached to a second surface opposite the first surface of the redistribution layer.
- balls or bumps 145 may be formed on exposed surfaces of traces or pads 169 of conductive layer 136 . Such balls or bumps 145 may be mechanically isolated from electrical conductivity by one or more dielectric layers 137 of an RDL 135 . However, such conductive traces or pads 169 of conductive layer 136 may be coupled for electrical conductivity with wire bond wires 110 , as well as one or more posts 117 , as previously described. Balls or bumps 145 for interconnection with posts 117 and not wire bond wires 110 are not illustratively depicted in this figure for purposes of clarity and not limitation.
- third interconnects of another microelectronic device may be coupled to the conductive pads for electrical conductivity with the wire bond wires.
- FIG. 9 there is shown a block diagram of a cross-sectional side view depicting an exemplary PoP microelectronic package 300 .
- a microelectronic package 100 which may still be in a reconstituted wafer or may be diced therefrom, has coupled on a back side thereof another microelectronic package 200 .
- PoP microelectronic package 300 may be package-to-package assembled, package-to reconstituted wafer assembled, or wafer/reconstituted wafer to reconstituted wafer assembled, with the last three involving subsequent dicing.
- microelectronic devices 115 and 201 are respective packaged integrated circuit dies; however, in another example either or both microelectronic devices 115 and 201 may be bare integrated circuit dies.
- Bumps or balls 155 of microelectronic package 200 may be physically coupled to tips 123 , or upper surfaces 130 in another implementation, of wire bond wires 110 of microelectronic package 100 for electrical conductivity between microelectronic packages 100 and 200 .
- PoP microelectronic package 300 may be coupled to a PCB or other circuit board 160 not part of PoP microelectronic package 300 .
- Overall height 400 of PoP microelectronic package 300 may be approximately 1.5 mm or less.
- an underfill (not shown) may be injected between microelectronic packages 100 and 200 .
- wire bond wires 110 may be disposed around a perimeter of microelectronic device 115 .
- FIG. 10 there is shown a block diagram of a cross-sectional side view depicting another exemplary PoP microelectronic package 300 .
- a microelectronic package 100 which may still be in a reconstituted wafer or may be diced therefrom, has formed on a back side thereof another RDL 165 .
- Another microelectronic package 200 may be coupled to an optional RDL 165 .
- a bottom surface of RDL 165 may be interconnected to upper surfaces 130 of wire bond wires 110 of microelectronic package 100 for electrical conductivity therewith.
- tips 123 of FIG. 7-5 may be ground down to surface 124 for example.
- Bumps or balls 155 of microelectronic package 200 may be physically coupled to conductive pads 164 of RDL 165 of microelectronic package 100 for electrical conductivity between microelectronic packages 100 and 200 .
- PoP microelectronic package 300 may be coupled to a PCB or other circuit board 160 not part of PoP microelectronic package 300 .
- Overall height 400 of PoP microelectronic package 300 may be approximately 1.5 mm or less.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
- This patent application is a divisional application of and claims benefit of priority to U.S. patent application Ser. No. 15/332,991, filed Oct. 24, 2016, which claims the benefit of priority to U.S. Provisional Patent Application No. 62/246,517, filed Oct. 26, 2015, and each of the aforementioned applications is incorporated by reference herein in its entirety for all purposes.
- The following description relates to integrated circuit (“IC”) packaging. More particularly, the following description relates to microelectronic packages for wafer-level chip scale packaging with fan-out.
- Microelectronic assemblies generally include one or more ICs, such as for example one or more packaged dies (“chips”) or one or more dies. One or more of such ICs may be mounted on a circuit platform, such as a wafer such as in wafer-level-packaging (“WLP”), printed board (“PB”), a printed wiring board (“PWB”), a printed circuit board (“PCB”), a printed wiring assembly (“PWA”), a printed circuit assembly (“PCA”), a package substrate, an interposer, or a chip carrier. Additionally, one IC may be mounted on another IC. An interposer may be an IC, and an interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device. Furthermore, an interposer may be formed like a PWB, namely without any circuit elements such as capacitors, resistors, or active devices. Additionally, an interposer includes at least one through-substrate-via.
- An IC may include conductive elements, such as pathways, traces, tracks, vias, contacts, pads such as contact pads and bond pads, plugs, nodes, or terminals for example, that may be used for making electrical interconnections with a circuit platform. These arrangements may facilitate electrical connections used to provide functionality of ICs. An IC may be coupled to a circuit platform by bonding, such as bonding traces or terminals, for example, of such circuit platform to bond pads or exposed ends of pins or posts or the like of an IC. Additionally, a redistribution layer (“RDL”) may be part of an IC to facilitate a flip-chip configuration, die stacking, or more convenient or accessible position of bond pads for example.
- More recently, fan-out wafer-level chip scale packaging (“FO-WCSP”) has been used to reduce costs. Semiconductor dies are formed, such as in their smallest configurations, and these dies or a combination of different dies may then be molded together in what is known as a reconstituted wafer. This reconstituted wafer provides more surface area for interconnects using WCSP in combination with a fan-out technology, such as a lead frame, ball grid array, or other fan-out technology. This allows for a larger pitch for interconnection to a PCB or other circuit board.
- Accordingly, it would be desirable and useful to provide for FO-WCSP for a package-on-package (“PoP”) configuration or other die stacking configuration.
- An apparatus relates generally to a microelectronic package for wafer-level chip scale packaging with fan-out. In such an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from a face of the microelectronic device facing away from the substrate. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate.
- A method relates generally to forming a microelectronic package for wafer-level chip scale packaging with fan-out. In such a method, obtained is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device having posts is coupled in a face-up orientation to the upper surface of the substrate. Wire bond wires are bonded to the upper surface of the substrate for extending away therefrom to a height above the posts. The substrate, the microelectronic device and the wire bond wires in combination is molded with a molding material layer. An uppermost portion of the wire bond wires and an uppermost portion of the molding material layer is removed to upper ends of the posts. Conductive pads are formed in the substrate. The conductive pads are for the wire bond wires for electrical conductivity between the wire bond wires and the conductive pads associated therewith.
- An apparatus relates generally to another microelectronic package for wafer-level chip scale packaging with fan-out. In such an apparatus, a substrate has an upper surface and a lower surface opposite the upper surface. The substrate includes conductive pads formed therein. Wire bond wires are coupled to and extend away from a first portion of the conductive pads along the upper surface for electrical conductivity between the wire bond wires and the first portion of the conductive pads associated therewith. A microelectronic device is coupled to a second portion of the conductive pads along the upper surface with the microelectronic device in a face-down orientation.
- A method relates generally to another microelectronic package for wafer-level chip scale packaging with fan-out. In such a method, obtained is a substrate having an upper surface and a lower surface opposite the upper surface. Conductive pads are formed in the substrate. Wire bond wires are bonded to the conductive pads along the upper surface of the substrate for extending away therefrom. The conductive pads are for the wire bond wires for electrical conductivity between the wire bond wires and the conductive pads associated therewith. A microelectronic device is coupled in a face-down orientation to the upper surface of the substrate with interconnects. The substrate, the microelectronic device and the wire bond wires in combination is molded with a molding material layer.
- Accompanying drawing(s) show exemplary embodiment(s) in accordance with one or more aspects of exemplary apparatus(es) or method(s). However, the accompanying drawings should not be taken to limit the scope of the claims, but are for explanation and understanding only.
-
FIGS. 1-1 through 1-9 are a progression of block diagrams of a cross-sectional side view depicting formation of an exemplary in-process microelectronic package for wafer-level chip scale package (“WCSP”) with fan-out (“FO”). -
FIG. 2 is a block diagram of a top view depicting an exemplary in-process microelectronic package. -
FIG. 3 is a block diagram of a top view depicting an exemplary in-process microelectronic package after forming balls on a redistribution layer (“RDL”). -
FIG. 4 is a block diagram of a cross-sectional side view depicting an exemplary package-on-package (“PoP”) microelectronic package. -
FIG. 5 is a block diagram of a cross-sectional side view depicting another exemplary PoP microelectronic package. -
FIG. 6 is a flow diagram depicting an exemplary process flow for forming a microelectronic package for WCSP with FO. -
FIGS. 7-1 through 7-6 are a progression of block diagrams of a cross-sectional side view depicting formation of another exemplary in-process microelectronic package for WCSP with fan-out FO. -
FIG. 8 is a flow diagram depicting an exemplary process flow for forming another microelectronic package for WCSP with fan-out FO. -
FIG. 9 is a block diagram of a cross-sectional side view depicting an exemplary PoP microelectronic package. -
FIG. 10 is a block diagram of a cross-sectional side view depicting another exemplary PoP microelectronic package. - In the following description, numerous specific details are set forth to provide a more thorough description of the specific examples described herein. It should be apparent, however, to one skilled in the art, that one or more other examples or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative examples the items may be different.
- Moreover, the features described herein as well as the numerical instances thereof are for purposes of conveying with clarity one or more aspects of exemplary apparatus(es) and/or method(s) described herein. These features are not to scale, and numerical instances thereof in an actual implementation may be the same or different from the numerical instances illustratively depicted. It should be understood that the word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any example or feature described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other examples or features.
- Generally, an integrated circuit die includes a substrate of a semiconductor material such as silicon (Si), gallium arsenide (GaAs), polymeric, ceramic, carbon-based substrates such as diamond, a silicon carbon (SiC), germanium (Ge), Si1-xGex, or the like. Even though a semiconductor substrate as provided from an in-process wafer is generally described below, any sheet or layer semiconductor material or dielectric material, such as ceramic or glass for example, may be used as a substrate.
- A substrate includes an upper surface and a lower surface that extend in lateral directions and are generally parallel to each other at a thickness thereof. Use of terms such as “upper” and “lower” or other directional terms is made with respect to the reference frame of the figures and is not meant to be limiting with respect to potential alternative orientations, such as in further assemblies or as used in various systems.
- An upper surface may generally be associated with what is referred to as a “front side” of an in-process wafer, and a lower surface may generally be associated with what is referred to as a “back side” of an in-process wafer. However, upper and lower may be reversed during processing. Along those lines, a front-side of an in-process wafer may be used for forming what is referred to as front-end-of-line (“FEOL”) structures and back-end-of-line (“BEOL”) structures. Generally, FEOL structures may include shallow trench isolations (“STI”), transistor gates, transistor source/drain regions (not shown), transistor gate dielectrics (not shown), contact etch stop layer (“CESL”; not shown), a pre-metallization dielectric or pre-metal dielectric (“PMD”), and contact plugs, among other FEOL structures. A PMD may be composed of one or more layers. Generally, BEOL structures may include one or more inter-level dielectrics (“ILDs”) and one or more levels of metallization (“M”). Each ILD may be composed of one or more dielectric layers, and each metal or metallization level may be composed of one or more metal layers, as well as one or more barrier and/or liner layers. Additionally, metal from a metallization level may extend through one or more ILDs, as is known. A passivation level may be formed on a last metallization layer. Such passivation level may include one or more dielectric layers, and further may include an anti-reflective coating (“ARC”). Furthermore, a redistribution layer (“RDL”) may be formed on such passivation level. Conventionally, an RDL may include: a dielectric layer, such as a polyimide layer for example; another metal layer on such dielectric layer connected to a bond pad of a metal layer of a last metallization level; and another dielectric layer, such as another polyimide layer for example, over such RDL metal layer while leaving a portion thereof exposed to provide another bond pad. A terminal opening may expose such other bond pad of such RDL metal layer. Thereafter, a solder bump or wire bond may be conventionally coupled to such bond pad.
- Balls or other discrete interconnects may be respectively formed on bonding pads, where such pads may be formed on or as part of metal layer. Balls may be formed of a bonding material, such as solder or other bonding material. Balls may be microbumps, C4 bumps, ball grid array (“BGA”) balls, or some other die interconnect structure. In some applications, metal layer may be referred to as a landing pad. BGA, lead frame, and other types of interconnects may be used as fan-out technologies.
- The following description is for fan-out wafer-level chip scale packaging (“FO-WCSP for a stacked or 3D device, such as for a package-on-package PoP device. Along those lines, wire bond wires are used for interconnection with an upper package of a PoP device. Use of wire bond wires as described below may eliminate a substrate and/or corresponding through substrate vias used in a conventionally manufactured PoP device with fan-out. Thus, a lower cost and thinner PoP device with fan-out may be manufactured using wire bond wires as described hereinbelow. Along those lines, a PoP device with fan-out using wire bond wires, such as of a BVA™ technology, may be used in mobile devices and other small form factor applications.
-
FIGS. 1-1 through 1-9 (collectively and singly “FIG. 1 ”) are a progression of block diagrams of a cross-sectional side view depicting formation of an exemplary in-process microelectronic package 100 for wafer-level chip scale package (“WCSP”) with fan-out (“FO”).FIGS. 1, 4 and 5 hereof are described with simultaneous reference toFIG. 6 , where there is shown a flow diagram depicting anexemplary process flow 600 for forming amicroelectronic package 100 for WCSP with FO. - At 601, a substrate having an upper surface and a lower surface opposite the upper surface is obtained. With reference to
FIG. 1-1 , in-process microelectronic package 100 includes acarrier 101 coupled to afoil substrate layer 103 with areleasable adhesive 102. In this example implementation,carrier 101 is a copper carrier, and foilsubstrate layer 103 is copper foil layer. However, in other implementations,carrier 101 may be silicon, glass, laminate, or other dielectric and/or metal carrier material.Carrier 101 may or may not be opaque, such as with respect to UV rays for example. Along those lines,releasable adhesive 102 may be a thermal or UV released adhesive for example. Moreover, in other implementations,foil substrate layer 103 may be another electrical conductor, such as gold, platinum or other thin film metal for example. Foil substrate layer (“substrate”) 103 has anupper surface 104 and alower surface 105 opposite suchupper surface 104. - At 602, wire bond wires may be bonded to the upper surface of the substrate for extending away therefrom to a height above posts of a microelectronic device. With reference to
FIG. 1-2 ,wire bond wires 110 are coupled to and extend away fromupper surface 104. In this example, copperwire bond wires 110 are used. However, in another implementation, another form ofwire bond wires 110 may be used, such as aluminum, silver, gold, palladium-coated copper (“PCC”), core wires, or other forms of wire bond wire.Wire bond wires 110 may be BVA™ bonded wires. Columns and/or rows (“rows”) 112 ofwire bond wires 110 may be spaced apart from one another to define aregion 111 and may be coupled toupper surface 104. - In this example,
wire bond wires 110 are ball bonded withcorresponding ball bonds 113 toupper surface 104. However, in another implementation, stitch, wedge, compliant, or other forms of BVA bonding may be used. For this implementation, which does not use soldering ofwire bond wires 110, copperwire bond wires 110 may be attached with ball bonds toupper surface 104 ofsubstrate 103 for substrate-to-upper package routing. - In another example, a “wired-arch” or “wired-loop”
wire bond wire 114 may be formed onupper surface 104 such that a first bond, such as aball bond 113 for example, is formed at a first location onupper surface 104 and a second bond, such as a wedge or stitchbond 144, is formed at a second location onupper surface 104 spaced apart from such first location by at least approximately 10-400 microns for example. Anupper surface 134 of such a “wired-arch”wire bond wire 114 may be used for interconnection, as described elsewhere herein. However, for purposes of clarity by way of example and not limitation, generally onlywire bond wires 110, and not wired-archwire bond wires 114, are further described. -
Ball bonds 113, as well aswire bond wires 110 drawn therefrom, may be spaced apart from one another. Even though onlysingle rows 112 spaced apart from one another are illustratively depicted inFIG. 1-2 , in other implementations one ormore rows 112 may be on one or more sides ofregion 111 defined bysuch rows 112. However, for purposes of clarity by way of example and not limitation, it shall be assumed that asingle row 112 is located on each side ofregion 111 for defining such region for receipt of a microelectronic device. Moreover,wire bond wires 110 may extend to a height above posts of such a microelectronic device, as described below in additional detail. - At 603, a microelectronic device having posts may be coupled in a face-up orientation to the upper surface of the substrate. In another implementation, operations at 602 and 603 may be in reverse order. With reference to
FIG. 1-3 , amicroelectronic device 115 may be coupled toupper surface 104 with an adhesive or anunderfill 116 inregion 111.Microelectronic device 115 may be spaced apart fromball bonds 113 after coupling toupper surface 104. Adhesive 116 may be a compliant material after curing, such as a polyimide (“PI”) or a polybenzoxazole (“PBO”) for example, with a modulus of elasticity of less than approximately 4 gigapascals (“GPa”). -
Microelectronic device 115 may be coupled toupper surface 104 in a face-up or front side up orientation. Generally, a face ofmicroelectronic device 115 having posts extending away therefrom, such a face may be facing away from such substrate to whichmicroelectronic device 115 is coupled in this implementation. Even thoughwire bond wires 110 are attached toupper surface 104 in this example prior to couplingmicroelectronic device 115, this order may be reversed in this or another implementation.Microelectronic device 115 may be a packaged or bare integrated circuit die formed using a Si, GaAs, or other semiconductor wafer. Optionally,microelectronic device 115 may be a passive device. - Along an
upper surface 118 ofmicroelectronic device 115, conductive posts orpads 117 ofmicroelectronic device 115 extend away from a front side or face thereof, namelyupper surface 118. In this example, upper ends 122 of electrically conductive posts orpads 117 are over and above anupper surface 118 ofmicroelectronic device 115. In this example, copper posts orpads 117 are used. However, in another example, another type of electrically conductive material may be used for posts orpads 117. Furthermore, a structure other than posts orpads 117, such as stud bumps for example, may be attached alongupper surface 118 ofmicroelectronic device 115. Stud bumps may be a ball bonds, such as a ball bond-only portion of wire bonds. Additionally, posts orpads 117 may be formed with a metalization layer used in formingmicroelectronic device 115. For purposes of clarity by way of example and not limitation, it shall be assumed that copper posts 117 are used for interconnects. - Even though a single instance of an exemplary in-
process microelectronic package 100 is illustratively depicted, two or more of such in-processmicroelectronic packages 100 may be used. In another example, such in-process microelectronic package 100 may be a portion of a reconstituted wafer having multiple in-process microelectronic packages 100. A reconstituted wafer typically consist of dies coupled to one another by a molding material in-between them to form a wafer or substrate. - At 604, the substrate, the microelectronic device and the wire bond wires assemblage or combination may be molded with a molding material layer, which may include grinding or polishing of a surface of such molding material layer. With reference to
FIG. 1-4 , amolding material layer 120 may be formed overupper surface 104,microelectronic device 115 andwire bond wires 110. In this example, tips orupper ends 123 ofwire bond wires 110 are above anupper surface 124 ofmolding material layer 120. For a wired-archwire bond wire 114, anupper surface 134 of such awire arch 114 may be embedded or protrude above anupper surface 124 ofmolding material layer 120. Along those lines,wire bond wires 110 may extend above upper ends 122 ofposts 117. Thus, whiletips 123 ofwire bond wires 110, orupper surface 134 of wired-archwire bond wires 114, may be exposed after formingmolding material layer 120, upper ends 122 ofpost 117 are covered bymolding material layer 120. In another implementation,molding layer 120 may covertips 123, orupper surfaces 134, as generally indicated by dashedline 121. For purposes of clarity by way of example and not limitation, it shall be assumed thattips 123 are exposed after formingmolding material layer 120.Molding material layer 120 may be for forming a reconstituted wafer having multiple in-process microelectronic packages 100. - With reference to
FIG. 1-5 , after molding,carrier 101 may be removed along withadhesive 102. Again, adhesive 102 may be a releasable adhesive using temperature, UV rays, and/or other releasing agent. - With reference to
FIG. 1-6 ,molding material layer 120, as well astips 123 ofwire bond wires 110, may be ground or polished down to expose upper ends 122. Removal of material such as by grinding may occur before or after removal ofcarrier 101. After grinding, upper ends 130 ofwire bond wires 110, as well as upper ends 122 ofposts 117, may be exposed for interconnections respectively thereto. However, after grinding,molding material layer 120 may be left in place aroundposts 117 and remaining portions ofwire bond wires 110. For a wired-archwire bond wire 114, after grinding ofupper surface 134 of such awire arch 114, first and second bonds thereof may be electrically disconnected from one another for example by grinding a protrudingupper surface 134 to cause a break insuch wire arch 114 leaving two at least temporarily exposed upper ends alongupper surface 134. Along those lines, grinding may effectively form two separate wire bonds with different bond types, for example aball bond 113 and a wedge or stitchbond 144. - With reference to
FIG. 2 , where there is shown a block diagram of a top view depicting an exemplary in-process microelectronic package 100. For this implementation,upper surface 124 may be generally co-planar withupper ends Posts 117 may be inregion 111 defined by rows and columns ofwire bond wires 110 surroundingmicroelectronic device 115. - At 605, the wire bond wires and the posts may be interconnected with a redistribution layer. With reference to
FIG. 1-7 , a redistribution layer (“RDL”) 135 may be formed with a bottom surface thereof interconnected toupper ends 122 ofposts 117 andupper ends 130 ofwire bond wires 110 for interconnecting at least a portion ofwire bond wires 110 with at least a portion ofposts 117. Even though a single layer of adielectric layer 137 and aconductive layer 136 is illustratively depicted forRDL 135, in other implementations,RDL 135 may include one or more dielectric and conductive layers. Along those lines, an integrated circuit die may be interconnected to conductive pads on a lower surface of a substrate, as described below in additional detail. -
RDL 135 may be entirely formed onupper surface 124 ofmolding material layer 120, as well as being interconnect toupper ends 130 ofwire bond wires 110 and toupper ends 122 ofposts 117. In a conventional FOWLP package, an RDL is formed on top of a Si substrate and then surrounded with molding material, and so a large stress field is developed around a transition area or “triple point” where such RDL, Si substrate and molding material intersect. In contrast, by covering an area of amicroelectronic device 115 withmolding material layer 120 as described herein,RDL 135 avoids a conventional “triple point.” - Traces or
pads 169 ofconductive layer 136 may interconnect upper ends 122 ofposts 117 andupper ends 130 ofwire bond wires 110. Accordingly,wire bond wires 110 may provide “vertical interconnects” along sides of a microelectronic device for interconnectingsubstrate 103 andRDL 135. Suchwire bond wires 110 may additionally be interconnected tocorresponding posts 117 ofmicroelectronic device 115. - At 606, conductive pads may be formed in the substrate electrically isolated from a remainder of the substrate, where the conductive pads correspond to the wire bond wires for electrical conductivity between the wire bond wires and the conductive pads corresponding thereto. With reference to
FIG. 1-8 , in-process microelectronic package 100 may be flipped for patterning and etching alower surface 105 ofsubstrate 103, namely a back side ofmicroelectronic package 100. In another implementation, a direct write etch may be used onlower surface 105. - Through
substrate channels 142 may be formed fromlower surface 105 toupper surface 104 with astop molding layer 120 for example. Throughsubstrate channels 142 may be at least partially, if not completely, filled with adielectric material 143, such as a polyimide for example.Conductive pads 140 may be defined by such throughsubstrate channels 142 incopper substrate 103 for this example implementation. Conductive pads orconductive islands 140 may have previously been coupled towire bond wires 110, as previously described with reference to bonding toupper surface 104 ofsubstrate 103.Conductive pads 140 may be defined insubstrate 103 as respective islands of a material of such substrate. Even thoughconductive pads 140 are illustratively depicted near an outer edge ofmicroelectronic package 100,conductive pads 140 may be formed in generally a middle region (“remainder”) 141, such as directly belowmicroelectronic device 115 for example. -
Conductive pads 140 may be formed usingsubstrate 103 material for electrical isolation from aremainder 141 ofsubstrate 103.Such remainder 141 may be used as a ground plane. In some instances, noconductive pad 140 may be associated with awire bond wire 110 for coupling to a ground plane, or other voltage plane.Conductive pads 140 corresponding to wirebond wires 110 for electrical conductivity therebetween may be used for electrical communication withmicroelectronic package 100 and/or another microelectronic package as described below in additional detail. Although not illustratively depicted inFIG. 1 , another redistribution layer RDL may be formed on a top surface ofsubstrate 103. This RDL, likeRDL 135, may include one or more dielectric and conductive layers. - At 607, first interconnects may be attached to a top surface of the redistribution layer for electrical conductivity with the posts and the wire bond wires. With reference to
FIG. 1-9 , balls or bumps 145 may be formed on exposed surfaces of traces orpads 169 ofconductive layer 136. Such balls or bumps 145 may be mechanically isolated from electrical conductivity by one or moredielectric layers 137 of anRDL 135. However, such conductive traces orpads 169 ofconductive layer 136 may be coupled for electrical conductivity withwire bond wires 110, as well as one ormore posts 117, as previously described. Balls or bumps 145 for interconnection withposts 117 and not wirebond wires 110 are not illustratively depicted in this figure for purposes of clarity and not limitation. - With reference to
FIG. 3 , where there is shown a block diagram of a top view depicting an exemplary in-process microelectronic package 100 after formingballs 145 onRDL 135. Some ofballs 145 may be associated with pads or traces 169 ofconductive layer 136 for coupling to wire bond wires. Others ofballs 145 may be associated with pads or traces 169 ofconductive layer 136 not associated withwire bond wires 110 and associated withposts 117. Moreover, even though generally a one-to-one correspondence betweenwire bond wires 110 coupled toposts 117 is illustratively depicted,wire bond wires 110 may be interconnected to more than onepost 117. In one or more instances, there may not be a direct coupling for an electrical connection between at least onewire bond wire 110 and at least onepost 117. -
Pitch 148 ofpads 169 ofconductive layer 136 forballs 145 associated withwire bond wires 110 may be in a range of approximately 350 to 600 microns or less for correspondence with pitch of contacts on a PCB or other circuit board. Along those lines, minimum pitch ofposts 117 andwire bond wires 110 may be as small as 5 microns and as small as 20 microns, respectively. AnRDL 135 may effectively causepitch 148 to be at least approximately the same as for example a BGA pitch of a circuit board, such as approximately 350 microns. - At 608, second interconnects of another microelectronic device may be coupled to the conductive pads for electrical conductivity with the wire bond wires. With reference to
FIG. 4 , there is shown a block diagram of a cross-sectional side view depicting an exemplary PoPmicroelectronic package 300. In this example, amicroelectronic package 100, which may still be in a reconstituted wafer or may be diced therefrom, has coupled on the back side thereof anothermicroelectronic package 200. In other words, PoPmicroelectronic package 300 may be package-to-package assembled, package-to reconstituted wafer assembled, or wafer/reconstituted wafer to reconstituted wafer assembled, with the last three involving subsequent dicing. In this example,microelectronic devices microelectronic devices microelectronic package 100 may be an applications processor or a baseband processor or any other logic device, andmicroelectronic package 200 may be a memory device, such as with one or more types of memory die including NAND, DRAM, memory controller, and/or the like. - Bumps or
balls 155 ofmicroelectronic package 200 may be physically coupled toconductive pads 140 ofmicroelectronic package 100 for electrical conductivity betweenmicroelectronic packages microelectronic package 300 may be coupled to a PCB orother circuit board 160 which is not part of PoPmicroelectronic package 300.Overall height 400 of PoPmicroelectronic package 300 may be approximately 1.5 mm or less. Optionally, an underfill (not shown) may be injected betweenmicroelectronic packages - With reference to
FIG. 5 , there is shown a block diagram of a cross-sectional side view depicting another exemplary PoPmicroelectronic package 300. In this example, amicroelectronic package 100, which may still be in a reconstituted wafer or may be diced therefrom, has formed on a back side thereof anotherRDL 165. Anothermicroelectronic package 200 may be coupled to anoptional RDL 165. Along those lines, a bottom surface ofRDL 165 may be interconnected toconductive pads 140 ofmicroelectronic package 100 for electrical conductivity therewith. Either or both ofRDLs 135 and/or 165 may have one or more metal layers and/or one or more dielectric layers. - Bumps or
balls 155 ofmicroelectronic package 200 may be physically coupled toconductive pads 164 ofRDL 165 ofmicroelectronic package 100 for electrical conductivity betweenmicroelectronic packages microelectronic package 300 may be coupled to a PCB orother circuit board 160 not part of PoPmicroelectronic package 300.Overall height 400 of PoPmicroelectronic package 300 may be approximately 1.5 mm or less.Wire bond wires 110 may be disposed around a perimeter ofmicroelectronic device 115, which may be packaged integrated circuit die or a bare integrated circuit die. -
FIGS. 7-1 through 7-6 (collectively and singly “FIG. 7 ”) are a progression of block diagrams of a cross-sectional side view depicting formation of another exemplary in-process microelectronic package 100 for WCSP with fan-out FO.FIGS. 7, 9 and 10 are hereafter described with simultaneous reference toFIG. 8 , where there is shown a flow diagram depicting anexemplary process flow 800 for forming such othermicroelectronic package 100 for WCSP with fan-out FO. - At 601, a substrate having an upper surface and a lower surface opposite the upper surface is obtained. With reference to
FIG. 7-1 , in-process microelectronic package 100 includes acarrier 101 coupled to afoil substrate layer 103 with areleasable adhesive 102. In this example implementation,carrier 101 is a copper carrier, and foilsubstrate layer 103 is copper foil layer. However, in other implementations,carrier 101 may be silicon, glass, laminate, or other metal and/or dielectric carrier material.Carrier 101 may or may not be opaque, such as with respect to UV rays for example. Along those lines,releasable adhesive 102 may be a thermal or UV released adhesive for example. Moreover, in other implementations,foil substrate layer 103 may be another electrical conductor, such as gold, platinum or other thin film metal for example. Foil substrate layer (“substrate”) 103 has anupper surface 104 and alower surface 105 opposite suchupper surface 104. - At 802, conductive pads or conductive islands may be formed in the substrate electrically isolated from a remainder of the substrate. The conductive pads may correspond to the wire bond wires for electrical conductivity between the wire bond wires and the conductive pads corresponding thereto as described below in additional detail.
- With reference to
FIG. 7-1 , in-process microelectronic package 100 may have anupper surface 104 ofsubstrate 103 directly written with a laser drill. In another implementation, patterning and etching may be used onupper surface 104. Throughsubstrate channels 142 may be formed fromupper surface 104 down tolower surface 105. - Through
substrate channels 142 may be at least partially, if not completely, be filled with adielectric material 143, such as a polyimide for example.Conductive pads 140 may be defined by such throughsubstrate channels 142 incopper substrate 103 for this example implementation.Conductive pads 140 may be defined insubstrate 103 as respective islands of a material of such substrate. In another implementation,substrate channels 142 may not be filled with any material, andconductive pads 140 may only be attached tocarrier 101 viaadhesive 102. -
Conductive pads 140 may be formed usingsubstrate 103 material for electrical isolation from a remainder ofsubstrate 103, and such remainder ofsubstrate 103 not used forconductive pads 140 may be used as a ground plane (not shown in this figure). However, for a face-down configuration as described with reference toFIG. 7 for example,conductive pads 140 may be formed for interconnection with posts orpads 117 of amicroelectronic device 115, as described below in additional detail. - At 803, wire bond wires may be bonded to the upper surface of the substrate for extending away therefrom to a height above a microelectronic device, as described below in additional detail. With reference to
FIG. 7-2 ,wire bond wires 110 are coupled to and extend away fromupper surface 104. In this example, copperwire bond wires 110 are used. However, in another implementation, another form ofwire bond wires 110 may be used, such as aluminum, silver, gold, palladium-coated copper (“PCC”), core wires, or other forms of wire bond wire.Wire bond wires 110 may be BVA™ bonded wires. - Again, in another example, a “wired-arch” or “wired-loop”
wire bond wire 114 may be formed onupper surface 104 such that a first bond, such as aball bond 113 for example, is formed at a first location onupper surface 104 and a second bond, such as a wedge or stitchbond 144, is formed at a second location onupper surface 104 spaced apart from such first location by at least approximately 10 microns for example. Anupper surface 134 of such a “wired-arch”wire bond wire 114 may be used for interconnection, as described elsewhere herein. However, for purposes of clarity by way of example and not limitation, generally onlywire bond wires 110, and not wired-archwire bond wires 114, are further described. - Columns and/or rows (“rows”) 112 of
wire bond wires 110 may be spaced apart from one another to define aregion 111 and may be coupled toupper surface 104. Such spacing betweenwire bond wires 110 may, though need not be uniform. For example, a denser spacing may be used in some locations as compared with other locations, as may vary from application to application depending on routing. Moreover, routing, including via RDL, may be denser in some areas as compare with other areas corresponding to layout of an integrated circuit die. Having the flexibility to havewire bond wires 110 use different spacings may be useful to accommodate shorter path distances and/or pin layout of a package. - In this example,
wire bond wires 110 are ball bonded withcorresponding ball bonds 113 toconductive pads 140 alongupper surface 104. However, in another implementation, stitch, wedge, compliant, or other forms of BVA bonding may be used. For this implementation, which does not use soldering ofwire bond wires 110, copperwire bond wires 110 may be attached with ball bonds toupper surface 104 ofsubstrate 103 for substrate-to-upper package routing. - In some instances, no
conductive pad 140 may be associated with awire bond wire 110, such as for coupling to a ground plane or other voltage plane.Conductive pads 140 corresponding to wirebond wires 110 for electrical conductivity therebetween may be used for electrical communication withmicroelectronic package 100 and/or another microelectronic package as described below in additional detail. -
Ball bonds 113, as well aswire bond wires 110 drawn therefrom, may be spaced apart from one another. Even though onlysingle rows 112 spaced apart from one another are illustratively depicted inFIG. 7-2 , in other implementations one ormore rows 112 may be on one or more sides ofregion 111 defined bysuch rows 112. However, for purposes of clarity by way of example and not limitation, it shall be assumed that asingle row 112 is located on each side ofregion 111 for defining such region for receipt of a microelectronic device. Moreover,wire bond wires 110 may extend to a height above a back side surface of such a microelectronic device, as described below in additional detail. - At 804, a microelectronic device having posts may be coupled in a face-down orientation to the upper surface of the substrate with first interconnects. In another implementation, operations at 803 and 804 may be in reverse order. Optionally,
microelectronic device 115 may be coupled to anupper surface 104 by injecting anunderfill 168 prior to molding. - With reference to
FIG. 7-3 , amicroelectronic device 115 may be coupled toupper surface 104 inregion 111. Amicroelectronic device 115 may be a bare IC or a packaged IC. Even though a single instance of an exemplary in-process microelectronic package 100 is illustratively depicted, two or more such in-processmicroelectronic packages 100 may be used. In another example, such in-process microelectronic package 100 may be a portion of a reconstituted wafer having multiple in-process microelectronic packages 100. -
Microelectronic device 115 may be spaced apart fromball bonds 113 after coupling toupper surface 104. Posts orpads 117 may be coupled to correspondingconductive pads 140 by bonding, such as copper-to-copper as in this example. Accordingly, soldering may be avoided for this interconnection by having copperconductive pads 140 aligned with lower surfaces ofposts 117. Although a copper-to-copper bond is illustratively depicted inFIG. 7 , in another implementation a conventional reflow bond using a solder material may be used. - Along a lower front side surface of
microelectronic device 115, conductive posts orpads 117 may extend away therefrom. In this example, lower ends of electrically conductive posts orpads 117 are over and aboveconductive pads 140 ofmicroelectronic device 100. In this example, copper posts orpads 117 are used. However, in another example, another type of electrically conductive material may be used for posts orpads 117. Additionally, posts orpads 117 may be formed with a metalization layer used in formingmicroelectronic device 115. For purposes of clarity by way of example and not limitation, it shall be assumed that copper posts 117 are used for interconnects. - With reference to
FIG. 7-4 ,microelectronic device 115 may be further coupled toupper surface 104 in a face-down or front side down orientation with an adhesive 716. Adhesive 716 may be injected between posts orpads 117 underneathmicroelectronic device 115. Additionally, adhesive 716 may extend into gaps between near surfaces ofwire bond wires 110 and sidewalls ofmicroelectronic device 115. Adhesive 716 may be deposited on aback side surface 724 of a packaged die or bare die integrated circuit ofmicroelectronic device 115.Tips 123 ofwire bond wires 110 may be above (i.e., higher than) anupper surface 725 of adhesive 716, or at least higher than backside surface 724. In another example, adhesive 716 may be an epoxy mold compound. In yet another example, adhesive 716 may be an underfill material which may extend into gaps between near surfaces ofwire bond wires 110 and sidewalls ofmicroelectronic device 115. - At 805, the substrate, the microelectronic device and the wire bond wires assemblage or combination may be molded with a molding material layer, which may include grinding or polishing such molding material layer. With reference to
FIG. 7-5 , amolding material layer 120 is formed overupper surface 104,microelectronic device 115, andwire bond wires 110. In this example, tips orupper ends 123 ofwire bond wires 110 are above anupper surface 124 ofmolding material layer 120. Thus,tips 123 ofwire bond wires 110 may be exposed after formingmolding material layer 120.Surfaces molding material layer 120. In another implementation,molding layer 120 may covertips 123 followed by a grind or etch back to reveal upper ends ofwire bond wires 110. For purposes of clarity by way of example and not limitation, it shall be assumed thattips 123 are exposed after formingmolding material layer 120.Molding material layer 120 may be for forming a reconstituted wafer having multiple in-process microelectronic packages 100. - For a wired-arch
wire bond wire 114, anupper surface 134 of such awire arch 114 may be embedded or protrude above anupper surface 124 ofmolding material layer 120. After molding,carrier 101 may be removed along withadhesive 102. Again, adhesive 102 may be a releasable adhesive with temperature, UV rays, and/or other releasing agent. - In another implementation,
molding material layer 120, as well astips 123 ofwire bond wires 110, or an upperarched surface 134 of wired-archwire bond wires 114, may be ground or polished down to anupper surface carrier 101. After grinding, upper ends 130, such as inFIG. 1-6 , ofwire bond wires 110 may be exposed for interconnections respectively thereto in such an implementation. After grinding,molding material layer 120 may be left in place aroundposts 117 and remaining portions ofwire bond wires 110. However, for purposes of clarity by way of example and not limitation, it shall be assumed thattips 123 extend above anupper surface 124 ofmolding material layer 120, and that grinding oftips 123 is not used. For a wired-archwire bond wire 114, after grinding ofupper surface 134 of such awire arch 114, first and second bonds thereof may be electrically disconnected from one another for example by grinding a protrudingupper surface 134 to cause a break insuch wire arch 114 leaving two at least temporarily exposed upper ends alongupper surface 134. Along those lines, grinding may effectively form two separate wire bonds with different bond types, for example aball bond 113 and a wedge or stitchbond 144. - At 806, the wire bond wires and the first interconnects may be interconnected via the conductive pads with a redistribution layer, where the redistribution layer has a first surface in contact with the conductive pads for the interconnecting. With reference to
FIG. 7-6 , anRDL 135 may be formed with a bottom surface thereof interconnected to upper surfaces ofconductive pads 140 for interconnecting at least a portion ofwire bond wires 110 with at least a portion ofposts 117. Even though asingle dielectric layer 137 and a singleconductive layer 136 are illustratively depicted forRDL 135, inother implementations RDL 135 may include one or more dielectric and conductive layers. Along those lines, a PCB or other circuit board may be interconnected toRDL 135, as described below in additional detail. - Traces or
pads 169 ofconductive layer 136 may interconnect upper surfaces ofconductive pads 140 for coupling upper ends ofwire bond wires 110 andposts 117 to one another. Accordingly,wire bond wires 110 may provide “vertical interconnects” along sides of amicroelectronic device 115 for interconnectingsubstrate 103 andRDL 135. - At 807, second interconnects may be attached to a second surface opposite the first surface of the redistribution layer. With continued reference to
FIG. 7-6 , balls or bumps 145 may be formed on exposed surfaces of traces orpads 169 ofconductive layer 136. Such balls or bumps 145 may be mechanically isolated from electrical conductivity by one or moredielectric layers 137 of anRDL 135. However, such conductive traces orpads 169 ofconductive layer 136 may be coupled for electrical conductivity withwire bond wires 110, as well as one ormore posts 117, as previously described. Balls or bumps 145 for interconnection withposts 117 and not wirebond wires 110 are not illustratively depicted in this figure for purposes of clarity and not limitation. - At 808, third interconnects of another microelectronic device may be coupled to the conductive pads for electrical conductivity with the wire bond wires. With reference to
FIG. 9 , there is shown a block diagram of a cross-sectional side view depicting an exemplary PoPmicroelectronic package 300. In this example, amicroelectronic package 100, which may still be in a reconstituted wafer or may be diced therefrom, has coupled on a back side thereof anothermicroelectronic package 200. In other words, PoPmicroelectronic package 300 may be package-to-package assembled, package-to reconstituted wafer assembled, or wafer/reconstituted wafer to reconstituted wafer assembled, with the last three involving subsequent dicing. In this example,microelectronic devices microelectronic devices - Bumps or
balls 155 ofmicroelectronic package 200 may be physically coupled totips 123, orupper surfaces 130 in another implementation, ofwire bond wires 110 ofmicroelectronic package 100 for electrical conductivity betweenmicroelectronic packages microelectronic package 300 may be coupled to a PCB orother circuit board 160 not part of PoPmicroelectronic package 300.Overall height 400 of PoPmicroelectronic package 300 may be approximately 1.5 mm or less. Optionally, an underfill (not shown) may be injected betweenmicroelectronic packages wire tips 123 may thus avoid having to introduce another metal layer, such as another copper layer on a back side surface, such as either ofsurfaces FIG. 7-4 , for example. Again,wire bond wires 110 may be disposed around a perimeter ofmicroelectronic device 115. - With reference to
FIG. 10 , there is shown a block diagram of a cross-sectional side view depicting another exemplary PoPmicroelectronic package 300. In this example, amicroelectronic package 100, which may still be in a reconstituted wafer or may be diced therefrom, has formed on a back side thereof anotherRDL 165. Anothermicroelectronic package 200 may be coupled to anoptional RDL 165. Along those lines, a bottom surface ofRDL 165 may be interconnected toupper surfaces 130 ofwire bond wires 110 ofmicroelectronic package 100 for electrical conductivity therewith. Along those lines,tips 123 ofFIG. 7-5 may be ground down tosurface 124 for example. - Bumps or
balls 155 ofmicroelectronic package 200 may be physically coupled toconductive pads 164 ofRDL 165 ofmicroelectronic package 100 for electrical conductivity betweenmicroelectronic packages microelectronic package 300 may be coupled to a PCB orother circuit board 160 not part of PoPmicroelectronic package 300.Overall height 400 of PoPmicroelectronic package 300 may be approximately 1.5 mm or less. - While the foregoing describes exemplary embodiment(s) in accordance with one or more aspects of the invention, other and further embodiment(s) in accordance with the one or more aspects of the invention may be devised without departing from the scope thereof, which is determined by the claim(s) that follow and equivalents thereof. Claim(s) listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/201,569 US20190096861A1 (en) | 2015-10-26 | 2018-11-27 | Microelectronic package for wafer-level chip scale packaging with fan-out |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562246517P | 2015-10-26 | 2015-10-26 | |
US15/332,991 US10181457B2 (en) | 2015-10-26 | 2016-10-24 | Microelectronic package for wafer-level chip scale packaging with fan-out |
US16/201,569 US20190096861A1 (en) | 2015-10-26 | 2018-11-27 | Microelectronic package for wafer-level chip scale packaging with fan-out |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/332,991 Division US10181457B2 (en) | 2015-10-26 | 2016-10-24 | Microelectronic package for wafer-level chip scale packaging with fan-out |
Publications (1)
Publication Number | Publication Date |
---|---|
US20190096861A1 true US20190096861A1 (en) | 2019-03-28 |
Family
ID=58559010
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/332,991 Active US10181457B2 (en) | 2015-10-26 | 2016-10-24 | Microelectronic package for wafer-level chip scale packaging with fan-out |
US16/201,569 Abandoned US20190096861A1 (en) | 2015-10-26 | 2018-11-27 | Microelectronic package for wafer-level chip scale packaging with fan-out |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/332,991 Active US10181457B2 (en) | 2015-10-26 | 2016-10-24 | Microelectronic package for wafer-level chip scale packaging with fan-out |
Country Status (1)
Country | Link |
---|---|
US (2) | US10181457B2 (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101128063B1 (en) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | Package-on-package assembly with wire bonds to encapsulation surface |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US9911718B2 (en) * | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9923011B2 (en) * | 2016-01-12 | 2018-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with stacked semiconductor dies |
US10461042B2 (en) * | 2016-01-31 | 2019-10-29 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor module |
US10720339B2 (en) * | 2016-05-10 | 2020-07-21 | Agency For Science, Technology And Research | Fan-out wafer-level packaging method and the package produced thereof |
US10461022B2 (en) | 2017-08-21 | 2019-10-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and manufacturing method thereof |
US11764187B2 (en) * | 2017-09-29 | 2023-09-19 | Intel Corporation | Semiconductor packages, and methods for forming semiconductor packages |
WO2019163580A1 (en) * | 2018-02-20 | 2019-08-29 | 株式会社村田製作所 | Semiconductor device and method for manufacturing semiconductor device |
US10818635B2 (en) | 2018-04-23 | 2020-10-27 | Deca Technologies Inc. | Fully molded semiconductor package for power devices and method of making the same |
US10593647B2 (en) | 2018-06-27 | 2020-03-17 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
US11107791B2 (en) * | 2019-03-14 | 2021-08-31 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US11145627B2 (en) | 2019-10-04 | 2021-10-12 | Winbond Electronics Corp. | Semiconductor package and manufacturing method thereof |
US20210125959A1 (en) * | 2019-10-24 | 2021-04-29 | Texas Instruments Incorporated | Metal-covered chip scale packages |
US11289453B2 (en) * | 2020-02-27 | 2022-03-29 | Qualcomm Incorporated | Package comprising a substrate and a high-density interconnect structure coupled to the substrate |
US11335646B2 (en) * | 2020-03-10 | 2022-05-17 | Advanced Semiconductor Engineering, Inc. | Substrate structure including embedded semiconductor device and method of manufacturing the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060216868A1 (en) * | 2005-03-25 | 2006-09-28 | Advanced Semiconductor Engineering Inc. | Package structure and fabrication thereof |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
US8193034B2 (en) * | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
US8569892B2 (en) * | 2008-10-10 | 2013-10-29 | Nec Corporation | Semiconductor device and manufacturing method thereof |
US9443797B2 (en) * | 2012-09-14 | 2016-09-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device having wire studs as vertical interconnect in FO-WLP |
Family Cites Families (794)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2230663A (en) | 1940-01-18 | 1941-02-04 | Alden Milton | Electric contact and wire assembly mechanism |
US3017437A (en) | 1956-11-27 | 1962-01-16 | Rhone Poulenc Sa | Production of glycol monoethers |
US3017452A (en) | 1958-12-23 | 1962-01-16 | Bell Telephone Labor Inc | High pressure seals for lead-in conductors |
US3020290A (en) | 1959-10-14 | 1962-02-06 | Jefferson Chem Co Inc | Preparation of unsaturated compounds |
DE1439262B2 (en) | 1963-07-23 | 1972-03-30 | Siemens AG, 1000 Berlin u. 8000 München | METHOD OF CONTACTING SEMICONDUCTOR COMPONENTS BY THERMOCOMPRESSION |
US3358897A (en) | 1964-03-31 | 1967-12-19 | Tempress Res Co | Electric lead wire bonding tools |
US3430835A (en) | 1966-06-07 | 1969-03-04 | Westinghouse Electric Corp | Wire bonding apparatus for microelectronic components |
US3623649A (en) | 1969-06-09 | 1971-11-30 | Gen Motors Corp | Wedge bonding tool for the attachment of semiconductor leads |
DE2119567C2 (en) | 1970-05-05 | 1983-07-14 | International Computers Ltd., London | Electrical connection device and method for making the same |
DE2228703A1 (en) | 1972-06-13 | 1974-01-10 | Licentia Gmbh | PROCESS FOR MANUFACTURING A SPECIFIED SOLDER THICKNESS IN THE MANUFACTURING OF SEMI-CONDUCTOR COMPONENTS |
JPS5150661A (en) | 1974-10-30 | 1976-05-04 | Hitachi Ltd | |
US4072816A (en) | 1976-12-13 | 1978-02-07 | International Business Machines Corporation | Integrated circuit package |
US4067104A (en) | 1977-02-24 | 1978-01-10 | Rockwell International Corporation | Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components |
US4213556A (en) | 1978-10-02 | 1980-07-22 | General Motors Corporation | Method and apparatus to detect automatic wire bonder failure |
US4327860A (en) | 1980-01-03 | 1982-05-04 | Kulicke And Soffa Ind. Inc. | Method of making slack free wire interconnections |
US4422568A (en) | 1981-01-12 | 1983-12-27 | Kulicke And Soffa Industries, Inc. | Method of making constant bonding wire tail lengths |
US4437604A (en) | 1982-03-15 | 1984-03-20 | Kulicke & Soffa Industries, Inc. | Method of making fine wire interconnections |
JPS59189069A (en) | 1983-04-12 | 1984-10-26 | Alps Electric Co Ltd | Device and method for coating solder on terminal |
JPS61125062A (en) | 1984-11-22 | 1986-06-12 | Hitachi Ltd | Method and device for attaching pin |
US4667267A (en) | 1985-01-22 | 1987-05-19 | Rogers Corporation | Decoupling capacitor for pin grid array package |
US4604644A (en) | 1985-01-28 | 1986-08-05 | International Business Machines Corporation | Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making |
US4642889A (en) | 1985-04-29 | 1987-02-17 | Amp Incorporated | Compliant interconnection and method therefor |
JPS61269345A (en) | 1985-05-24 | 1986-11-28 | Hitachi Ltd | Semiconductor device |
US5917707A (en) | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
US5476211A (en) | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
US4924353A (en) | 1985-12-20 | 1990-05-08 | Hughes Aircraft Company | Connector system for coupling to an integrated circuit chip |
US4716049A (en) | 1985-12-20 | 1987-12-29 | Hughes Aircraft Company | Compressive pedestal for microminiature connections |
JPS62158338A (en) | 1985-12-28 | 1987-07-14 | Tanaka Denshi Kogyo Kk | Semiconductor device |
US4793814A (en) | 1986-07-21 | 1988-12-27 | Rogers Corporation | Electrical circuit board interconnect |
US4695870A (en) | 1986-03-27 | 1987-09-22 | Hughes Aircraft Company | Inverted chip carrier |
JPS62226307A (en) | 1986-03-28 | 1987-10-05 | Toshiba Corp | Robot device |
US4771930A (en) | 1986-06-30 | 1988-09-20 | Kulicke And Soffa Industries Inc. | Apparatus for supplying uniform tail lengths |
JPS6397941A (en) | 1986-10-14 | 1988-04-28 | Fuji Photo Film Co Ltd | Photosensitive material |
US4955523A (en) | 1986-12-17 | 1990-09-11 | Raychem Corporation | Interconnection of electronic components |
DE3703694A1 (en) | 1987-02-06 | 1988-08-18 | Dynapert Delvotec Gmbh | BALL BONDING METHOD AND DEVICE FOR CARRYING OUT THE SAME |
KR970003915B1 (en) | 1987-06-24 | 1997-03-22 | 미다 가쓰시게 | Semiconductor device and the use memory module |
JP2642359B2 (en) | 1987-09-11 | 1997-08-20 | 株式会社日立製作所 | Semiconductor device |
US5138438A (en) | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
JPS6412769A (en) | 1987-07-07 | 1989-01-17 | Sony Corp | Correction circuit for image distortion |
US4804132A (en) | 1987-08-28 | 1989-02-14 | Difrancesco Louis | Method for cold bonding |
US4867267A (en) | 1987-10-14 | 1989-09-19 | Industrial Research Products, Inc. | Hearing aid transducer |
JPH01118364A (en) | 1987-10-30 | 1989-05-10 | Fujitsu Ltd | Presolder dipping method |
US4845354A (en) | 1988-03-08 | 1989-07-04 | International Business Machines Corporation | Process control for laser wire bonding |
JPH01313969A (en) | 1988-06-13 | 1989-12-19 | Hitachi Ltd | Semiconductor device |
US4998885A (en) | 1989-10-27 | 1991-03-12 | International Business Machines Corporation | Elastomeric area array interposer |
US5077598A (en) | 1989-11-08 | 1991-12-31 | Hewlett-Packard Company | Strain relief flip-chip integrated circuit assembly with test fixturing |
US5095187A (en) | 1989-12-20 | 1992-03-10 | Raychem Corporation | Weakening wire supplied through a wire bonder |
CA2034700A1 (en) | 1990-01-23 | 1991-07-24 | Masanori Nishiguchi | Substrate for packaging a semiconductor device |
AU645283B2 (en) | 1990-01-23 | 1994-01-13 | Sumitomo Electric Industries, Ltd. | Substrate for packaging a semiconductor device |
US5948533A (en) | 1990-02-09 | 1999-09-07 | Ormet Corporation | Vertically interconnected electronic assemblies and compositions useful therefor |
US5376403A (en) | 1990-02-09 | 1994-12-27 | Capote; Miguel A. | Electrically conductive compositions and methods for the preparation and use thereof |
US5083697A (en) | 1990-02-14 | 1992-01-28 | Difrancesco Louis | Particle-enhanced joining of metal surfaces |
US4975079A (en) | 1990-02-23 | 1990-12-04 | International Business Machines Corp. | Connector assembly for chip testing |
US4999472A (en) | 1990-03-12 | 1991-03-12 | Neinast James E | Electric arc system for ablating a surface coating |
US5241456A (en) | 1990-07-02 | 1993-08-31 | General Electric Company | Compact high density interconnect structure |
US5148266A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5679977A (en) | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5067382A (en) | 1990-11-02 | 1991-11-26 | Cray Computer Corporation | Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire |
KR940001149B1 (en) | 1991-04-16 | 1994-02-14 | 삼성전자 주식회사 | Chip bonding method of semiconductor device |
JPH04346436A (en) | 1991-05-24 | 1992-12-02 | Fujitsu Ltd | Bump manufacturing method and device |
US5316788A (en) | 1991-07-26 | 1994-05-31 | International Business Machines Corporation | Applying solder to high density substrates |
US5203075A (en) | 1991-08-12 | 1993-04-20 | Inernational Business Machines | Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders |
US5133495A (en) | 1991-08-12 | 1992-07-28 | International Business Machines Corporation | Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween |
JPH06510122A (en) | 1991-08-23 | 1994-11-10 | エヌチップ インコーポレイテッド | Burn-in techniques for unpackaged integrated circuits |
US5220489A (en) | 1991-10-11 | 1993-06-15 | Motorola, Inc. | Multicomponent integrated circuit package |
US5238173A (en) | 1991-12-04 | 1993-08-24 | Kaijo Corporation | Wire bonding misattachment detection apparatus and that detection method in a wire bonder |
JP2931936B2 (en) | 1992-01-17 | 1999-08-09 | 株式会社日立製作所 | Method for manufacturing lead frame for semiconductor device, lead frame for semiconductor device, and resin-sealed semiconductor device |
US5241454A (en) | 1992-01-22 | 1993-08-31 | International Business Machines Corporation | Mutlilayered flexible circuit package |
US5831836A (en) | 1992-01-30 | 1998-11-03 | Lsi Logic | Power plane for semiconductor device |
US5222014A (en) | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5438224A (en) | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
US5494667A (en) | 1992-06-04 | 1996-02-27 | Kabushiki Kaisha Hayahibara | Topically applied hair restorer containing pine extract |
US6054756A (en) | 1992-07-24 | 2000-04-25 | Tessera, Inc. | Connection components with frangible leads and bus |
US5977618A (en) | 1992-07-24 | 1999-11-02 | Tessera, Inc. | Semiconductor connection components and methods with releasable lead support |
WO1994003036A1 (en) | 1992-07-24 | 1994-02-03 | Tessera, Inc. | Semiconductor connection components and methods with releasable lead support |
US5371654A (en) | 1992-10-19 | 1994-12-06 | International Business Machines Corporation | Three dimensional high performance interconnection package |
US6295729B1 (en) | 1992-10-19 | 2001-10-02 | International Business Machines Corporation | Angled flying lead wire bonding process |
US20050062492A1 (en) | 2001-08-03 | 2005-03-24 | Beaman Brian Samuel | High density integrated circuit apparatus, test probe and methods of use thereof |
JP2716336B2 (en) | 1993-03-10 | 1998-02-18 | 日本電気株式会社 | Integrated circuit device |
JPH06268101A (en) | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate |
US5340771A (en) | 1993-03-18 | 1994-08-23 | Lsi Logic Corporation | Techniques for providing high I/O count connections to semiconductor dies |
US20030048108A1 (en) | 1993-04-30 | 2003-03-13 | Beaman Brian Samuel | Structural design and processes to control probe position accuracy in a wafer test probe assembly |
US7368924B2 (en) | 1993-04-30 | 2008-05-06 | International Business Machines Corporation | Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof |
US5811982A (en) | 1995-11-27 | 1998-09-22 | International Business Machines Corporation | High density cantilevered probe for electronic devices |
JPH06333931A (en) | 1993-05-20 | 1994-12-02 | Nippondenso Co Ltd | Manufacture of fine electrode of semiconductor device |
JP2981385B2 (en) | 1993-09-06 | 1999-11-22 | シャープ株式会社 | Structure of chip component type LED and method of manufacturing the same |
US5346118A (en) | 1993-09-28 | 1994-09-13 | At&T Bell Laboratories | Surface mount solder assembly of leadless integrated circuit packages to substrates |
US6741085B1 (en) | 1993-11-16 | 2004-05-25 | Formfactor, Inc. | Contact carriers (tiles) for populating larger substrates with spring contacts |
US6835898B2 (en) | 1993-11-16 | 2004-12-28 | Formfactor, Inc. | Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures |
US5455390A (en) | 1994-02-01 | 1995-10-03 | Tessera, Inc. | Microelectronics unit mounting with multiple lead bonding |
WO1995026047A1 (en) | 1994-03-18 | 1995-09-28 | Hitachi Chemical Company, Ltd. | Semiconductor package manufacturing method and semiconductor package |
US5578869A (en) | 1994-03-29 | 1996-11-26 | Olin Corporation | Components for housing an integrated circuit device |
US5802699A (en) | 1994-06-07 | 1998-09-08 | Tessera, Inc. | Methods of assembling microelectronic assembly with socket for engaging bump leads |
US5615824A (en) | 1994-06-07 | 1997-04-01 | Tessera, Inc. | Soldering with resilient contacts |
JPH07335783A (en) | 1994-06-13 | 1995-12-22 | Fujitsu Ltd | Semiconductor device and semiconductor device unit |
US5468995A (en) | 1994-07-05 | 1995-11-21 | Motorola, Inc. | Semiconductor device having compliant columnar electrical connections |
US5518964A (en) | 1994-07-07 | 1996-05-21 | Tessera, Inc. | Microelectronic mounting with multiple lead deformation and bonding |
US6177636B1 (en) | 1994-12-29 | 2001-01-23 | Tessera, Inc. | Connection components with posts |
US5989936A (en) | 1994-07-07 | 1999-11-23 | Tessera, Inc. | Microelectronic assembly fabrication with terminal formation from a conductive layer |
US5688716A (en) | 1994-07-07 | 1997-11-18 | Tessera, Inc. | Fan-out semiconductor chip assembly |
US6828668B2 (en) | 1994-07-07 | 2004-12-07 | Tessera, Inc. | Flexible lead structures and methods of making same |
US6117694A (en) | 1994-07-07 | 2000-09-12 | Tessera, Inc. | Flexible lead structures and methods of making same |
US5656550A (en) | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
US5659952A (en) | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
US5541567A (en) | 1994-10-17 | 1996-07-30 | International Business Machines Corporation | Coaxial vias in an electronic substrate |
US5495667A (en) | 1994-11-07 | 1996-03-05 | Micron Technology, Inc. | Method for forming contact pins for semiconductor dice and interconnects |
JP2002509639A (en) | 1994-11-15 | 2002-03-26 | フォームファクター,インコーポレイテッド | Interconnection elements for microelectronic devices |
US6826827B1 (en) | 1994-12-29 | 2004-12-07 | Tessera, Inc. | Forming conductive posts by selective removal of conductive material |
US5736074A (en) | 1995-06-30 | 1998-04-07 | Micro Fab Technologies, Inc. | Manufacture of coated spheres |
US5971253A (en) | 1995-07-31 | 1999-10-26 | Tessera, Inc. | Microelectronic component mounting with deformable shell terminals |
US5872051A (en) | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
US5874781A (en) | 1995-08-16 | 1999-02-23 | Micron Technology, Inc. | Angularly offset stacked die multichip device and method of manufacture |
US5886412A (en) | 1995-08-16 | 1999-03-23 | Micron Technology, Inc. | Angularly offset and recessed stacked die multichip device |
US5810609A (en) | 1995-08-28 | 1998-09-22 | Tessera, Inc. | Socket for engaging bump leads on a microelectronic device and methods therefor |
US5766987A (en) | 1995-09-22 | 1998-06-16 | Tessera, Inc. | Microelectronic encapsulation methods and equipment |
US6211572B1 (en) | 1995-10-31 | 2001-04-03 | Tessera, Inc. | Semiconductor chip package with fan-in leads |
JP3332308B2 (en) | 1995-11-07 | 2002-10-07 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
JPH09134934A (en) | 1995-11-07 | 1997-05-20 | Sumitomo Metal Ind Ltd | Semiconductor package and semiconductor device |
US5718361A (en) | 1995-11-21 | 1998-02-17 | International Business Machines Corporation | Apparatus and method for forming mold for metallic material |
US5731709A (en) | 1996-01-26 | 1998-03-24 | Motorola, Inc. | Method for testing a ball grid array semiconductor device and a device for such testing |
US7166495B2 (en) | 1996-02-20 | 2007-01-23 | Micron Technology, Inc. | Method of fabricating a multi-die semiconductor package assembly |
US5994152A (en) | 1996-02-21 | 1999-11-30 | Formfactor, Inc. | Fabricating interconnects and tips using sacrificial substrates |
JP3146345B2 (en) | 1996-03-11 | 2001-03-12 | アムコー テクノロジー コリア インコーポレーティド | Bump forming method for bump chip scale semiconductor package |
US6000126A (en) | 1996-03-29 | 1999-12-14 | General Dynamics Information Systems, Inc. | Method and apparatus for connecting area grid arrays to printed wire board |
US6821821B2 (en) | 1996-04-18 | 2004-11-23 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
DE19618227A1 (en) | 1996-05-07 | 1997-11-13 | Herbert Streckfus Gmbh | Method and device for soldering electronic components on a printed circuit board |
KR100186333B1 (en) | 1996-06-20 | 1999-03-20 | 문정환 | Chip-sized semiconductor package and its manufacturing method |
EP2270845A3 (en) | 1996-10-29 | 2013-04-03 | Invensas Corporation | Integrated circuits and methods for their fabrication |
JPH10135220A (en) | 1996-10-29 | 1998-05-22 | Taiyo Yuden Co Ltd | Bump-forming method |
JPH10135221A (en) | 1996-10-29 | 1998-05-22 | Taiyo Yuden Co Ltd | Bump-forming method |
US6492719B2 (en) | 1999-07-30 | 2002-12-10 | Hitachi, Ltd. | Semiconductor device |
US5976913A (en) | 1996-12-12 | 1999-11-02 | Tessera, Inc. | Microelectronic mounting with multiple lead deformation using restraining straps |
US6121676A (en) | 1996-12-13 | 2000-09-19 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
US6054337A (en) | 1996-12-13 | 2000-04-25 | Tessera, Inc. | Method of making a compliant multichip package |
US6225688B1 (en) | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
US6133072A (en) | 1996-12-13 | 2000-10-17 | Tessera, Inc. | Microelectronic connector with planar elastomer sockets |
US5736785A (en) | 1996-12-20 | 1998-04-07 | Industrial Technology Research Institute | Semiconductor package for improving the capability of spreading heat |
JP3400279B2 (en) | 1997-01-13 | 2003-04-28 | 株式会社新川 | Bump forming method |
US5898991A (en) | 1997-01-16 | 1999-05-04 | International Business Machines Corporation | Methods of fabrication of coaxial vias and magnetic devices |
US5839191A (en) | 1997-01-24 | 1998-11-24 | Unisys Corporation | Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package |
KR100543836B1 (en) | 1997-08-19 | 2006-01-23 | 가부시키가이샤 히타치세이사쿠쇼 | Multichip module structure and method for manufacturing the same |
CA2213590C (en) | 1997-08-21 | 2006-11-07 | Keith C. Carroll | Flexible circuit connector and method of making same |
JP3859318B2 (en) | 1997-08-29 | 2006-12-20 | シチズン電子株式会社 | Electronic circuit packaging method |
US6525414B2 (en) | 1997-09-16 | 2003-02-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device including a wiring board and semiconductor elements mounted thereon |
JP3937265B2 (en) | 1997-09-29 | 2007-06-27 | エルピーダメモリ株式会社 | Semiconductor device |
JP3262531B2 (en) | 1997-10-02 | 2002-03-04 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Bent flying lead wire bonding process |
JP2978861B2 (en) | 1997-10-28 | 1999-11-15 | 九州日本電気株式会社 | Molded BGA type semiconductor device and manufacturing method thereof |
US6038136A (en) | 1997-10-29 | 2000-03-14 | Hestia Technologies, Inc. | Chip package with molded underfill |
JP3393800B2 (en) | 1997-11-05 | 2003-04-07 | 新光電気工業株式会社 | Manufacturing method of semiconductor device |
JPH11219984A (en) | 1997-11-06 | 1999-08-10 | Sharp Corp | Semiconductor device package, its manufacture and circuit board therefor |
US6222136B1 (en) | 1997-11-12 | 2001-04-24 | International Business Machines Corporation | Printed circuit board with continuous connective bumps |
US6038133A (en) | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
US6002168A (en) | 1997-11-25 | 1999-12-14 | Tessera, Inc. | Microelectronic component with rigid interposer |
JPH11163022A (en) | 1997-11-28 | 1999-06-18 | Sony Corp | Semiconductor and manufacture of the same and electronic equipment |
US6124546A (en) | 1997-12-03 | 2000-09-26 | Advanced Micro Devices, Inc. | Integrated circuit chip package and method of making the same |
US6260264B1 (en) | 1997-12-08 | 2001-07-17 | 3M Innovative Properties Company | Methods for making z-axis electrical connections |
US6052287A (en) | 1997-12-09 | 2000-04-18 | Sandia Corporation | Silicon ball grid array chip carrier |
US5973391A (en) | 1997-12-11 | 1999-10-26 | Read-Rite Corporation | Interposer with embedded circuitry and method for using the same to package microelectronic units |
JPH11220082A (en) | 1998-02-03 | 1999-08-10 | Oki Electric Ind Co Ltd | Semiconductor device |
JP3536650B2 (en) | 1998-02-27 | 2004-06-14 | 富士ゼロックス株式会社 | Bump forming method and apparatus |
JPH11260856A (en) | 1998-03-11 | 1999-09-24 | Matsushita Electron Corp | Semiconductor device and its manufacture and mounting structure of the device |
US5933713A (en) | 1998-04-06 | 1999-08-03 | Micron Technology, Inc. | Method of forming overmolded chip scale package and resulting product |
US6222276B1 (en) | 1998-04-07 | 2001-04-24 | International Business Machines Corporation | Through-chip conductors for low inductance chip-to-chip integration and off-chip connections |
KR100260997B1 (en) | 1998-04-08 | 2000-07-01 | 마이클 디. 오브라이언 | Semiconductor package |
US6329224B1 (en) | 1998-04-28 | 2001-12-11 | Tessera, Inc. | Encapsulation of microelectronic assemblies |
US6180881B1 (en) | 1998-05-05 | 2001-01-30 | Harlan Ruben Isaak | Chip stack and method of making same |
JPH11330134A (en) | 1998-05-12 | 1999-11-30 | Hitachi Ltd | Wire-bonding method and device, and semiconductor device |
KR100266693B1 (en) | 1998-05-30 | 2000-09-15 | 김영환 | Stackable ball grid array semiconductor package and fabrication method thereof |
US5977640A (en) | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
KR100265563B1 (en) | 1998-06-29 | 2000-09-15 | 김영환 | Ball grid array package and fabricating method thereof |
US6414391B1 (en) | 1998-06-30 | 2002-07-02 | Micron Technology, Inc. | Module assembly for stacked BGA packages with a common bus bar in the assembly |
US6164523A (en) | 1998-07-01 | 2000-12-26 | Semiconductor Components Industries, Llc | Electronic component and method of manufacture |
US5854507A (en) | 1998-07-21 | 1998-12-29 | Hewlett-Packard Company | Multiple chip assembly |
US6399426B1 (en) | 1998-07-21 | 2002-06-04 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US6515355B1 (en) | 1998-09-02 | 2003-02-04 | Micron Technology, Inc. | Passivation layer for packaged integrated circuits |
JP2000091383A (en) | 1998-09-07 | 2000-03-31 | Ngk Spark Plug Co Ltd | Wiring board |
US6194250B1 (en) | 1998-09-14 | 2001-02-27 | Motorola, Inc. | Low-profile microelectronic package |
US6158647A (en) | 1998-09-29 | 2000-12-12 | Micron Technology, Inc. | Concave face wire bond capillary |
US6684007B2 (en) | 1998-10-09 | 2004-01-27 | Fujitsu Limited | Optical coupling structures and the fabrication processes |
US6268662B1 (en) | 1998-10-14 | 2001-07-31 | Texas Instruments Incorporated | Wire bonded flip-chip assembly of semiconductor devices |
JP3407275B2 (en) | 1998-10-28 | 2003-05-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Bump and method of forming the same |
US6332270B2 (en) | 1998-11-23 | 2001-12-25 | International Business Machines Corporation | Method of making high density integral test probe |
US6255126B1 (en) | 1998-12-02 | 2001-07-03 | Formfactor, Inc. | Lithographic contact elements |
KR100502222B1 (en) | 1999-01-29 | 2005-07-18 | 마츠시타 덴끼 산교 가부시키가이샤 | Electronic parts mounting method and device therefor |
US6206273B1 (en) | 1999-02-17 | 2001-03-27 | International Business Machines Corporation | Structures and processes to create a desired probetip contact geometry on a wafer test probe |
KR100319609B1 (en) | 1999-03-09 | 2002-01-05 | 김영환 | A wire arrayed chip size package and the fabrication method thereof |
US6177729B1 (en) | 1999-04-03 | 2001-01-23 | International Business Machines Corporation | Rolling ball connector |
US6211574B1 (en) | 1999-04-16 | 2001-04-03 | Advanced Semiconductor Engineering Inc. | Semiconductor package with wire protection and method therefor |
JP2000323516A (en) | 1999-05-14 | 2000-11-24 | Fujitsu Ltd | Manufacture of wiring substrate, wiring substrate, and semiconductor device |
US6258625B1 (en) | 1999-05-18 | 2001-07-10 | International Business Machines Corporation | Method of interconnecting electronic components using a plurality of conductive studs |
US6376769B1 (en) | 1999-05-18 | 2002-04-23 | Amerasia International Technology, Inc. | High-density electronic package, and method for making same |
JP3398721B2 (en) | 1999-05-20 | 2003-04-21 | アムコー テクノロジー コリア インコーポレーティド | Semiconductor package and manufacturing method thereof |
US6238949B1 (en) | 1999-06-18 | 2001-05-29 | National Semiconductor Corporation | Method and apparatus for forming a plastic chip on chip package module |
JP4367730B2 (en) | 1999-06-25 | 2009-11-18 | 株式会社エンプラス | IC socket and spring means of the IC socket |
US6228687B1 (en) | 1999-06-28 | 2001-05-08 | Micron Technology, Inc. | Wafer-level package and methods of fabricating |
TW417839U (en) | 1999-07-30 | 2001-01-01 | Shen Ming Tung | Stacked memory module structure and multi-layered stacked memory module structure using the same |
JP5333337B2 (en) | 1999-08-12 | 2013-11-06 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
US6168965B1 (en) | 1999-08-12 | 2001-01-02 | Tower Semiconductor Ltd. | Method for making backside illuminated image sensor |
JP4526651B2 (en) | 1999-08-12 | 2010-08-18 | 富士通セミコンダクター株式会社 | Semiconductor device |
US6319764B1 (en) | 1999-08-25 | 2001-11-20 | Micron Technology, Inc. | Method of forming haze-free BST films |
KR101084526B1 (en) | 1999-09-02 | 2011-11-18 | 이비덴 가부시키가이샤 | Printed circuit board and method of manufacturing printed circuit board |
US6867499B1 (en) | 1999-09-30 | 2005-03-15 | Skyworks Solutions, Inc. | Semiconductor packaging |
JP3513444B2 (en) | 1999-10-20 | 2004-03-31 | 株式会社新川 | Method for forming pin-shaped wires |
JP2001127246A (en) | 1999-10-29 | 2001-05-11 | Fujitsu Ltd | Semiconductor device |
US6362525B1 (en) | 1999-11-09 | 2002-03-26 | Cypress Semiconductor Corp. | Circuit structure including a passive element formed within a grid array substrate and method for making the same |
JP3619410B2 (en) | 1999-11-18 | 2005-02-09 | 株式会社ルネサステクノロジ | Bump forming method and system |
JP3798597B2 (en) | 1999-11-30 | 2006-07-19 | 富士通株式会社 | Semiconductor device |
JP3566156B2 (en) | 1999-12-02 | 2004-09-15 | 株式会社新川 | Method for forming pin-shaped wires |
KR100426494B1 (en) | 1999-12-20 | 2004-04-13 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
US6790757B1 (en) | 1999-12-20 | 2004-09-14 | Agere Systems Inc. | Wire bonding method for copper interconnects in semiconductor devices |
KR20010061849A (en) | 1999-12-29 | 2001-07-07 | 박종섭 | Wafer level package |
JP2001196407A (en) | 2000-01-14 | 2001-07-19 | Seiko Instruments Inc | Semiconductor device and method of forming the same |
US6710454B1 (en) | 2000-02-16 | 2004-03-23 | Micron Technology, Inc. | Adhesive layer for an electronic apparatus having multiple semiconductor devices |
JP2001319992A (en) | 2000-02-28 | 2001-11-16 | Shinko Electric Ind Co Ltd | Wiring board, semiconductor device, and their manufacturing methods |
JP2001339011A (en) | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
JP3980807B2 (en) | 2000-03-27 | 2007-09-26 | 株式会社東芝 | Semiconductor device and semiconductor module |
JP2001274196A (en) | 2000-03-28 | 2001-10-05 | Rohm Co Ltd | Semiconductor device |
US6581276B2 (en) | 2000-04-04 | 2003-06-24 | Amerasia International Technology, Inc. | Fine-pitch flexible connector, and method for making same |
KR100583491B1 (en) | 2000-04-07 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
US6578754B1 (en) | 2000-04-27 | 2003-06-17 | Advanpack Solutions Pte. Ltd. | Pillar connections for semiconductor chips and method of manufacture |
US6531335B1 (en) | 2000-04-28 | 2003-03-11 | Micron Technology, Inc. | Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods |
JP2001326236A (en) | 2000-05-12 | 2001-11-22 | Nec Kyushu Ltd | Manufacturing method of semiconductor device |
JP2001326304A (en) | 2000-05-15 | 2001-11-22 | Toshiba Corp | Semiconductor device and its manufacturing method |
US6522018B1 (en) | 2000-05-16 | 2003-02-18 | Micron Technology, Inc. | Ball grid array chip packages having improved testing and stacking characteristics |
US6647310B1 (en) | 2000-05-30 | 2003-11-11 | Advanced Micro Devices, Inc. | Temperature control of an integrated circuit |
US6531784B1 (en) | 2000-06-02 | 2003-03-11 | Amkor Technology, Inc. | Semiconductor package with spacer strips |
US6717245B1 (en) | 2000-06-02 | 2004-04-06 | Micron Technology, Inc. | Chip scale packages performed by wafer level processing |
US6395199B1 (en) | 2000-06-07 | 2002-05-28 | Graftech Inc. | Process for providing increased conductivity to a material |
US6560117B2 (en) | 2000-06-28 | 2003-05-06 | Micron Technology, Inc. | Packaged microelectronic die assemblies and methods of manufacture |
US6525413B1 (en) | 2000-07-12 | 2003-02-25 | Micron Technology, Inc. | Die to die connection method and assemblies and packages including dice so connected |
US6476583B2 (en) | 2000-07-21 | 2002-11-05 | Jomahip, Llc | Automatic battery charging system for a battery back-up DC power supply |
JP2002050871A (en) | 2000-08-02 | 2002-02-15 | Casio Comput Co Ltd | Build-up circuit board and manufacturing method thereof |
SE517086C2 (en) | 2000-08-08 | 2002-04-09 | Ericsson Telefon Ab L M | Method for securing solder beads and any components attached to one and the same side of a substrate |
US20020020898A1 (en) | 2000-08-16 | 2002-02-21 | Vu Quat T. | Microelectronic substrates with integrated devices |
US6462575B1 (en) | 2000-08-28 | 2002-10-08 | Micron Technology, Inc. | Method and system for wafer level testing and burning-in semiconductor components |
JP2002076250A (en) | 2000-08-29 | 2002-03-15 | Nec Corp | Semiconductor device |
US6614103B1 (en) | 2000-09-01 | 2003-09-02 | General Electric Company | Plastic packaging of LED arrays |
JP3874062B2 (en) | 2000-09-05 | 2007-01-31 | セイコーエプソン株式会社 | Semiconductor device |
US6507104B2 (en) | 2000-09-07 | 2003-01-14 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with embedded heat-dissipating device |
US7009297B1 (en) | 2000-10-13 | 2006-03-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal particle |
US6423570B1 (en) | 2000-10-18 | 2002-07-23 | Intel Corporation | Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby |
JP4505983B2 (en) | 2000-12-01 | 2010-07-21 | 日本電気株式会社 | Semiconductor device |
JP3798620B2 (en) | 2000-12-04 | 2006-07-19 | 富士通株式会社 | Manufacturing method of semiconductor device |
US6734539B2 (en) | 2000-12-27 | 2004-05-11 | Lucent Technologies Inc. | Stacked module package |
TW511405B (en) | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
KR100393102B1 (en) | 2000-12-29 | 2003-07-31 | 앰코 테크놀로지 코리아 주식회사 | Stacked semiconductor package |
AUPR244801A0 (en) | 2001-01-10 | 2001-02-01 | Silverbrook Research Pty Ltd | A method and apparatus (WSM01) |
US6388322B1 (en) | 2001-01-17 | 2002-05-14 | Aralight, Inc. | Article comprising a mechanically compliant bump |
US6653170B1 (en) | 2001-02-06 | 2003-11-25 | Charles W. C. Lin | Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit |
US6472743B2 (en) | 2001-02-22 | 2002-10-29 | Siliconware Precision Industries, Co., Ltd. | Semiconductor package with heat dissipating structure |
KR100401020B1 (en) | 2001-03-09 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | Stacking structure of semiconductor chip and semiconductor package using it |
JP2002280414A (en) | 2001-03-22 | 2002-09-27 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
JP2002289769A (en) | 2001-03-26 | 2002-10-04 | Matsushita Electric Ind Co Ltd | Stacked semiconductor device and its manufacturing method |
SG108245A1 (en) | 2001-03-30 | 2005-01-28 | Micron Technology Inc | Ball grid array interposer, packages and methods |
US6874910B2 (en) | 2001-04-12 | 2005-04-05 | Matsushita Electric Works, Ltd. | Light source device using LED, and method of producing same |
US7115986B2 (en) | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
US6825552B2 (en) | 2001-05-09 | 2004-11-30 | Tessera, Inc. | Connection components with anisotropic conductive material interconnection |
US20040201774A1 (en) | 2001-05-15 | 2004-10-14 | Gennetten K. Douglas | Docked camera becomes electronic picture frame |
TW544826B (en) | 2001-05-18 | 2003-08-01 | Nec Electronics Corp | Flip-chip-type semiconductor device and manufacturing method thereof |
US6930256B1 (en) | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laser-embedded conductive patterns and method therefor |
US6900528B2 (en) | 2001-06-21 | 2005-05-31 | Micron Technology, Inc. | Stacked mass storage flash memory package |
US6754407B2 (en) | 2001-06-26 | 2004-06-22 | Intel Corporation | Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board |
US20030006494A1 (en) | 2001-07-03 | 2003-01-09 | Lee Sang Ho | Thin profile stackable semiconductor package and method for manufacturing |
US6486545B1 (en) | 2001-07-26 | 2002-11-26 | Amkor Technology, Inc. | Pre-drilled ball grid array package |
US6451626B1 (en) | 2001-07-27 | 2002-09-17 | Charles W.C. Lin | Three-dimensional stacked semiconductor package |
US6765287B1 (en) | 2001-07-27 | 2004-07-20 | Charles W. C. Lin | Three-dimensional stacked semiconductor package |
JP4023159B2 (en) | 2001-07-31 | 2007-12-19 | ソニー株式会社 | Manufacturing method of semiconductor device and manufacturing method of laminated semiconductor device |
JP2003042639A (en) | 2001-07-31 | 2003-02-13 | Matsushita Refrig Co Ltd | Refrigerator |
US6550666B2 (en) | 2001-08-21 | 2003-04-22 | Advanpack Solutions Pte Ltd | Method for forming a flip chip on leadframe semiconductor package |
US7605479B2 (en) | 2001-08-22 | 2009-10-20 | Tessera, Inc. | Stacked chip assembly with encapsulant layer |
US7176506B2 (en) | 2001-08-28 | 2007-02-13 | Tessera, Inc. | High frequency chip packages with connecting elements |
SG117395A1 (en) | 2001-08-29 | 2005-12-29 | Micron Technology Inc | Wire bonded microelectronic device assemblies and methods of manufacturing same |
US6864166B1 (en) | 2001-08-29 | 2005-03-08 | Micron Technology, Inc. | Method of manufacturing wire bonded microelectronic device assemblies |
US6787926B2 (en) | 2001-09-05 | 2004-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd | Wire stitch bond on an integrated circuit bond pad and method of making the same |
US20030057544A1 (en) | 2001-09-13 | 2003-03-27 | Nathan Richard J. | Integrated assembly protocol |
US6476506B1 (en) | 2001-09-28 | 2002-11-05 | Motorola, Inc. | Packaged semiconductor with multiple rows of bond pads and method therefor |
DE10297316T5 (en) | 2001-10-09 | 2004-12-09 | Tessera, Inc., San Jose | Stacked assemblies |
US6977440B2 (en) | 2001-10-09 | 2005-12-20 | Tessera, Inc. | Stacked packages |
JP2003122611A (en) | 2001-10-11 | 2003-04-25 | Oki Electric Ind Co Ltd | Data providing method and server device |
JP4257771B2 (en) | 2001-10-16 | 2009-04-22 | シンジーテック株式会社 | Conductive blade |
US20030094666A1 (en) | 2001-11-16 | 2003-05-22 | R-Tec Corporation | Interposer |
JP3875077B2 (en) | 2001-11-16 | 2007-01-31 | 富士通株式会社 | Electronic device and device connection method |
JP2003174124A (en) | 2001-12-04 | 2003-06-20 | Sainekkusu:Kk | Method of forming external electrode of semiconductor device |
KR100435813B1 (en) | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | Multi chip package using metal bar and manufacturing method thereof |
JP2003197668A (en) | 2001-12-10 | 2003-07-11 | Senmao Koochii Kofun Yugenkoshi | Bonding wire for semiconductor package, and its manufacturing method |
JP3507059B2 (en) | 2002-06-27 | 2004-03-15 | 沖電気工業株式会社 | Stacked multi-chip package |
JP2003197669A (en) | 2001-12-28 | 2003-07-11 | Seiko Epson Corp | Bonding method and bonding apparatus |
TW584950B (en) | 2001-12-31 | 2004-04-21 | Megic Corp | Chip packaging structure and process thereof |
TW548816B (en) | 2002-01-23 | 2003-08-21 | Via Tech Inc | Formation method of conductor pillar |
JP3935370B2 (en) | 2002-02-19 | 2007-06-20 | セイコーエプソン株式会社 | Bumped semiconductor element manufacturing method, semiconductor device and manufacturing method thereof, circuit board, and electronic device |
SG115456A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
DE10209922A1 (en) | 2002-03-07 | 2003-10-02 | Infineon Technologies Ag | Electronic module, use of electronic modules to be separated and processes for their production |
US6653723B2 (en) | 2002-03-09 | 2003-11-25 | Fujitsu Limited | System for providing an open-cavity low profile encapsulated semiconductor package |
KR100452819B1 (en) | 2002-03-18 | 2004-10-15 | 삼성전기주식회사 | Chip scale package and method of fabricating the same |
US6979230B2 (en) | 2002-03-20 | 2005-12-27 | Gabe Cherian | Light socket |
JP2003318327A (en) | 2002-04-22 | 2003-11-07 | Mitsui Chemicals Inc | Printed wiring board and stacked package |
US7323767B2 (en) | 2002-04-25 | 2008-01-29 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US7633765B1 (en) | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US7078822B2 (en) | 2002-06-25 | 2006-07-18 | Intel Corporation | Microelectronic device interconnects |
US6906415B2 (en) | 2002-06-27 | 2005-06-14 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor devices and methods |
JP4601892B2 (en) | 2002-07-04 | 2010-12-22 | ラムバス・インコーポレーテッド | Semiconductor device and bump manufacturing method of semiconductor chip |
JP2004047702A (en) | 2002-07-11 | 2004-02-12 | Toshiba Corp | Semiconductor device laminated module |
US6756252B2 (en) | 2002-07-17 | 2004-06-29 | Texas Instrument Incorporated | Multilayer laser trim interconnect method |
US6987032B1 (en) | 2002-07-19 | 2006-01-17 | Asat Ltd. | Ball grid array package and process for manufacturing same |
WO2004017399A1 (en) | 2002-08-16 | 2004-02-26 | Tessera, Inc. | Microelectronic packages with self-aligning features |
TW549592U (en) | 2002-08-16 | 2003-08-21 | Via Tech Inc | Integrated circuit package with a balanced-part structure |
US6964881B2 (en) | 2002-08-27 | 2005-11-15 | Micron Technology, Inc. | Multi-chip wafer level system packages and methods of forming same |
JP3765778B2 (en) | 2002-08-29 | 2006-04-12 | ローム株式会社 | Capillary for wire bonding and wire bonding method using the same |
JP2004095799A (en) | 2002-08-30 | 2004-03-25 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
US20040041757A1 (en) | 2002-09-04 | 2004-03-04 | Ming-Hsiang Yang | Light emitting diode display module with high heat-dispersion and the substrate thereof |
US7294928B2 (en) | 2002-09-06 | 2007-11-13 | Tessera, Inc. | Components, methods and assemblies for stacked packages |
US7246431B2 (en) | 2002-09-06 | 2007-07-24 | Tessera, Inc. | Methods of making microelectronic packages including folded substrates |
US7071547B2 (en) | 2002-09-11 | 2006-07-04 | Tessera, Inc. | Assemblies having stacked semiconductor chips and methods of making same |
US7229906B2 (en) | 2002-09-19 | 2007-06-12 | Kulicke And Soffa Industries, Inc. | Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine |
WO2004032186A2 (en) | 2002-09-30 | 2004-04-15 | Advanced Interconnect Technologies Limited | Thermal enhanced package for block mold assembly |
US7045884B2 (en) | 2002-10-04 | 2006-05-16 | International Rectifier Corporation | Semiconductor device package |
US7057269B2 (en) | 2002-10-08 | 2006-06-06 | Chippac, Inc. | Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package |
US6989122B1 (en) | 2002-10-17 | 2006-01-24 | National Semiconductor Corporation | Techniques for manufacturing flash-free contacts on a semiconductor package |
TW567601B (en) | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
TWI221664B (en) | 2002-11-07 | 2004-10-01 | Via Tech Inc | Structure of chip package and process thereof |
JP2004172157A (en) | 2002-11-15 | 2004-06-17 | Shinko Electric Ind Co Ltd | Semiconductor package and package stack semiconductor device |
US20050176233A1 (en) | 2002-11-15 | 2005-08-11 | Rajeev Joshi | Wafer-level chip scale package and method for fabricating and using the same |
JP2004172477A (en) | 2002-11-21 | 2004-06-17 | Kaijo Corp | Wire loop form, semiconductor device having the same, wire bonding method, and semiconductor manufacturing apparatus |
JP4464041B2 (en) | 2002-12-13 | 2010-05-19 | キヤノン株式会社 | Columnar structure, electrode having columnar structure, and manufacturing method thereof |
JP2004200316A (en) | 2002-12-17 | 2004-07-15 | Shinko Electric Ind Co Ltd | Semiconductor device |
US20050161814A1 (en) | 2002-12-27 | 2005-07-28 | Fujitsu Limited | Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus |
KR100621991B1 (en) | 2003-01-03 | 2006-09-13 | 삼성전자주식회사 | Chip scale stack package |
JP2004221257A (en) | 2003-01-14 | 2004-08-05 | Seiko Epson Corp | Wire bonding method and device thereof |
JP2006518944A (en) | 2003-02-25 | 2006-08-17 | テッセラ,インコーポレイテッド | Ball grid array with bumps |
TW583757B (en) | 2003-02-26 | 2004-04-11 | Advanced Semiconductor Eng | A structure of a flip-chip package and a process thereof |
US20040217471A1 (en) | 2003-02-27 | 2004-11-04 | Tessera, Inc. | Component and assemblies with ends offset downwardly |
JP3885747B2 (en) | 2003-03-13 | 2007-02-28 | 株式会社デンソー | Wire bonding method |
JP2004343030A (en) | 2003-03-31 | 2004-12-02 | North:Kk | Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board |
JP2004319892A (en) | 2003-04-18 | 2004-11-11 | Renesas Technology Corp | Manufacturing method of semiconductor device |
JP2004327855A (en) | 2003-04-25 | 2004-11-18 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
JP4199588B2 (en) | 2003-04-25 | 2008-12-17 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | Wiring circuit board manufacturing method and semiconductor integrated circuit device manufacturing method using the wiring circuit board |
DE10320646A1 (en) | 2003-05-07 | 2004-09-16 | Infineon Technologies Ag | Electronic component, typically integrated circuit, system support and manufacturing method, with support containing component positions in lines and columns, starting with coating auxiliary support with photosensitive layer |
JP4145730B2 (en) | 2003-06-17 | 2008-09-03 | 松下電器産業株式会社 | Module with built-in semiconductor |
KR100604821B1 (en) | 2003-06-30 | 2006-07-26 | 삼성전자주식회사 | Stack type Ball grid array package and method for manufacturing the same |
US20040262728A1 (en) | 2003-06-30 | 2004-12-30 | Sterrett Terry L. | Modular device assemblies |
JP2005033141A (en) | 2003-07-11 | 2005-02-03 | Sony Corp | Semiconductor device, its manufacturing method, false wafer, its manufacturing method, and packaging structure of semiconductor device |
US7227095B2 (en) | 2003-08-06 | 2007-06-05 | Micron Technology, Inc. | Wire bonders and methods of wire-bonding |
KR100537892B1 (en) | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | Chip stack package and manufacturing method thereof |
KR100546374B1 (en) | 2003-08-28 | 2006-01-26 | 삼성전자주식회사 | Multi chip package having center pads and method for manufacturing the same |
US7372151B1 (en) | 2003-09-12 | 2008-05-13 | Asat Ltd. | Ball grid array package and process for manufacturing same |
JP2005093551A (en) | 2003-09-12 | 2005-04-07 | Genusion:Kk | Package structure of semiconductor device, and packaging method |
JP3999720B2 (en) | 2003-09-16 | 2007-10-31 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
US7061096B2 (en) | 2003-09-24 | 2006-06-13 | Silicon Pipe, Inc. | Multi-surface IC packaging structures and methods for their manufacture |
US7224056B2 (en) | 2003-09-26 | 2007-05-29 | Tessera, Inc. | Back-face and edge interconnects for lidded package |
US7462936B2 (en) | 2003-10-06 | 2008-12-09 | Tessera, Inc. | Formation of circuitry with modification of feature height |
US7495179B2 (en) | 2003-10-06 | 2009-02-24 | Tessera, Inc. | Components with posts and pads |
JP4272968B2 (en) | 2003-10-16 | 2009-06-03 | エルピーダメモリ株式会社 | Semiconductor device and semiconductor chip control method |
JP4167965B2 (en) | 2003-11-07 | 2008-10-22 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | Method for manufacturing wiring circuit member |
KR100564585B1 (en) | 2003-11-13 | 2006-03-28 | 삼성전자주식회사 | Double stacked BGA package and multi-stacked BGA package |
TWI227555B (en) | 2003-11-17 | 2005-02-01 | Advanced Semiconductor Eng | Structure of chip package and the process thereof |
KR100621992B1 (en) | 2003-11-19 | 2006-09-13 | 삼성전자주식회사 | structure and method of wafer level stack for devices of different kind and system-in-package using the same |
JP2005183923A (en) | 2003-11-28 | 2005-07-07 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
US7345361B2 (en) | 2003-12-04 | 2008-03-18 | Intel Corporation | Stackable integrated circuit packaging |
JP2005175019A (en) | 2003-12-08 | 2005-06-30 | Sharp Corp | Semiconductor device and multilayer semiconductor device |
JP5197961B2 (en) | 2003-12-17 | 2013-05-15 | スタッツ・チップパック・インコーポレイテッド | Multi-chip package module and manufacturing method thereof |
DE10360708B4 (en) | 2003-12-19 | 2008-04-10 | Infineon Technologies Ag | Semiconductor module with a semiconductor stack, rewiring plate, and method of making the same |
JP4334996B2 (en) | 2003-12-24 | 2009-09-30 | 株式会社フジクラ | SUBSTRATE FOR MULTILAYER WIRING BOARD, DOUBLE WIRE WIRING BOARD AND METHOD FOR PRODUCING THEM |
US7495644B2 (en) | 2003-12-26 | 2009-02-24 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method for manufacturing display device |
JP3917133B2 (en) | 2003-12-26 | 2007-05-23 | 株式会社東芝 | LSI package with interface module and interposer, interface module, connection monitor circuit, signal processing LSI used therefor |
US6900530B1 (en) | 2003-12-29 | 2005-05-31 | Ramtek Technology, Inc. | Stacked IC |
US6917098B1 (en) | 2003-12-29 | 2005-07-12 | Texas Instruments Incorporated | Three-level leadframe for no-lead packages |
US7709968B2 (en) | 2003-12-30 | 2010-05-04 | Tessera, Inc. | Micro pin grid array with pin motion isolation |
US8207604B2 (en) | 2003-12-30 | 2012-06-26 | Tessera, Inc. | Microelectronic package comprising offset conductive posts on compliant layer |
US7176043B2 (en) | 2003-12-30 | 2007-02-13 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP2005203497A (en) | 2004-01-14 | 2005-07-28 | Toshiba Corp | Semiconductor device and method for manufacturing same |
US20050173807A1 (en) | 2004-02-05 | 2005-08-11 | Jianbai Zhu | High density vertically stacked semiconductor device |
US7198987B1 (en) | 2004-03-04 | 2007-04-03 | Skyworks Solutions, Inc. | Overmolded semiconductor package with an integrated EMI and RFI shield |
US8399972B2 (en) | 2004-03-04 | 2013-03-19 | Skyworks Solutions, Inc. | Overmolded semiconductor package with a wirebond cage for EMI shielding |
US7095105B2 (en) | 2004-03-23 | 2006-08-22 | Texas Instruments Incorporated | Vertically stacked semiconductor device |
JP4484035B2 (en) | 2004-04-06 | 2010-06-16 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
US8092734B2 (en) | 2004-05-13 | 2012-01-10 | Aptina Imaging Corporation | Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers |
US7629695B2 (en) | 2004-05-20 | 2009-12-08 | Kabushiki Kaisha Toshiba | Stacked electronic component and manufacturing method thereof |
US6962864B1 (en) | 2004-05-26 | 2005-11-08 | National Chung Cheng University | Wire-bonding method for chips with copper interconnects by introducing a thin layer |
US7233057B2 (en) | 2004-05-28 | 2007-06-19 | Nokia Corporation | Integrated circuit package with optimized mold shape |
TWI255022B (en) | 2004-05-31 | 2006-05-11 | Via Tech Inc | Circuit carrier and manufacturing process thereof |
US7453157B2 (en) | 2004-06-25 | 2008-11-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
TWI250596B (en) | 2004-07-23 | 2006-03-01 | Ind Tech Res Inst | Wafer-level chip scale packaging method |
JP3956965B2 (en) | 2004-09-07 | 2007-08-08 | 日立エーアイシー株式会社 | Chip component type light emitting device and wiring board therefor |
US7290448B2 (en) | 2004-09-10 | 2007-11-06 | Yamaha Corporation | Physical quantity sensor, lead frame, and manufacturing method therefor |
CN1755929B (en) | 2004-09-28 | 2010-08-18 | 飞思卡尔半导体(中国)有限公司 | Method for forming semiconductor package and its structure |
US7595548B2 (en) | 2004-10-08 | 2009-09-29 | Yamaha Corporation | Physical quantity sensor and manufacturing method therefor |
JP4385329B2 (en) | 2004-10-08 | 2009-12-16 | Okiセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
JP4671802B2 (en) | 2004-10-18 | 2011-04-20 | 富士通株式会社 | Plating method, semiconductor device manufacturing method, and circuit board manufacturing method |
US20060087013A1 (en) | 2004-10-21 | 2006-04-27 | Etron Technology, Inc. | Stacked multiple integrated circuit die package assembly |
US8646675B2 (en) | 2004-11-02 | 2014-02-11 | Hid Global Gmbh | Laying apparatus, contact-making apparatus, movement system, laying and contact-making unit, production system, method for production and a transponder unit |
CN101053079A (en) | 2004-11-03 | 2007-10-10 | 德塞拉股份有限公司 | Stacked packaging improvements |
TW200631111A (en) | 2004-11-04 | 2006-09-01 | Koninkl Philips Electronics Nv | Nanotube-based circuit connection approach |
US7268421B1 (en) | 2004-11-10 | 2007-09-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond |
US7750483B1 (en) | 2004-11-10 | 2010-07-06 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal |
JP4917257B2 (en) | 2004-11-12 | 2012-04-18 | 浜松ホトニクス株式会社 | Laser processing method |
KR100674926B1 (en) | 2004-12-08 | 2007-01-26 | 삼성전자주식회사 | Memory card and method of fabricating the same |
US7301770B2 (en) | 2004-12-10 | 2007-11-27 | International Business Machines Corporation | Cooling apparatus, cooled electronic module, and methods of fabrication thereof employing thermally conductive, wire-bonded pin fins |
JP4504798B2 (en) | 2004-12-16 | 2010-07-14 | パナソニック株式会社 | Multistage semiconductor module |
JP2006186086A (en) | 2004-12-27 | 2006-07-13 | Itoo:Kk | Method for soldering printed circuit board and guide plate for preventing bridge |
KR100843137B1 (en) | 2004-12-27 | 2008-07-02 | 삼성전자주식회사 | Semiconductor device package |
DE102005006333B4 (en) | 2005-02-10 | 2007-10-18 | Infineon Technologies Ag | Semiconductor device having a plurality of bonding terminals and bonded contact elements of different metal composition and method for producing the same |
DE102005006995B4 (en) | 2005-02-15 | 2008-01-24 | Infineon Technologies Ag | Semiconductor device with plastic housing and external connections and method for producing the same |
KR100867038B1 (en) | 2005-03-02 | 2008-11-04 | 삼성전기주식회사 | Printed circuit board with embedded capacitors, and manufacturing process thereof |
KR100630741B1 (en) | 2005-03-04 | 2006-10-02 | 삼성전자주식회사 | Stack type semiconductor package having a multiple molding process and manufacturing method thereof |
US7939934B2 (en) | 2005-03-16 | 2011-05-10 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7582963B2 (en) | 2005-03-29 | 2009-09-01 | Texas Instruments Incorporated | Vertically integrated system-in-a-package |
US7371676B2 (en) | 2005-04-08 | 2008-05-13 | Micron Technology, Inc. | Method for fabricating semiconductor components with through wire interconnects |
US7815323B2 (en) | 2005-05-04 | 2010-10-19 | Lang-Mekra North America, Llc | Mirror stabilizer arm connector assembly |
TWI284394B (en) | 2005-05-12 | 2007-07-21 | Advanced Semiconductor Eng | Lid used in package structure and the package structure of having the same |
JP2006324553A (en) | 2005-05-20 | 2006-11-30 | Renesas Technology Corp | Semiconductor device and method of manufacturing same |
US7528474B2 (en) | 2005-05-31 | 2009-05-05 | Stats Chippac Ltd. | Stacked semiconductor package assembly having hollowed substrate |
US7216794B2 (en) | 2005-06-09 | 2007-05-15 | Texas Instruments Incorporated | Bond capillary design for ribbon wire bonding |
JP4322844B2 (en) | 2005-06-10 | 2009-09-02 | シャープ株式会社 | Semiconductor device and stacked semiconductor device |
CN100550367C (en) | 2005-07-01 | 2009-10-14 | 皇家飞利浦电子股份有限公司 | Electronic device |
TWI294757B (en) | 2005-07-06 | 2008-03-11 | Delta Electronics Inc | Circuit board with a through hole wire, and forming method thereof |
US7476608B2 (en) | 2005-07-14 | 2009-01-13 | Hewlett-Packard Development Company, L.P. | Electrically connecting substrate with electrical device |
JP4787559B2 (en) | 2005-07-26 | 2011-10-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US7355289B2 (en) | 2005-07-29 | 2008-04-08 | Freescale Semiconductor, Inc. | Packaged integrated circuit with enhanced thermal dissipation |
TWI263313B (en) | 2005-08-15 | 2006-10-01 | Phoenix Prec Technology Corp | Stack structure of semiconductor component embedded in supporting board |
SG130055A1 (en) | 2005-08-19 | 2007-03-20 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices |
SG130066A1 (en) | 2005-08-26 | 2007-03-20 | Micron Technology Inc | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
JP5522561B2 (en) | 2005-08-31 | 2014-06-18 | マイクロン テクノロジー, インク. | Microelectronic device package, stacked microelectronic device package, and method of manufacturing microelectronic device |
US7485969B2 (en) | 2005-09-01 | 2009-02-03 | Micron Technology, Inc. | Stacked microelectronic devices and methods for manufacturing microelectronic devices |
US7675152B2 (en) | 2005-09-01 | 2010-03-09 | Texas Instruments Incorporated | Package-on-package semiconductor assembly |
US20070080360A1 (en) | 2005-10-06 | 2007-04-12 | Url Mirsky | Microelectronic interconnect substrate and packaging techniques |
KR101241650B1 (en) | 2005-10-19 | 2013-03-08 | 엘지이노텍 주식회사 | Package of light emitting diode |
US8810031B2 (en) | 2005-10-26 | 2014-08-19 | Industrial Technology Research Institute | Wafer-to-wafer stack with supporting pedestal |
US7504716B2 (en) | 2005-10-26 | 2009-03-17 | Texas Instruments Incorporated | Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking |
JP2007123595A (en) | 2005-10-28 | 2007-05-17 | Nec Corp | Semiconductor device and its mounting structure |
US8183682B2 (en) | 2005-11-01 | 2012-05-22 | Nxp B.V. | Methods of packaging a semiconductor die and package formed by the methods |
JP4530975B2 (en) | 2005-11-14 | 2010-08-25 | 株式会社新川 | Wire bonding method |
JP2007142042A (en) | 2005-11-16 | 2007-06-07 | Sharp Corp | Semiconductor package, manufacturing method thereof, semiconductor module, and electronic equipment |
US7344917B2 (en) | 2005-11-30 | 2008-03-18 | Freescale Semiconductor, Inc. | Method for packaging a semiconductor device |
US7307348B2 (en) | 2005-12-07 | 2007-12-11 | Micron Technology, Inc. | Semiconductor components having through wire interconnects (TWI) |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP4530984B2 (en) | 2005-12-28 | 2010-08-25 | 株式会社新川 | Wire bonding apparatus, bonding control program, and bonding method |
US7378726B2 (en) | 2005-12-28 | 2008-05-27 | Intel Corporation | Stacked packages with interconnecting pins |
JP2007194436A (en) | 2006-01-19 | 2007-08-02 | Elpida Memory Inc | Semiconductor package and manufacturing method thereof, substrate with conductive post, and laminated semiconductor device and manufacturing method thereof |
US20070190747A1 (en) | 2006-01-23 | 2007-08-16 | Tessera Technologies Hungary Kft. | Wafer level packaging to lidded chips |
JP2007201254A (en) | 2006-01-27 | 2007-08-09 | Ibiden Co Ltd | Built-in semiconductor-element including board, and built-in semiconductor-element including multilayer circuit board |
JP2007208159A (en) | 2006-02-06 | 2007-08-16 | Hitachi Ltd | Semiconductor device |
SG135074A1 (en) | 2006-02-28 | 2007-09-28 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
TWI295115B (en) | 2006-02-13 | 2008-03-21 | Ind Tech Res Inst | Encapsulation and methods thereof |
JP2007234845A (en) | 2006-03-01 | 2007-09-13 | Nec Corp | Semiconductor device |
US7876180B2 (en) | 2006-03-09 | 2011-01-25 | Kyocera Corporation | Waveguide forming apparatus, dielectric waveguide forming apparatus, pin structure, and high frequency circuit |
US7759782B2 (en) | 2006-04-07 | 2010-07-20 | Tessera, Inc. | Substrate for a microelectronic package and method of fabricating thereof |
US7390700B2 (en) | 2006-04-07 | 2008-06-24 | Texas Instruments Incorporated | Packaged system of semiconductor chips having a semiconductor interposer |
WO2007116544A1 (en) | 2006-04-10 | 2007-10-18 | Murata Manufacturing Co., Ltd. | Composite substrate and method of manufacturing composite substrate |
JP5598787B2 (en) | 2006-04-17 | 2014-10-01 | マイクロンメモリジャパン株式会社 | Manufacturing method of stacked semiconductor device |
US7242081B1 (en) | 2006-04-24 | 2007-07-10 | Advanced Semiconductor Engineering Inc. | Stacked package structure |
US7659612B2 (en) | 2006-04-24 | 2010-02-09 | Micron Technology, Inc. | Semiconductor components having encapsulated through wire interconnects (TWI) |
US7910385B2 (en) | 2006-05-12 | 2011-03-22 | Micron Technology, Inc. | Method of fabricating microelectronic devices |
DE102006022360B4 (en) | 2006-05-12 | 2009-07-09 | Infineon Technologies Ag | shielding |
US7780064B2 (en) | 2006-06-02 | 2010-08-24 | Asm Technology Singapore Pte Ltd | Wire bonding method for forming low-loop profiles |
JP4961848B2 (en) | 2006-06-12 | 2012-06-27 | 日本電気株式会社 | WIRING BOARD HAVING METAL POST, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MODULE MANUFACTURING METHOD |
US7967062B2 (en) | 2006-06-16 | 2011-06-28 | International Business Machines Corporation | Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof |
US20070290325A1 (en) | 2006-06-16 | 2007-12-20 | Lite-On Semiconductor Corporation | Surface mounting structure and packaging method thereof |
WO2008014633A1 (en) | 2006-06-29 | 2008-02-07 | Intel Corporation | Apparatus, system, and method for wireless connection in integrated circuit packages |
KR100792352B1 (en) | 2006-07-06 | 2008-01-08 | 삼성전기주식회사 | Bottom substrate of pop and manufacturing method thereof |
US7612638B2 (en) | 2006-07-14 | 2009-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Waveguides in integrated circuits |
SG139573A1 (en) | 2006-07-17 | 2008-02-29 | Micron Technology Inc | Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods |
KR100800478B1 (en) | 2006-07-18 | 2008-02-04 | 삼성전자주식회사 | Stack type semiconductor package and method of fabricating the same |
US20080023805A1 (en) | 2006-07-26 | 2008-01-31 | Texas Instruments Incorporated | Array-Processed Stacked Semiconductor Packages |
JP5132101B2 (en) | 2006-07-27 | 2013-01-30 | 新光電気工業株式会社 | Stack package structure, unit package used for manufacturing the same, and manufacturing method |
US8048479B2 (en) | 2006-08-01 | 2011-11-01 | Qimonda Ag | Method for placing material onto a target board by means of a transfer board |
JP2008039502A (en) | 2006-08-03 | 2008-02-21 | Alps Electric Co Ltd | Contact and its manufacturing method |
US7486525B2 (en) | 2006-08-04 | 2009-02-03 | International Business Machines Corporation | Temporary chip attach carrier |
KR100809696B1 (en) | 2006-08-08 | 2008-03-06 | 삼성전자주식회사 | A Multi chip package stacked a plurality of semiconductor chips having different size and method of manufacturing the same |
US20080042265A1 (en) | 2006-08-15 | 2008-02-21 | Merilo Leo A | Chip scale module package in bga semiconductor package |
US7425758B2 (en) | 2006-08-28 | 2008-09-16 | Micron Technology, Inc. | Metal core foldover package structures |
KR20080020069A (en) | 2006-08-30 | 2008-03-05 | 삼성전자주식회사 | Semiconductor package and method for fabricating the same |
US7560360B2 (en) | 2006-08-30 | 2009-07-14 | International Business Machines Corporation | Methods for enhancing trench capacitance and trench capacitor |
KR100891516B1 (en) | 2006-08-31 | 2009-04-06 | 주식회사 하이닉스반도체 | Stackable fbga type semiconductor package and stack package using the same |
US7683460B2 (en) | 2006-09-22 | 2010-03-23 | Infineon Technologies Ag | Module with a shielding and/or heat dissipating element |
KR100770934B1 (en) | 2006-09-26 | 2007-10-26 | 삼성전자주식회사 | Semiconductor package and semiconductor system in package |
TWI336502B (en) | 2006-09-27 | 2011-01-21 | Advanced Semiconductor Eng | Semiconductor package and semiconductor device and the method of making the same |
US7901989B2 (en) | 2006-10-10 | 2011-03-08 | Tessera, Inc. | Reconstituted wafer level stacking |
TWI312561B (en) | 2006-10-27 | 2009-07-21 | Advanced Semiconductor Eng | Structure of package on package and method for fabricating the same |
KR100817073B1 (en) | 2006-11-03 | 2008-03-26 | 삼성전자주식회사 | Semiconductor chip stack package with reinforce member for preventing package warpage connected to pcb |
WO2008065896A1 (en) | 2006-11-28 | 2008-06-05 | Kyushu Institute Of Technology | Method for manufacturing semiconductor device having dual-face electrode structure and semiconductor device manufactured by the method |
US7659617B2 (en) | 2006-11-30 | 2010-02-09 | Tessera, Inc. | Substrate for a flexible microelectronic assembly and a method of fabricating thereof |
US7537962B2 (en) | 2006-12-22 | 2009-05-26 | Stats Chippac Ltd. | Method of fabricating a shielded stacked integrated circuit package system |
JP2008166439A (en) | 2006-12-27 | 2008-07-17 | Spansion Llc | Semiconductor device and manufacturing method thereof |
US8598717B2 (en) | 2006-12-27 | 2013-12-03 | Spansion Llc | Semiconductor device and method for manufacturing the same |
DE102007062787A1 (en) | 2006-12-29 | 2008-07-17 | Qimonda Ag | Semiconductor arrangement for use in integrated circuit, has organic solderability preservative material applied to one of substrate and semiconductor chip, and copper wire wire-bonded to one of chip and substrate by material |
KR100757345B1 (en) | 2006-12-29 | 2007-09-10 | 삼성전자주식회사 | Flip chip package and method of manufacturing the same |
US20080156518A1 (en) | 2007-01-03 | 2008-07-03 | Tessera, Inc. | Alignment and cutting of microelectronic substrates |
TWI332702B (en) | 2007-01-09 | 2010-11-01 | Advanced Semiconductor Eng | Stackable semiconductor package and the method for making the same |
JP5347222B2 (en) | 2007-01-10 | 2013-11-20 | 富士通株式会社 | Manufacturing method of semiconductor device |
US7719122B2 (en) | 2007-01-11 | 2010-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | System-in-package packaging for minimizing bond wire contamination and yield loss |
KR100827667B1 (en) | 2007-01-16 | 2008-05-07 | 삼성전자주식회사 | Semiconductor package having semiconductor chip in substrate and method of fabricating the same |
WO2008093414A1 (en) | 2007-01-31 | 2008-08-07 | Fujitsu Microelectronics Limited | Semiconductor device and method for manufacturing the same |
JP4823089B2 (en) | 2007-01-31 | 2011-11-24 | 株式会社東芝 | Manufacturing method of stacked semiconductor device |
US8685792B2 (en) | 2007-03-03 | 2014-04-01 | Stats Chippac Ltd. | Integrated circuit package system with interposer |
KR101460141B1 (en) | 2007-03-05 | 2014-12-02 | 인벤사스 코포레이션 | Chips having rear contacts connected by through vias to front contacts |
US20080217708A1 (en) | 2007-03-09 | 2008-09-11 | Skyworks Solutions, Inc. | Integrated passive cap in a system-in-package |
JP5010316B2 (en) | 2007-03-16 | 2012-08-29 | 日本電気株式会社 | Wiring board having a metal post, semiconductor device |
US7517733B2 (en) | 2007-03-22 | 2009-04-14 | Stats Chippac, Ltd. | Leadframe design for QFN package with top terminal leads |
US8183684B2 (en) | 2007-03-23 | 2012-05-22 | Semiconductor Components Industries, Llc | Semiconductor device and method of manufacturing the same |
US8198716B2 (en) | 2007-03-26 | 2012-06-12 | Intel Corporation | Die backside wire bond technology for single or stacked die package |
WO2008120755A1 (en) | 2007-03-30 | 2008-10-09 | Nec Corporation | Circuit board incorporating functional element, method for manufacturing the circuit board, and electronic device |
JP4926787B2 (en) | 2007-03-30 | 2012-05-09 | アオイ電子株式会社 | Manufacturing method of semiconductor device |
US20080246126A1 (en) * | 2007-04-04 | 2008-10-09 | Freescale Semiconductor, Inc. | Stacked and shielded die packages with interconnects |
US7589394B2 (en) | 2007-04-10 | 2009-09-15 | Ibiden Co., Ltd. | Interposer |
JP5003260B2 (en) | 2007-04-13 | 2012-08-15 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US7994622B2 (en) | 2007-04-16 | 2011-08-09 | Tessera, Inc. | Microelectronic packages having cavities for receiving microelectric elements |
KR20080094251A (en) | 2007-04-19 | 2008-10-23 | 삼성전자주식회사 | Wafer level package and method for the manufacturing same |
JP5601751B2 (en) | 2007-04-26 | 2014-10-08 | スパンション エルエルシー | Semiconductor device |
US20080280393A1 (en) | 2007-05-09 | 2008-11-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for forming package structures |
US20080284045A1 (en) | 2007-05-18 | 2008-11-20 | Texas Instruments Incorporated | Method for Fabricating Array-Molded Package-On-Package |
TWI371809B (en) | 2007-06-04 | 2012-09-01 | Advanced Semiconductor Eng | Wafer structure and method for fabricating the same |
US7872335B2 (en) | 2007-06-08 | 2011-01-18 | Broadcom Corporation | Lead frame-BGA package with enhanced thermal performance and I/O counts |
JP2008306128A (en) | 2007-06-11 | 2008-12-18 | Shinko Electric Ind Co Ltd | Semiconductor device and its production process |
KR100865125B1 (en) | 2007-06-12 | 2008-10-24 | 삼성전기주식회사 | Semiconductor and method for manufacturing thereof |
TW200908819A (en) | 2007-06-15 | 2009-02-16 | Ngk Spark Plug Co | Wiring substrate with reinforcing member |
US7576415B2 (en) | 2007-06-15 | 2009-08-18 | Advanced Semiconductor Engineering, Inc. | EMI shielded semiconductor package |
JP5179787B2 (en) | 2007-06-22 | 2013-04-10 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
US7944034B2 (en) | 2007-06-22 | 2011-05-17 | Texas Instruments Incorporated | Array molded package-on-package having redistribution lines |
US7911805B2 (en) | 2007-06-29 | 2011-03-22 | Tessera, Inc. | Multilayer wiring element having pin interface |
SG148901A1 (en) | 2007-07-09 | 2009-01-29 | Micron Technology Inc | Packaged semiconductor assemblies and methods for manufacturing such assemblies |
KR20090007120A (en) | 2007-07-13 | 2009-01-16 | 삼성전자주식회사 | An wafer level stacked package having a via contact in encapsulation portion and manufacturing method thereof |
US7781877B2 (en) | 2007-08-07 | 2010-08-24 | Micron Technology, Inc. | Packaged integrated circuit devices with through-body conductive vias, and methods of making same |
JP2009044110A (en) | 2007-08-13 | 2009-02-26 | Elpida Memory Inc | Semiconductor device and its manufacturing method |
SG150396A1 (en) | 2007-08-16 | 2009-03-30 | Micron Technology Inc | Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods |
KR101329355B1 (en) | 2007-08-31 | 2013-11-20 | 삼성전자주식회사 | stack-type semicondoctor package, method of forming the same and electronic system including the same |
KR101365621B1 (en) | 2007-09-04 | 2014-02-24 | 서울반도체 주식회사 | Light emitting diode package having heat dissipating slugs |
JP2009064966A (en) | 2007-09-06 | 2009-03-26 | Shinko Electric Ind Co Ltd | Multilayer wiring board and manufacturing method thereof, and semiconductor device |
US7808439B2 (en) | 2007-09-07 | 2010-10-05 | University Of Tennessee Reserch Foundation | Substrate integrated waveguide antenna array |
US9330945B2 (en) | 2007-09-18 | 2016-05-03 | Stats Chippac Ltd. | Integrated circuit package system with multi-chip module |
US8039960B2 (en) | 2007-09-21 | 2011-10-18 | Stats Chippac, Ltd. | Solder bump with inner core pillar in semiconductor package |
US8558379B2 (en) | 2007-09-28 | 2013-10-15 | Tessera, Inc. | Flip chip interconnection with double post |
JP2009088254A (en) | 2007-09-28 | 2009-04-23 | Toshiba Corp | Electronic component package, and manufacturing method for electronic component package |
KR100902128B1 (en) | 2007-09-28 | 2009-06-09 | 삼성전기주식회사 | Heat radiating printed circuit board and semiconductor chip package |
KR20090033605A (en) | 2007-10-01 | 2009-04-06 | 삼성전자주식회사 | Stack-type semicondoctor package, method of forming the same and electronic system including the same |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US20090091009A1 (en) | 2007-10-03 | 2009-04-09 | Corisis David J | Stackable integrated circuit package |
US8008183B2 (en) | 2007-10-04 | 2011-08-30 | Texas Instruments Incorporated | Dual capillary IC wirebonding |
US7834464B2 (en) | 2007-10-09 | 2010-11-16 | Infineon Technologies Ag | Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device |
TWI360207B (en) | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
TWI389220B (en) | 2007-10-22 | 2013-03-11 | 矽品精密工業股份有限公司 | Semiconductor package and method for fabricating the same |
FR2923081B1 (en) | 2007-10-26 | 2009-12-11 | 3D Plus | PROCESS FOR VERTICAL INTERCONNECTION OF 3D ELECTRONIC MODULES BY VIAS. |
GB0721957D0 (en) | 2007-11-08 | 2007-12-19 | Photonstar Led Ltd | Ultra high thermal performance packaging for optoelectronics devices |
JP2009123863A (en) | 2007-11-14 | 2009-06-04 | Tessera Interconnect Materials Inc | Method of forming bump structure and the bump structure |
EP2220430A4 (en) | 2007-11-19 | 2010-12-22 | Nexxus Lighting Inc | Apparatus and methods for thermal management of light emitting diodes |
US20090127686A1 (en) | 2007-11-21 | 2009-05-21 | Advanced Chip Engineering Technology Inc. | Stacking die package structure for semiconductor devices and method of the same |
KR100886100B1 (en) | 2007-11-29 | 2009-02-27 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and method for manufacturing the same |
JP2009135398A (en) | 2007-11-29 | 2009-06-18 | Ibiden Co Ltd | Combination substrate |
US7902644B2 (en) | 2007-12-07 | 2011-03-08 | Stats Chippac Ltd. | Integrated circuit package system for electromagnetic isolation |
US7696631B2 (en) | 2007-12-10 | 2010-04-13 | International Business Machines Corporation | Wire bonding personalization and discrete component attachment on wirebond pads |
US7964956B1 (en) | 2007-12-10 | 2011-06-21 | Oracle America, Inc. | Circuit packaging and connectivity |
US8390117B2 (en) | 2007-12-11 | 2013-03-05 | Panasonic Corporation | Semiconductor device and method of manufacturing the same |
US7706144B2 (en) | 2007-12-17 | 2010-04-27 | Lynch Thomas W | Heat dissipation system and related method |
JP2009158593A (en) | 2007-12-25 | 2009-07-16 | Tessera Interconnect Materials Inc | Bump structure and method of manufacturing the same |
US20090170241A1 (en) | 2007-12-26 | 2009-07-02 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
US20090166873A1 (en) | 2007-12-27 | 2009-07-02 | Advanced Chip Engineering Technology Inc. | Inter-connecting structure for semiconductor device package and method of the same |
JP4989614B2 (en) | 2007-12-28 | 2012-08-01 | サムソン エルイーディー カンパニーリミテッド. | High power LED package manufacturing method |
WO2009096950A1 (en) | 2008-01-30 | 2009-08-06 | Kulicke And Soffa Industries, Inc. | Wire loop and method of forming the wire loop |
US20090194829A1 (en) | 2008-01-31 | 2009-08-06 | Shine Chung | MEMS Packaging Including Integrated Circuit Dies |
US8120186B2 (en) | 2008-02-15 | 2012-02-21 | Qimonda Ag | Integrated circuit and method |
US8258015B2 (en) | 2008-02-22 | 2012-09-04 | Stats Chippac Ltd. | Integrated circuit package system with penetrable film adhesive |
US7956456B2 (en) | 2008-02-27 | 2011-06-07 | Texas Instruments Incorporated | Thermal interface material design for enhanced thermal performance and improved package structural integrity |
US8018065B2 (en) | 2008-02-28 | 2011-09-13 | Atmel Corporation | Wafer-level integrated circuit package with top and bottom side electrical connections |
KR101501739B1 (en) | 2008-03-21 | 2015-03-11 | 삼성전자주식회사 | Method of Fabricating Semiconductor Packages |
US7919871B2 (en) | 2008-03-21 | 2011-04-05 | Stats Chippac Ltd. | Integrated circuit package system for stackable devices |
US8525214B2 (en) | 2008-03-25 | 2013-09-03 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader with thermal via |
US8072079B2 (en) | 2008-03-27 | 2011-12-06 | Stats Chippac, Ltd. | Through hole vias at saw streets including protrusions or recesses for interconnection |
CN101978490B (en) | 2008-03-31 | 2012-10-17 | 株式会社村田制作所 | Electronic component module and method of manufacturing the electronic component module |
JP5043743B2 (en) | 2008-04-18 | 2012-10-10 | ラピスセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
US7741156B2 (en) | 2008-05-27 | 2010-06-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming through vias with reflowed conductive material |
KR20090123680A (en) | 2008-05-28 | 2009-12-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
US8093704B2 (en) | 2008-06-03 | 2012-01-10 | Intel Corporation | Package on package using a bump-less build up layer (BBUL) package |
US8021907B2 (en) | 2008-06-09 | 2011-09-20 | Stats Chippac, Ltd. | Method and apparatus for thermally enhanced semiconductor package |
WO2009154761A1 (en) | 2008-06-16 | 2009-12-23 | Tessera Research Llc | Stacking of wafer-level chip scale packages having edge contacts |
US7932170B1 (en) | 2008-06-23 | 2011-04-26 | Amkor Technology, Inc. | Flip chip bump structure and fabrication method |
DE102008048420A1 (en) | 2008-06-27 | 2010-01-28 | Qimonda Ag | Chip arrangement and method for producing a chip arrangement |
US7969009B2 (en) | 2008-06-30 | 2011-06-28 | Qualcomm Incorporated | Through silicon via bridge interconnect |
TWI473553B (en) | 2008-07-03 | 2015-02-11 | Advanced Semiconductor Eng | Chip package structure |
US7859033B2 (en) | 2008-07-09 | 2010-12-28 | Eastman Kodak Company | Wafer level processing for backside illuminated sensors |
JP5339800B2 (en) | 2008-07-10 | 2013-11-13 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
TWI372453B (en) | 2008-09-01 | 2012-09-11 | Advanced Semiconductor Eng | Copper bonding wire, wire bonding structure and method for processing and bonding a wire |
TWI573201B (en) | 2008-07-18 | 2017-03-01 | 聯測總部私人有限公司 | Packaging structural member |
US8923004B2 (en) | 2008-07-31 | 2014-12-30 | Micron Technology, Inc. | Microelectronic packages with small footprints and associated methods of manufacturing |
WO2010014103A1 (en) | 2008-07-31 | 2010-02-04 | Skyworks Solutions, Inc. | Semiconductor package with integrated interference shielding and method of manufacture therof |
US8004093B2 (en) | 2008-08-01 | 2011-08-23 | Stats Chippac Ltd. | Integrated circuit package stacking system |
US7800810B2 (en) | 2008-08-06 | 2010-09-21 | Spatial Photonics, Inc. | Packaging and testing of multiple MEMS devices on a wafer |
TW201007924A (en) | 2008-08-07 | 2010-02-16 | Advanced Semiconductor Eng | Chip package structure |
US20100044860A1 (en) | 2008-08-21 | 2010-02-25 | Tessera Interconnect Materials, Inc. | Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer |
KR20100026556A (en) | 2008-08-30 | 2010-03-10 | 박민호 | Safty boxing ring |
KR100997793B1 (en) | 2008-09-01 | 2010-12-02 | 주식회사 하이닉스반도체 | Semiconductor pacakge and method of manufacturing thereof |
KR20100033012A (en) | 2008-09-19 | 2010-03-29 | 주식회사 하이닉스반도체 | Semiconductor package and stacked semiconductor package having the same |
US7842541B1 (en) | 2008-09-24 | 2010-11-30 | Amkor Technology, Inc. | Ultra thin package and fabrication method |
US8237257B2 (en) | 2008-09-25 | 2012-08-07 | King Dragon International Inc. | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same |
US8063475B2 (en) | 2008-09-26 | 2011-11-22 | Stats Chippac Ltd. | Semiconductor package system with through silicon via interposer |
JP5185062B2 (en) | 2008-10-21 | 2013-04-17 | パナソニック株式会社 | Multilayer semiconductor device and electronic device |
MY149251A (en) | 2008-10-23 | 2013-07-31 | Carsem M Sdn Bhd | Wafer-level package using stud bump coated with solder |
KR101461630B1 (en) | 2008-11-06 | 2014-11-20 | 삼성전자주식회사 | Wafer level chip on chip package, package on package improving solder joint reliability but reducing mounting height and manufacturing method thereof |
TW201023308A (en) | 2008-12-01 | 2010-06-16 | Advanced Semiconductor Eng | Package-on-package device, semiconductor package and method for manufacturing the same |
KR101011863B1 (en) | 2008-12-02 | 2011-01-31 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating?method thereof |
KR101015651B1 (en) | 2008-12-05 | 2011-02-22 | 삼성전기주식회사 | Chip embedded printed circuit board and manufacturing method thereof |
JP2010135671A (en) | 2008-12-08 | 2010-06-17 | Panasonic Corp | Semiconductor equipment and method of manufacturing the same |
US7642128B1 (en) | 2008-12-12 | 2010-01-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
US7898083B2 (en) | 2008-12-17 | 2011-03-01 | Texas Instruments Incorporated | Method for low stress flip-chip assembly of fine-pitch semiconductor devices |
US8012797B2 (en) | 2009-01-07 | 2011-09-06 | Advanced Semiconductor Engineering, Inc. | Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries |
TWI499024B (en) | 2009-01-07 | 2015-09-01 | Advanced Semiconductor Eng | Package-on-package device, semiconductor package and method for manufacturing the same |
JP2010199528A (en) | 2009-01-27 | 2010-09-09 | Tatsuta System Electronics Kk | Bonding wire |
JP2010177597A (en) | 2009-01-30 | 2010-08-12 | Sanyo Electric Co Ltd | Semiconductor module and portable device |
US20100200981A1 (en) | 2009-02-09 | 2010-08-12 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method of manufacturing the same |
US9142586B2 (en) | 2009-02-24 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for backside illuminated image sensor |
JP2010206007A (en) | 2009-03-04 | 2010-09-16 | Nec Corp | Semiconductor device and method of manufacturing the same |
US8115283B1 (en) | 2009-07-14 | 2012-02-14 | Amkor Technology, Inc. | Reversible top/bottom MEMS package |
JP5471605B2 (en) | 2009-03-04 | 2014-04-16 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US8106498B2 (en) | 2009-03-05 | 2012-01-31 | Stats Chippac Ltd. | Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof |
DE102009001461A1 (en) | 2009-03-11 | 2010-09-16 | Robert Bosch Gmbh | Method for producing an electronic assembly |
US8258010B2 (en) | 2009-03-17 | 2012-09-04 | Stats Chippac, Ltd. | Making a semiconductor device having conductive through organic vias |
US20100244276A1 (en) | 2009-03-25 | 2010-09-30 | Lsi Corporation | Three-dimensional electronics package |
US20110068478A1 (en) | 2009-03-26 | 2011-03-24 | Reza Argenty Pagaila | Integrated circuit packaging system with package stacking and method of manufacture thereof |
US8194411B2 (en) | 2009-03-31 | 2012-06-05 | Hong Kong Applied Science and Technology Research Institute Co. Ltd | Electronic package with stacked modules with channels passing through metal layers of the modules |
US8053814B2 (en) | 2009-04-08 | 2011-11-08 | International Business Machines Corporation | On-chip embedded thermal antenna for chip cooling |
US8039316B2 (en) | 2009-04-14 | 2011-10-18 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof |
JP2010251483A (en) | 2009-04-14 | 2010-11-04 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
US20100289142A1 (en) | 2009-05-15 | 2010-11-18 | Il Kwon Shim | Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof |
TWI379367B (en) | 2009-06-15 | 2012-12-11 | Kun Yuan Technology Co Ltd | Chip packaging method and structure thereof |
US20120153444A1 (en) | 2009-06-18 | 2012-06-21 | Rohm Co., Ltd | Semiconductor device |
US20100327419A1 (en) | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
JP5214554B2 (en) | 2009-07-30 | 2013-06-19 | ラピスセミコンダクタ株式会社 | Semiconductor chip built-in package and manufacturing method thereof, and package-on-package semiconductor device and manufacturing method thereof |
US8183678B2 (en) | 2009-08-04 | 2012-05-22 | Amkor Technology Korea, Inc. | Semiconductor device having an interposer |
US20110209908A1 (en) | 2009-08-06 | 2011-09-01 | Advanced Chip Engineering Technology Inc. | Conductor package structure and method of the same |
KR101124102B1 (en) | 2009-08-24 | 2012-03-21 | 삼성전기주식회사 | Substrate for light emitting device package and light emitting device package comprising the same |
EP2290686A3 (en) | 2009-08-28 | 2011-04-20 | STMicroelectronics S.r.l. | Method to perform electrical testing and assembly of electronic devices |
US7923304B2 (en) | 2009-09-10 | 2011-04-12 | Stats Chippac Ltd. | Integrated circuit packaging system with conductive pillars and method of manufacture thereof |
US8264091B2 (en) | 2009-09-21 | 2012-09-11 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulated via and method of manufacture thereof |
US8008121B2 (en) | 2009-11-04 | 2011-08-30 | Stats Chippac, Ltd. | Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate |
US8390108B2 (en) | 2009-12-16 | 2013-03-05 | Stats Chippac Ltd. | Integrated circuit packaging system with stacking interconnect and method of manufacture thereof |
US8169065B2 (en) | 2009-12-22 | 2012-05-01 | Epic Technologies, Inc. | Stackable circuit structures and methods of fabrication thereof |
TW201123387A (en) | 2009-12-25 | 2011-07-01 | xiang-hua Wang | Thermal-electric separated metal PCB with a chip carrier. |
TWI392066B (en) | 2009-12-28 | 2013-04-01 | 矽品精密工業股份有限公司 | Package structure and fabrication method thereof |
JP5550369B2 (en) | 2010-02-03 | 2014-07-16 | 新日鉄住金マテリアルズ株式会社 | Copper bonding wire for semiconductor and its bonding structure |
JP2011166051A (en) | 2010-02-15 | 2011-08-25 | Panasonic Corp | Semiconductor device and method of manufacturing the same |
US7990711B1 (en) | 2010-02-24 | 2011-08-02 | International Business Machines Corporation | Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate |
US9496152B2 (en) | 2010-03-12 | 2016-11-15 | STATS ChipPAC Pte. Ltd. | Carrier system with multi-tier conductive posts and method of manufacture thereof |
US7928552B1 (en) | 2010-03-12 | 2011-04-19 | Stats Chippac Ltd. | Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof |
KR101667656B1 (en) | 2010-03-24 | 2016-10-20 | 삼성전자주식회사 | Method of forming package on package |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8564141B2 (en) | 2010-05-06 | 2013-10-22 | SK Hynix Inc. | Chip unit and stack package having the same |
US8558392B2 (en) | 2010-05-14 | 2013-10-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant |
US8288854B2 (en) | 2010-05-19 | 2012-10-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for making the same |
US8217502B2 (en) | 2010-06-08 | 2012-07-10 | Stats Chippac Ltd. | Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof |
US20120001336A1 (en) | 2010-07-02 | 2012-01-05 | Texas Instruments Incorporated | Corrosion-resistant copper-to-aluminum bonds |
US8330272B2 (en) | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
KR20120007839A (en) | 2010-07-15 | 2012-01-25 | 삼성전자주식회사 | Manufacturing method of stack type package |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
JP5713598B2 (en) | 2010-07-20 | 2015-05-07 | 新光電気工業株式会社 | Socket and manufacturing method thereof |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8847376B2 (en) | 2010-07-23 | 2014-09-30 | Tessera, Inc. | Microelectronic elements with post-assembly planarization |
KR101683814B1 (en) | 2010-07-26 | 2016-12-08 | 삼성전자주식회사 | Semiconductor apparatus having through vias |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US8304900B2 (en) | 2010-08-11 | 2012-11-06 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked lead and method of manufacture thereof |
US8076184B1 (en) | 2010-08-16 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die |
US8518746B2 (en) | 2010-09-02 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die |
US8354297B2 (en) | 2010-09-03 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die |
US8080445B1 (en) | 2010-09-07 | 2011-12-20 | Stats Chippac, Ltd. | Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers |
US20120063090A1 (en) | 2010-09-09 | 2012-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cooling mechanism for stacked die package and method of manufacturing the same |
US8409922B2 (en) | 2010-09-14 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect |
US8415704B2 (en) | 2010-09-22 | 2013-04-09 | Ut-Battelle, Llc | Close-packed array of light emitting devices |
US8349735B2 (en) | 2010-09-22 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive TSV with insulating annular ring |
US9224647B2 (en) | 2010-09-24 | 2015-12-29 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer |
JP5616739B2 (en) | 2010-10-01 | 2014-10-29 | 新日鉄住金マテリアルズ株式会社 | Multilayer copper bonding wire bonding structure |
US20120080787A1 (en) | 2010-10-05 | 2012-04-05 | Qualcomm Incorporated | Electronic Package and Method of Making an Electronic Package |
CN102024782B (en) | 2010-10-12 | 2012-07-25 | 北京大学 | Three-dimensional vertical interconnecting structure and manufacturing method thereof |
JP2012104790A (en) | 2010-10-12 | 2012-05-31 | Elpida Memory Inc | Semiconductor device |
US8618646B2 (en) | 2010-10-12 | 2013-12-31 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
JP5591653B2 (en) | 2010-10-27 | 2014-09-17 | 東和精工株式会社 | Label peeling machine |
US8263435B2 (en) | 2010-10-28 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias |
US8697492B2 (en) | 2010-11-02 | 2014-04-15 | Tessera, Inc. | No flow underfill |
US8525318B1 (en) | 2010-11-10 | 2013-09-03 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
KR101075241B1 (en) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | Microelectronic package with terminals on dielectric mass |
JPWO2012067177A1 (en) | 2010-11-17 | 2014-05-12 | 株式会社フジクラ | Wiring board and manufacturing method thereof |
KR20120056052A (en) | 2010-11-24 | 2012-06-01 | 삼성전자주식회사 | Semiconductor Package |
US8502387B2 (en) | 2010-12-09 | 2013-08-06 | Stats Chippac Ltd. | Integrated circuit packaging system with vertical interconnection and method of manufacture thereof |
US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
US8772817B2 (en) | 2010-12-22 | 2014-07-08 | Cree, Inc. | Electronic device submounts including substrates with thermally conductive vias |
US8736065B2 (en) | 2010-12-22 | 2014-05-27 | Intel Corporation | Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same |
KR101215271B1 (en) | 2010-12-29 | 2012-12-26 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package structure and method of manufacturing the same |
US20120184116A1 (en) | 2011-01-18 | 2012-07-19 | Tyco Electronics Corporation | Interposer |
US8766436B2 (en) | 2011-03-01 | 2014-07-01 | Lsi Corporation | Moisture barrier for a wire bond |
US8508045B2 (en) | 2011-03-03 | 2013-08-13 | Broadcom Corporation | Package 3D interconnection and method of making same |
US8841765B2 (en) | 2011-04-22 | 2014-09-23 | Tessera, Inc. | Multi-chip module with stacked face-down connected dies |
US9508622B2 (en) | 2011-04-28 | 2016-11-29 | Freescale Semiconductor, Inc. | Method for protecting copper wire bonds on aluminum pads of a semiconductor device from corrosion |
US8476115B2 (en) | 2011-05-03 | 2013-07-02 | Stats Chippac, Ltd. | Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
KR101128063B1 (en) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | Package-on-package assembly with wire bonds to encapsulation surface |
US8633059B2 (en) | 2011-05-11 | 2014-01-21 | Stats Chippac Ltd. | Integrated circuit packaging system with interconnect and method of manufacture thereof |
US8669646B2 (en) | 2011-05-31 | 2014-03-11 | Broadcom Corporation | Apparatus and method for grounding an IC package lid for EMI reduction |
US9128123B2 (en) | 2011-06-03 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interposer test structures and methods |
US9117811B2 (en) | 2011-06-13 | 2015-08-25 | Tessera, Inc. | Flip chip assembly and process with sintering material on metal bumps |
US9006031B2 (en) | 2011-06-23 | 2015-04-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps |
KR20130007049A (en) | 2011-06-28 | 2013-01-18 | 삼성전자주식회사 | Package on package using through silicon via technique |
US9449941B2 (en) | 2011-07-07 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting function chips to a package to form package-on-package |
US8476770B2 (en) | 2011-07-07 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and methods for forming through vias |
US8816505B2 (en) | 2011-07-29 | 2014-08-26 | Tessera, Inc. | Low stress vias |
US8487421B2 (en) | 2011-08-01 | 2013-07-16 | Tessera, Inc. | Microelectronic package with stacked microelectronic elements and method for manufacture thereof |
US8937309B2 (en) | 2011-08-08 | 2015-01-20 | Micron Technology, Inc. | Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication |
US20130037929A1 (en) | 2011-08-09 | 2013-02-14 | Kay S. Essig | Stackable wafer level packages and related methods |
US20130040423A1 (en) | 2011-08-10 | 2013-02-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Multi-Chip Wafer Level Packaging |
US8988895B2 (en) | 2011-08-23 | 2015-03-24 | Tessera, Inc. | Interconnection elements with encased interconnects |
KR101800440B1 (en) | 2011-08-31 | 2017-11-23 | 삼성전자주식회사 | Semiconductor package having plural semiconductor chips and method of forming the same |
US20130049218A1 (en) | 2011-08-31 | 2013-02-28 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation |
US9177832B2 (en) | 2011-09-16 | 2015-11-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect |
US8816404B2 (en) | 2011-09-16 | 2014-08-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant |
KR101900423B1 (en) | 2011-09-19 | 2018-09-21 | 삼성전자주식회사 | Semiconductor memory device |
TWI501254B (en) | 2011-10-03 | 2015-09-21 | Invensas Corp | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
KR101906408B1 (en) | 2011-10-04 | 2018-10-11 | 삼성전자주식회사 | Semiconductor package and method of manufacturing the same |
US20130087915A1 (en) | 2011-10-10 | 2013-04-11 | Conexant Systems, Inc. | Copper Stud Bump Wafer Level Package |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9105552B2 (en) | 2011-10-31 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
KR101297015B1 (en) | 2011-11-03 | 2013-08-14 | 주식회사 네패스 | Method of manufacturing fan-out semiconductor package using lead frame, semiconductor package thereof, and package on package thereof |
US9196588B2 (en) | 2011-11-04 | 2015-11-24 | Invensas Corporation | EMI shield |
US8916781B2 (en) | 2011-11-15 | 2014-12-23 | Invensas Corporation | Cavities containing multi-wiring structures and devices |
US8552556B1 (en) | 2011-11-22 | 2013-10-08 | Amkor Technology, Inc. | Wafer level fan out package |
US8912651B2 (en) | 2011-11-30 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) structure including stud bulbs and method |
TWI464031B (en) | 2011-12-14 | 2014-12-11 | Univ Yuan Ze | Method for suppressing kirkendall voids formation at the interface between solder and cu pad |
KR101924388B1 (en) | 2011-12-30 | 2018-12-04 | 삼성전자주식회사 | Semiconductor Package having a redistribution structure |
US8680684B2 (en) | 2012-01-09 | 2014-03-25 | Invensas Corporation | Stackable microelectronic package structures |
US9258922B2 (en) | 2012-01-18 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | PoP structures including through-assembly via modules |
US8686570B2 (en) | 2012-01-20 | 2014-04-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-dimensional integrated circuit structures and methods of forming the same |
KR20130090143A (en) | 2012-02-03 | 2013-08-13 | 삼성전자주식회사 | Package on package type semicoductor packages and method for fabricating the same |
US8742576B2 (en) | 2012-02-15 | 2014-06-03 | Oracle International Corporation | Maintaining alignment in a multi-chip module using a compressible structure |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
DE102012203293B4 (en) | 2012-03-02 | 2021-12-02 | Robert Bosch Gmbh | Semiconductor module with integrated waveguide for radar signals |
US20130234317A1 (en) | 2012-03-09 | 2013-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging Methods and Packaged Semiconductor Devices |
US9082763B2 (en) | 2012-03-15 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Joint structure for substrates and methods of forming |
US9842798B2 (en) | 2012-03-23 | 2017-12-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a PoP device with embedded vertical interconnect units |
KR20130111780A (en) | 2012-04-02 | 2013-10-11 | 삼성전자주식회사 | Silicon devices having an emi shield |
US9405064B2 (en) | 2012-04-04 | 2016-08-02 | Texas Instruments Incorporated | Microstrip line of different widths, ground planes of different distances |
US8922005B2 (en) | 2012-04-11 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for package on package devices with reversed stud bump through via interconnections |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US8978247B2 (en) | 2012-05-22 | 2015-03-17 | Invensas Corporation | TSV fabrication using a removable handling structure |
US9171790B2 (en) | 2012-05-30 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US20130323409A1 (en) | 2012-05-31 | 2013-12-05 | Skyworks Solutions, Inc. | Systems and methods for controlling electromagnetic interference for integrated circuit modules |
US8948712B2 (en) | 2012-05-31 | 2015-02-03 | Skyworks Solutions, Inc. | Via density and placement in radio frequency shielding applications |
US8981559B2 (en) | 2012-06-25 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US8742597B2 (en) | 2012-06-29 | 2014-06-03 | Intel Corporation | Package substrates with multiple dice |
US8653626B2 (en) | 2012-07-18 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures including a capacitor and methods of forming the same |
US10115671B2 (en) | 2012-08-03 | 2018-10-30 | Snaptrack, Inc. | Incorporation of passives and fine pitch through via for package on package |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8642393B1 (en) | 2012-08-08 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of forming same |
US8828860B2 (en) | 2012-08-30 | 2014-09-09 | International Business Machines Corporation | Double solder bumps on substrates for low temperature flip chip bonding |
US8963339B2 (en) | 2012-10-08 | 2015-02-24 | Qualcomm Incorporated | Stacked multi-chip integrated circuit package |
US8975726B2 (en) | 2012-10-11 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | POP structures and methods of forming the same |
KR101419597B1 (en) | 2012-11-06 | 2014-07-14 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
US9418971B2 (en) | 2012-11-08 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure including a thermal isolation material and method of forming the same |
US9412661B2 (en) | 2012-11-21 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming package-on-package structure |
US9401338B2 (en) | 2012-11-29 | 2016-07-26 | Freescale Semiconductor, Inc. | Electronic devices with embedded die interconnect structures, and methods of manufacture thereof |
KR101393102B1 (en) | 2012-12-03 | 2014-05-09 | (주)원에스티 | Supporting device for preventing earthquake and equipment to preventing earthquake using the same |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US20140175657A1 (en) | 2012-12-21 | 2014-06-26 | Mihir A. Oka | Methods to improve laser mark contrast on die backside film in embedded die packages |
US8729714B1 (en) | 2012-12-31 | 2014-05-20 | Intel Mobile Communications GmbH | Flip-chip wafer level package and methods thereof |
US9378982B2 (en) | 2013-01-31 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package |
US8940630B2 (en) | 2013-02-01 | 2015-01-27 | Invensas Corporation | Method of making wire bond vias and microelectronic package having wire bond vias |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
US8907500B2 (en) | 2013-02-04 | 2014-12-09 | Invensas Corporation | Multi-die wirebond packages with elongated windows |
US20140225248A1 (en) | 2013-02-13 | 2014-08-14 | Qualcomm Incorporated | Power distribution and thermal solution for direct stacked integrated circuits |
US9209081B2 (en) | 2013-02-21 | 2015-12-08 | Freescale Semiconductor, Inc. | Semiconductor grid array package |
US20140239479A1 (en) | 2013-02-26 | 2014-08-28 | Paul R Start | Microelectronic package including an encapsulated heat spreader |
US20140239490A1 (en) | 2013-02-26 | 2014-08-28 | Unimicron Technology Corporation | Packaging substrate and fabrication method thereof |
US9461025B2 (en) | 2013-03-12 | 2016-10-04 | Taiwan Semiconductor Manfacturing Company, Ltd. | Electric magnetic shielding structure in packages |
US9299670B2 (en) | 2013-03-14 | 2016-03-29 | Freescale Semiconductor, Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
US9419667B2 (en) | 2013-04-16 | 2016-08-16 | Skyworks Solutions, Inc. | Apparatus and methods related to conformal coating implemented with surface mount devices |
KR20140126598A (en) | 2013-04-23 | 2014-10-31 | 삼성전자주식회사 | semiconductor package and method for manufacturing of the same |
KR101771064B1 (en) | 2013-06-28 | 2017-08-24 | 인텔 아이피 코포레이션 | Microelectromechanical system (mems) on application specific integrated circuit (asic) |
US9167710B2 (en) * | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
KR102161173B1 (en) | 2013-08-29 | 2020-09-29 | 삼성전자주식회사 | Package-on-package device and method of fabricating the same |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9012263B1 (en) | 2013-10-31 | 2015-04-21 | Freescale Semiconductor, Inc. | Method for treating a bond pad of a package substrate |
US9379078B2 (en) | 2013-11-07 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D die stacking structure with fine pitches |
KR101631934B1 (en) | 2013-11-13 | 2016-06-21 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package structure and manufacturing method thereof |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9653442B2 (en) | 2014-01-17 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and methods of forming same |
US9196586B2 (en) | 2014-02-13 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package including an embedded surface mount device and method of forming the same |
US9362161B2 (en) | 2014-03-20 | 2016-06-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package |
US9318452B2 (en) | 2014-03-21 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming the same |
US9437459B2 (en) | 2014-05-01 | 2016-09-06 | Freescale Semiconductor, Inc. | Aluminum clad copper structure of an electronic component package and a method of making an electronic component package with an aluminum clad copper structure |
US20150340305A1 (en) | 2014-05-20 | 2015-11-26 | Freescale Semiconductor, Inc. | Stacked die package with redistribution layer |
US10325876B2 (en) | 2014-06-25 | 2019-06-18 | Nxp Usa, Inc. | Surface finish for wirebonding |
KR101640341B1 (en) | 2015-02-04 | 2016-07-15 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
-
2016
- 2016-10-24 US US15/332,991 patent/US10181457B2/en active Active
-
2018
- 2018-11-27 US US16/201,569 patent/US20190096861A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060216868A1 (en) * | 2005-03-25 | 2006-09-28 | Advanced Semiconductor Engineering Inc. | Package structure and fabrication thereof |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
US8193034B2 (en) * | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
US8569892B2 (en) * | 2008-10-10 | 2013-10-29 | Nec Corporation | Semiconductor device and manufacturing method thereof |
US9443797B2 (en) * | 2012-09-14 | 2016-09-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device having wire studs as vertical interconnect in FO-WLP |
Also Published As
Publication number | Publication date |
---|---|
US20170117260A1 (en) | 2017-04-27 |
US10181457B2 (en) | 2019-01-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10181457B2 (en) | Microelectronic package for wafer-level chip scale packaging with fan-out | |
US11387214B2 (en) | Multi-chip modules formed using wafer-level processing of a reconstituted wafer | |
US11532594B2 (en) | Integrated fan-out package and the methods of manufacturing | |
US10741467B2 (en) | Die-on-interposer assembly with dam structure and method of manufacturing the same | |
KR101892801B1 (en) | Integrated fan-out package and the methods of manufacturing | |
US11955442B2 (en) | Semiconductor package and method | |
US11217546B2 (en) | Embedded voltage regulator structure and method forming same | |
US11862605B2 (en) | Integrated circuit package and method of forming same | |
US11355463B2 (en) | Semiconductor package and method | |
US10008469B2 (en) | Wafer-level packaging using wire bond wires in place of a redistribution layer | |
US20190326257A1 (en) | High density fan-out packaging | |
US20230114652A1 (en) | Integrated Fan-Out Package and the Methods of Manufacturing | |
US20230109128A1 (en) | Heat Dissipation in Semiconductor Packages and Methods of Forming Same | |
US20230386919A1 (en) | Semiconductor package and method comprising formation of redistribution structure and interconnecting die | |
US11728275B2 (en) | Semiconductor package and manufacturing method thereof | |
US20230387039A1 (en) | Semicondcutor packages and methods of forming thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INVENSAS CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KATKAR, RAJESH;PRABHU, ASHOK S.;SIGNING DATES FROM 20161004 TO 20161005;REEL/FRAME:047594/0982 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., NORTH CAROLINA Free format text: SECURITY INTEREST;ASSIGNORS:ROVI SOLUTIONS CORPORATION;ROVI TECHNOLOGIES CORPORATION;ROVI GUIDES, INC.;AND OTHERS;REEL/FRAME:053468/0001 Effective date: 20200601 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |