JPS61125062A - Method and device for attaching pin - Google Patents
Method and device for attaching pinInfo
- Publication number
- JPS61125062A JPS61125062A JP24599784A JP24599784A JPS61125062A JP S61125062 A JPS61125062 A JP S61125062A JP 24599784 A JP24599784 A JP 24599784A JP 24599784 A JP24599784 A JP 24599784A JP S61125062 A JPS61125062 A JP S61125062A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- pin
- clamper
- capillary
- wire material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 9
- 239000000463 material Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005520 cutting process Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000002788 crimping Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 8
- 238000005476 soldering Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 15
- 238000005219 brazing Methods 0.000 description 5
- 229920000742 Cotton Polymers 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[技術分野]
本発明は基板へのピン取付は技術に関し、特に高iji
積化した半導体装置の外部電掻随保に通用してを効な技
術に関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology for attaching pins to a board, especially in high
The present invention relates to a technology that is widely used and effective for external electrical protection for integrated semiconductor devices.
〔背景技術]
電子機器の小型化の傾向から、半導体装置にも高集積化
が要求されているが、この要求に応えるものとして、い
わゆるピングリッドアレイ型半導体装置が知られている
。[Background Art] Due to the trend toward miniaturization of electronic devices, semiconductor devices are also required to be highly integrated, and so-called pin grid array type semiconductor devices are known as devices that meet this demand.
ピングリフ1′了レイ型ルり体装置は、セラミックまた
はプラス千ツクのパッケージの裏面にマトリックス状に
ピンを取付けたti造を存しており、外部電極が数多く
確保出来る点から、高集積化に適したパフケージのひと
つとして考えられているものである。The pin-grip 1' lay-type flat body device has a structure in which pins are attached in a matrix on the back side of a ceramic or plastic package, and it is suitable for high integration because it can secure a large number of external electrodes. It is considered as one of the suitable puff cages.
ところで、ピングリシドアレイ型半導体装置の外部との
電気的接続は基板裏面に取付けたピンによって1テわれ
るが、該ピンの基板への固定は銀等のろう材によって行
われる。そのため、ピンの固定を的−11に行うために
はピンの周囲にろう材を山盛りにする必要がある。すな
わち、基板裏面上の各ピンの周囲にはある程度のスペー
スを必要とするのである。Incidentally, the electrical connection of the pin-glycide array type semiconductor device with the outside is made by pins attached to the back surface of the substrate, and the pins are fixed to the substrate using a brazing material such as silver. Therefore, in order to fix the pin to the target 11, it is necessary to heap a heap of brazing filler metal around the pin. That is, a certain amount of space is required around each pin on the back surface of the board.
しかし、このことが今後半導体装置の超高集積化が更に
進んだ際に、ピンのピッチを小さくすることを難しくし
、電極数の不足を生じ、結果的に半導体装置の高集積化
を困難にする原因となるであろうことが本発明者によっ
て明らかにされた。However, as the ultra-high integration of semiconductor devices progresses in the future, this will make it difficult to reduce the pin pitch, resulting in a shortage of electrodes, which will eventually make it difficult to increase the integration of semiconductor devices. The inventor has clarified that this may be the cause.
゛ また、半導体装置の超高!!積化に伴って、ピン
も微小化していくことが子息されるが、ピンの微小化に
際しては、パッケージ基板に正&電な位置でピンを取付
けることのできる技術が必要不可欠となるであろうこと
も同時に本発明者によって明らかにされた。゛ Also, the super high price of semiconductor devices! ! As devices become more integrated, pins will also become smaller, and as pins become smaller, technology that allows pins to be attached to package substrates in positive and electrical positions will become indispensable. This was also revealed by the present inventor at the same time.
なお、ピングリフトアレイ型半導体装置について詳しく
述べである例としては、株式会社サイエンスフォーラム
、昭和58年11月28日発行「超LSIデバイスハン
ドブックJP22B〜P229がある。An example of a detailed description of the pin lift array type semiconductor device is ``Very LSI Device Handbook JP22B-P229'' published by Science Forum Co., Ltd. on November 28, 1980.
[発明の目的]
本発明の目的は、高集積化した半導体装置の外部電極用
ピンの取付けを高密度かつ高精度で、しかも効率良く行
うことのできる技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a technique that can efficiently attach pins for external electrodes of a highly integrated semiconductor device with high density and precision.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
[発明の概要]
本願において開示される発明のうち代表的なものの概要
を筒中に説明すれば、次の通りである。[Summary of the Invention] A summary of typical inventions disclosed in this application is as follows.
ずなわら、パッケージ基板への外部電極用ピン取付けに
おいて、ポールボンディング用ワイヤボンダと類似の機
構を用いてピンの取付けを行うことによってピンの取付
けに際して、ろう材が不要となり、これによってピン間
隔を狭めることができ、半導体装置の超高集積化を図る
ことが可能となる。Of course, when attaching pins for external electrodes to the package substrate, by attaching the pins using a mechanism similar to the wire bonder for pole bonding, no brazing material is required when attaching the pins, thereby narrowing the pin spacing. This makes it possible to achieve ultra-high integration of semiconductor devices.
また、線材の接合に際して、超音波によるピン取付け、
または熱圧着と超音波を併用したピン取付けを行うこと
によりピン及び基板の熱ストレスを防止することができ
る。In addition, when joining wire rods, pin attachment using ultrasonic waves,
Alternatively, thermal stress on the pins and the substrate can be prevented by attaching the pins using both thermocompression bonding and ultrasonic waves.
[実施例IJ
第1図は本発明の一実施例であるピン取付は装置を示す
概略一部所面図である。[Embodiment IJ Fig. 1 is a schematic partial view showing a pin attachment device according to an embodiment of the present invention.
第2し1は本発明の一実施例である外部電極用ピン取付
は方法を順次段階的に説明した断面図である。2nd 1 is a sectional view illustrating a method of attaching an external electrode pin according to an embodiment of the present invention in a step-by-step manner.
ピン取付は装置1は第11剥に示すように金(AU)か
らなるピ/材料としての綿月2が巻装されたスプール(
ソイヤイ1蝙給部) 3を6i+7えCおり、スプール
3から繰り出された綿材2は第一クランパ4、カッター
5および第二クランパ6を経てキャピラリ7に押通され
ている。このキャピラリ7は超音波ホーンを有するボン
ディングアーム8を介してボンディングヘッド13に搭
載されており、このボンディングヘッドはXYテーブル
14によりXY方向に移動できるようになっている。こ
のアーム8およびヘッドを介してキャピラリ7は接合台
9上面に対し各上下方向および左右方向に相対的に移動
するように構成されている。接合台9の上面には半導体
装置のパッケージ基板10がピン取付は面を上にして@
置されている。また、接合台9上方には電気トーチ11
がキャピラリ7の先端に対して放電時に所定の間隔を維
持するように設けられている0図示しないが、上記スプ
ール3、第一クランパ4、カッター5、第二クランパ6
、電気トーチ11はボンディングヘッド13に各々連結
されており、駆動されている。To attach the pin, the device 1 uses a pin made of gold (AU) as shown in the 11th strip/a spool wrapped with cotton material 2 (
The cotton material 2 unwound from the spool 3 is forced through a capillary 7 through a first clamper 4, a cutter 5, and a second clamper 6. This capillary 7 is mounted on a bonding head 13 via a bonding arm 8 having an ultrasonic horn, and this bonding head can be moved in the XY directions by an XY table 14. The capillary 7 is configured to move relative to the upper surface of the joining table 9 in the vertical and horizontal directions via the arm 8 and the head. The package substrate 10 of the semiconductor device is mounted on the top surface of the bonding table 9 with the pin attached with the surface facing up.
It is placed. Additionally, an electric torch 11 is placed above the joining table 9.
Although not shown, the spool 3, the first clamper 4, the cutter 5, and the second clamper 6 are provided so as to maintain a predetermined distance from the tip of the capillary 7 during discharge.
, electric torches 11 are each connected to a bonding head 13 and driven.
次に本実施例によるピン取付は方法を順次説明する。Next, the pin attachment method according to this embodiment will be sequentially explained.
まず、第2図(81〜+blに示すように第一・クラン
ノサ4が閉塞した状態で線材2を保持しつつ下降して譲
綿材2をキャピラリ7に挿通させる。First, as shown in FIG. 2 (81 to +bl), the first crannosa 4 is lowered while holding the wire 2 in a closed state, and the loose cotton material 2 is inserted into the capillary 7.
次に、第2図1cIに示すように第二クランノぐ6が閉
塞し線材2を保持するとともに第一クランツク4は開放
し上昇する。Next, as shown in FIG. 2, 1cI, the second crank nozzle 6 closes and holds the wire 2, and the first crank 4 opens and rises.
次に、第2図1cIに示すように綿材2は第二クランパ
6の上方位置でカッター5により切断される。Next, as shown in FIG. 2 1cI, the cotton material 2 is cut by the cutter 5 at a position above the second clamper 6.
一方キャピラリ7の下方の線材2の先端部分は電気トー
チ11からの放電により線材2が溶融してボールI2が
形成される。On the other hand, at the tip of the wire 2 below the capillary 7, the wire 2 is melted by discharge from the electric torch 11, and a ball I2 is formed.
その後、第二クランパ6は閉塞したままの状態でキャピ
ラリ7と一体に線材2を保持しながらパフケージ5仮t
o上の所定位置まで下降する。そして、キャピラリ7の
先端部でボールI2の部分を加圧し、かつ超音波振動を
加えながらピンとしての線材2をパッケージ基板lO上
の所定位置にt【合する(第2図1cI) 。Thereafter, the second clamper 6 holds the wire rod 2 integrally with the capillary 7 in the closed state, and the puff cage 5 temporarily ts.
It descends to a predetermined position above o. Then, while pressing the ball I2 at the tip of the capillary 7 and applying ultrasonic vibration, the wire 2 serving as a pin is fitted into a predetermined position on the package substrate IO (FIG. 2, 1cI).
その後、第二クランパ6は開放して、キャピラ+77と
ともに上昇して(第2図1cI)−半導体装置パッケー
ジW&l Oへの外部ttti用ピン取付は作業の一工
程が完了する。Thereafter, the second clamper 6 is opened and raised together with the capillary +77 (FIG. 2, 1cI) - one step of the process of attaching the external ttti pin to the semiconductor device package W&l O is completed.
このように、本実施例によれば、ろう材を用いないため
各ピン間隔を狭めることができ、半導体装置の高集積化
に対応して高密度でピンをパッケージ基板に取付けるこ
とが可能となる。In this way, according to this embodiment, since no brazing material is used, the spacing between each pin can be narrowed, making it possible to attach pins to the package substrate at a high density in response to higher integration of semiconductor devices. .
また、ワイヤボンディングに用いるボールボンディング
方式のワイヤボンダと類似の411IFRを利用して、
キャピラリ7によってピンの接合を行うことにより、ピ
ンの取付は位置の決定およびピンの切断等においてポー
ルボンディング方式のワイヤボンダと同一の精度の高い
作業が可能となる。In addition, using the 411IFR, which is similar to the ball bonding type wire bonder used for wire bonding,
By bonding the pins using the capillary 7, it is possible to attach the pins with the same high precision as a pole bonding type wire bonder in determining the position and cutting the pins.
[効果]
(1)、ボールボンディング用ワイヤボンダと類似のn
横を用いてピン材料を所定の長さで切断して、ピン材料
先端部を基板上のピン取付部に圧着することによって、
ろう材を用いずにピン取付けが可能となり、パッケージ
基板に高密度でピンを取付けることができる。[Effect] (1), n similar to wire bonder for ball bonding
By cutting the pin material to a predetermined length using the side, and crimping the tip of the pin material to the pin mounting part on the board,
Pin attachment is now possible without using brazing filler metal, and pins can be attached to the package substrate at high density.
+2+、 iil記fl+より、半導体装置の高!Jl
積化に対応して必要な外部電極数を罐保することが可能
となり、半導体装置の高集積化をさらに促進することが
できる。+2+, from iii fl+, the high price of semiconductor devices! Jl
It becomes possible to keep the number of external electrodes required in response to the increase in integration, and it is possible to further promote higher integration of semiconductor devices.
(3)、ポールボンディング用ワイヤボンダと類似の!
!!+11を用いることにより、漱細なピンであっても
ポールボンディング用ワイヤボンダと同一の高精度で、
かつ効率のよいピン取付けを行うことができる。(3) Similar to wire bonder for pole bonding!
! ! By using +11, even thin pins can be made with the same high precision as a wire bonder for pole bonding.
In addition, efficient pin attachment can be performed.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明はl1il記実施例に限定さ
れるものではなく、その要旨を逸脱しない範囲で種々変
更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples described above, and it should be noted that various changes can be made without departing from the gist of the invention. Not even.
たとえば、実施例ではポールボンディング用ワイヤボン
ダとIff(以のn構として、キャピラリを用いたもの
について説明したが、これに限るものではなく、超音波
ワイヤボンディング用ワイヤ接続工具であるウェッジと
類似のウェッジによって超音波振動でピンの固定を行う
ものであってもよい。For example, in the embodiment, a wire bonder for pole bonding and an Iff (hereinafter n structure) using a capillary were described, but the invention is not limited to this, and a wedge similar to a wedge that is a wire connection tool for ultrasonic wire bonding was described. The pin may be fixed by ultrasonic vibration.
この場合、はぼ垂直方向にワイヤボンディングが可能な
ウェッジであればなおよい。In this case, it is preferable to use a wedge that allows wire bonding in a substantially vertical direction.
また、ピンとなる線材としては、実施例で説明した金に
限るものでなく、銅、アルミニウムなどであってもよい
。Further, the wire rod serving as the pin is not limited to gold as explained in the embodiment, but may be made of copper, aluminum, or the like.
第1図は本発明の一実施例であるピン取付は装置を示す
1a略一部所面図、
第2図181〜(【)は本発明の一実施例である外部電
極用ピン取付は方法を順次段階的に説明した断面図であ
る。
1・・・外部電極用ピン取付装置、2・・・線材、3・
・・スプール、4・・・第一クランパ、5・・・カッタ
ー、6・・・iニクランパ、7・・・キャピラリ、8・
・・ボンディングアーム、9・・・接合台、1G・・・
パッケージ基板、11・・・電気トーチ、12・・・ボ
ール、13・・・ボンディングヘッド、14・・・XY
テープ(とl ) (b)
((ン2図
(t)(e) (子)Fig. 1 is a schematic partial partial view of 1a showing a device for pin attachment, which is an embodiment of the present invention, and Fig. 2 (181 to [)) is a method for attaching external electrode pins, which is an embodiment of the present invention. FIG. 1... External electrode pin attachment device, 2... Wire rod, 3...
...Spool, 4...First clamper, 5...Cutter, 6...I clamper, 7...Capillary, 8...
...Bonding arm, 9...Joining table, 1G...
Package board, 11... Electric torch, 12... Ball, 13... Bonding head, 14... XY
tape (and l) (b)
((n) Figure 2 (t) (e) (child)
Claims (1)
イヤ接続工具に挿通されている長尺のピン線材を所定の
長さに切断する工程と、切断されたピン線材の先端部を
ワイヤ接続工具を用いて基板上のピン取付け部に固定す
る工程とからなることを特徴とするピン取付け方法。 2、ピン線材の先端部を溶融させボール形成を行った後
、加圧しながら超音波振動を加えることによって圧着を
行うことを特徴とする特許請求の範囲第1項記載のピン
取付け方法。 3、ワイヤ接続工具と、ワイヤ接続工具を先端部に取付
けているボンディングアームと、ボンディングアームを
上下動作させる駆動体と、ボンディングアームに連結さ
れてなり、ボンディングアームを通してワイヤ接続工具
に超音波振動を印加できる超音波振動源と、ワイヤ接続
工具に挿通可能なピン線材を適時挟持しうる2組のクラ
ンパと、前記2組のクランパの間にピン線材の切断部を
配置しているカッターと、ワイヤ接続工具に長尺のピン
線材を供給するワイヤ供給部と、前記ボンディングアー
ム、クランパ、カッター、ワイヤ供給部をXY方向に移
動可能なXYテーブルとを備えていることを特徴とする
ピン取付け装置。 4、ピン線材としては、金(Au)を主成分とするワイ
ヤを用いることを特徴とする特許請求の範囲第3項記載
のピン取付け装置。[Claims] 1. A method for attaching external electrode pins to a substrate, which includes a step of cutting a long pin wire inserted through a wire connection tool into a predetermined length, and a step of cutting the cut pin into a predetermined length. A pin attachment method comprising the step of fixing the tip of a wire to a pin attachment portion on a board using a wire connection tool. 2. The pin attachment method according to claim 1, wherein after melting the tip of the pin wire to form a ball, crimping is performed by applying ultrasonic vibration while applying pressure. 3. A wire connecting tool, a bonding arm with the wire connecting tool attached to the tip, a drive body that moves the bonding arm up and down, and a drive body that is connected to the bonding arm and applies ultrasonic vibration to the wire connecting tool through the bonding arm. An ultrasonic vibration source that can be applied, two sets of clampers that can timely clamp a pin wire that can be inserted into a wire connection tool, a cutter that has a cutting part for the pin wire between the two clampers, and a wire. A pin attaching device comprising: a wire supply section that supplies a long pin wire to a connecting tool; and an XY table capable of moving the bonding arm, clamper, cutter, and wire supply section in XY directions. 4. The pin attachment device according to claim 3, wherein the pin wire material is a wire whose main component is gold (Au).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24599784A JPS61125062A (en) | 1984-11-22 | 1984-11-22 | Method and device for attaching pin |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24599784A JPS61125062A (en) | 1984-11-22 | 1984-11-22 | Method and device for attaching pin |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61125062A true JPS61125062A (en) | 1986-06-12 |
Family
ID=17141928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24599784A Pending JPS61125062A (en) | 1984-11-22 | 1984-11-22 | Method and device for attaching pin |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61125062A (en) |
Cited By (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8372741B1 (en) * | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US8907466B2 (en) | 2010-07-19 | 2014-12-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US8927337B2 (en) | 2004-11-03 | 2015-01-06 | Tessera, Inc. | Stacked packaging improvements |
US8957527B2 (en) | 2010-11-15 | 2015-02-17 | Tessera, Inc. | Microelectronic package with terminals on dielectric mass |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9093435B2 (en) | 2011-05-03 | 2015-07-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US9218988B2 (en) | 2005-12-23 | 2015-12-22 | Tessera, Inc. | Microelectronic packages and methods therefor |
US9224717B2 (en) | 2011-05-03 | 2015-12-29 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9324681B2 (en) | 2010-12-13 | 2016-04-26 | Tessera, Inc. | Pin attachment |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US9530749B2 (en) | 2015-04-28 | 2016-12-27 | Invensas Corporation | Coupling of side surface contacts to a circuit platform |
US9553076B2 (en) | 2010-07-19 | 2017-01-24 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9601454B2 (en) | 2013-02-01 | 2017-03-21 | Invensas Corporation | Method of forming a component having wire bonds and a stiffening layer |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US9728527B2 (en) | 2013-11-22 | 2017-08-08 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US9812402B2 (en) | 2015-10-12 | 2017-11-07 | Invensas Corporation | Wire bond wires for interference shielding |
US9842745B2 (en) | 2012-02-17 | 2017-12-12 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9852969B2 (en) | 2013-11-22 | 2017-12-26 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US10008477B2 (en) | 2013-09-16 | 2018-06-26 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US10008469B2 (en) | 2015-04-30 | 2018-06-26 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US10026717B2 (en) | 2013-11-22 | 2018-07-17 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US10460958B2 (en) | 2013-08-07 | 2019-10-29 | Invensas Corporation | Method of manufacturing embedded packaging with preformed vias |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
-
1984
- 1984-11-22 JP JP24599784A patent/JPS61125062A/en active Pending
Cited By (93)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8927337B2 (en) | 2004-11-03 | 2015-01-06 | Tessera, Inc. | Stacked packaging improvements |
US9570416B2 (en) | 2004-11-03 | 2017-02-14 | Tessera, Inc. | Stacked packaging improvements |
US9153562B2 (en) | 2004-11-03 | 2015-10-06 | Tessera, Inc. | Stacked packaging improvements |
US9218988B2 (en) | 2005-12-23 | 2015-12-22 | Tessera, Inc. | Microelectronic packages and methods therefor |
US9984901B2 (en) | 2005-12-23 | 2018-05-29 | Tessera, Inc. | Method for making a microelectronic assembly having conductive elements |
US9570382B2 (en) | 2010-07-19 | 2017-02-14 | Tessera, Inc. | Stackable molded microelectronic packages |
US8907466B2 (en) | 2010-07-19 | 2014-12-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US9553076B2 (en) | 2010-07-19 | 2017-01-24 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US10128216B2 (en) | 2010-07-19 | 2018-11-13 | Tessera, Inc. | Stackable molded microelectronic packages |
US9123664B2 (en) | 2010-07-19 | 2015-09-01 | Tessera, Inc. | Stackable molded microelectronic packages |
US8957527B2 (en) | 2010-11-15 | 2015-02-17 | Tessera, Inc. | Microelectronic package with terminals on dielectric mass |
US9324681B2 (en) | 2010-12-13 | 2016-04-26 | Tessera, Inc. | Pin attachment |
US10593643B2 (en) | 2011-05-03 | 2020-03-17 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US11424211B2 (en) | 2011-05-03 | 2022-08-23 | Tessera Llc | Package-on-package assembly with wire bonds to encapsulation surface |
US10062661B2 (en) | 2011-05-03 | 2018-08-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9691731B2 (en) | 2011-05-03 | 2017-06-27 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9093435B2 (en) | 2011-05-03 | 2015-07-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9224717B2 (en) | 2011-05-03 | 2015-12-29 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9041227B2 (en) | 2011-10-17 | 2015-05-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9761558B2 (en) | 2011-10-17 | 2017-09-12 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9105483B2 (en) | 2011-10-17 | 2015-08-11 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9252122B2 (en) | 2011-10-17 | 2016-02-02 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US10756049B2 (en) | 2011-10-17 | 2020-08-25 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US11189595B2 (en) | 2011-10-17 | 2021-11-30 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US11735563B2 (en) | 2011-10-17 | 2023-08-22 | Invensas Llc | Package-on-package assembly with wire bond vias |
US9842745B2 (en) | 2012-02-17 | 2017-12-12 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8372741B1 (en) * | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9691679B2 (en) | 2012-02-24 | 2017-06-27 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US10510659B2 (en) | 2012-05-22 | 2019-12-17 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US10170412B2 (en) | 2012-05-22 | 2019-01-01 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9953914B2 (en) | 2012-05-22 | 2018-04-24 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9917073B2 (en) | 2012-07-31 | 2018-03-13 | Invensas Corporation | Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package |
US10297582B2 (en) | 2012-08-03 | 2019-05-21 | Invensas Corporation | BVA interposer |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US9615456B2 (en) | 2012-12-20 | 2017-04-04 | Invensas Corporation | Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9095074B2 (en) | 2012-12-20 | 2015-07-28 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9601454B2 (en) | 2013-02-01 | 2017-03-21 | Invensas Corporation | Method of forming a component having wire bonds and a stiffening layer |
US9633979B2 (en) | 2013-07-15 | 2017-04-25 | Invensas Corporation | Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US10460958B2 (en) | 2013-08-07 | 2019-10-29 | Invensas Corporation | Method of manufacturing embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US10008477B2 (en) | 2013-09-16 | 2018-06-26 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9893033B2 (en) | 2013-11-12 | 2018-02-13 | Invensas Corporation | Off substrate kinking of bond wire |
US10290613B2 (en) | 2013-11-22 | 2019-05-14 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9852969B2 (en) | 2013-11-22 | 2017-12-26 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
USRE49987E1 (en) | 2013-11-22 | 2024-05-28 | Invensas Llc | Multiple plated via arrays of different wire heights on a same substrate |
US10629567B2 (en) | 2013-11-22 | 2020-04-21 | Invensas Corporation | Multiple plated via arrays of different wire heights on same substrate |
US10026717B2 (en) | 2013-11-22 | 2018-07-17 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9728527B2 (en) | 2013-11-22 | 2017-08-08 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9837330B2 (en) | 2014-01-17 | 2017-12-05 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US11404338B2 (en) | 2014-01-17 | 2022-08-02 | Invensas Corporation | Fine pitch bva using reconstituted wafer with area array accessible for testing |
US11990382B2 (en) | 2014-01-17 | 2024-05-21 | Adeia Semiconductor Technologies Llc | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US10529636B2 (en) | 2014-01-17 | 2020-01-07 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9356006B2 (en) | 2014-03-31 | 2016-05-31 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US9812433B2 (en) | 2014-03-31 | 2017-11-07 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US10032647B2 (en) | 2014-05-29 | 2018-07-24 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US10475726B2 (en) | 2014-05-29 | 2019-11-12 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9947641B2 (en) | 2014-05-30 | 2018-04-17 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US10806036B2 (en) | 2015-03-05 | 2020-10-13 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9530749B2 (en) | 2015-04-28 | 2016-12-27 | Invensas Corporation | Coupling of side surface contacts to a circuit platform |
US10008469B2 (en) | 2015-04-30 | 2018-06-26 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US10115678B2 (en) | 2015-10-12 | 2018-10-30 | Invensas Corporation | Wire bond wires for interference shielding |
US10559537B2 (en) | 2015-10-12 | 2020-02-11 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US9812402B2 (en) | 2015-10-12 | 2017-11-07 | Invensas Corporation | Wire bond wires for interference shielding |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US10043779B2 (en) | 2015-11-17 | 2018-08-07 | Invensas Corporation | Packaged microelectronic device for a package-on-package device |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US10325877B2 (en) | 2015-12-30 | 2019-06-18 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US10658302B2 (en) | 2016-07-29 | 2020-05-19 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS61125062A (en) | Method and device for attaching pin | |
US8183607B2 (en) | Semiconductor device | |
KR100470897B1 (en) | Method for manufacturing dual die package | |
US7863107B2 (en) | Semiconductor device and manufacturing method of the same | |
JPH11121543A (en) | Chip scale package | |
JPH10335368A (en) | Wire-bonding structure and semiconductor device | |
US6331738B1 (en) | Semiconductor device having a BGA structure | |
JPS60134444A (en) | Formation for bump electrode | |
JP3276899B2 (en) | Semiconductor device | |
JP5026112B2 (en) | A method for manufacturing a semiconductor device. | |
JP5026113B2 (en) | A method for manufacturing a semiconductor device. | |
JP3293757B2 (en) | Method of manufacturing lead frame assembly for manufacturing semiconductor device | |
JP2846095B2 (en) | Method for manufacturing semiconductor device | |
JP3617574B2 (en) | Multiple-multi-row lead frame and method of manufacturing semiconductor device using the same | |
JPH0428241A (en) | Manufacture of semiconductor device | |
JP3257266B2 (en) | Semiconductor device | |
JPH01209733A (en) | Semiconductor device | |
JPS61117846A (en) | Manufacture of bonding metallic projection | |
JP3445687B2 (en) | Mounting method of semiconductor chip | |
JPH088285A (en) | Semiconductor device | |
JPH01175757A (en) | Manufacture of semiconductor device | |
JPH01175758A (en) | Semiconductor device | |
JPS58148432A (en) | Wire bonding | |
JPH01227457A (en) | Formation of bump electrode | |
JPH03142940A (en) | Wire bonding method |