JP2846095B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2846095B2
JP2846095B2 JP2270029A JP27002990A JP2846095B2 JP 2846095 B2 JP2846095 B2 JP 2846095B2 JP 2270029 A JP2270029 A JP 2270029A JP 27002990 A JP27002990 A JP 27002990A JP 2846095 B2 JP2846095 B2 JP 2846095B2
Authority
JP
Japan
Prior art keywords
pad
semiconductor chip
linear conductor
pads
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2270029A
Other languages
Japanese (ja)
Other versions
JPH04145633A (en
Inventor
正樹 長澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2270029A priority Critical patent/JP2846095B2/en
Publication of JPH04145633A publication Critical patent/JPH04145633A/en
Application granted granted Critical
Publication of JP2846095B2 publication Critical patent/JP2846095B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
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Description

【発明の詳細な説明】 〔概 要〕 ワイヤポンディング工程を含む半導体装置の製造方法
に関し、 半導体チップのパッド露出用窓の位置を変えずに量産
性を高めることを目的とし、 保護膜に設けた複数の窓によって複数のパッドの全て
を個々に露出させた半導体チップを用い、前記パッドの
うち使用されないパッドの上に線状導体の一端をボンデ
ィングした後に、該線状導体を伸ばさずに切断し、使用
されない前記パッドを前記線状導体で覆うことによって
構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a semiconductor device including a wire bonding step, which is provided on a protective film for the purpose of enhancing mass productivity without changing the position of a window for exposing a pad of a semiconductor chip. After using a semiconductor chip in which all of a plurality of pads are individually exposed by a plurality of windows and bonding one end of a linear conductor to an unused pad among the pads, the linear conductor is cut without extending. The unused pad is covered with the linear conductor.

〔産業上の利用分野〕[Industrial applications]

本発明は、半導体装置の製造方法に関し、より詳しく
は、ワイヤボンディング工程を含む半導体装置の製造方
法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a wire bonding step.

〔従来の技術〕[Conventional technology]

半導体集積回路を形成した半導体チップをパッケージ
ングする場合には、例えば、第４図に示すような方法が
ある。即ち、第５図に示すような半導体チップａをリー
ドフレームｂ中央のダイパッドｃに取付けた後に、半導
体チップａの表面のパッドｄとリードｅとを金のワイヤ
によって接続し、ついで、半導体チップａとリードｅの
一部を樹脂材ｆにより封止し、この後に、リードフレー
ムｂからリードｅを切り離すような工程を経るようにし
ている。For packaging a semiconductor chip on which a semiconductor integrated circuit is formed, for example, there is a method as shown in FIG. That is, after the semiconductor chip a as shown in FIG. 5 is attached to the die pad c at the center of the lead frame b, the pads d on the surface of the semiconductor chip a and the leads e are connected by gold wires. And a part of the lead e is sealed with a resin material f, and thereafter, a step of separating the lead e from the lead frame b is performed.

ところで、上記したパッドｄは、半導体回路の信号電
極や電源電極となるものであるが、半導体装置を取付け
ようとする外部回路の構成の相違によってパッドｄの形
成位置を半導体チップａの側部から端部に変更したい場
合もあり、半導体チップａ内の一つの電極配線の端部に
複数のパッドｄを接続するとともに、これに対応して複
数種類のパッケージを用意するようにしている。By the way, the pad d serves as a signal electrode and a power supply electrode of a semiconductor circuit. However, due to a difference in the configuration of an external circuit on which a semiconductor device is to be mounted, the pad d is formed from the side of the semiconductor chip a. In some cases, it is desired to change to an end. A plurality of pads d are connected to the end of one electrode wiring in the semiconductor chip a, and a plurality of types of packages are prepared correspondingly.

この場合、リードｅに接続されないパッドｄを半導体
チップａ表面の保護膜ｇから露出したままにしておく
と、アルミニウム製のパッドｄがその周囲のガスと反応
して腐食してしまい、これが内部にまで広がり、ついに
は内部の配線を断線させたり導通不良を生じさせること
になる。In this case, if the pad d that is not connected to the lead e is left exposed from the protective film g on the surface of the semiconductor chip a, the pad d made of aluminum reacts with the surrounding gas and corrodes, and this is formed inside. This eventually leads to disconnection of internal wiring and poor conduction.

このため、使用しないパッドｄを保護膜ｇによって覆
うとともに、リードｅに接続されるパッドｄだけを保護
膜ｇの開口部ｈから露出するようにしている。Therefore, the unused pad d is covered with the protective film g, and only the pad d connected to the lead e is exposed from the opening h of the protective film g.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかし、これによれば、第５図（ａ），（ｂ）に示す
ように、パッドｄの使用位置を変更する毎に開口部ｈの
位置を変えなければならず、半導体チップａの汎用性が
低くなり、量産化の妨げになるといった問題がある。However, according to this, as shown in FIGS. 5 (a) and 5 (b), the position of the opening h must be changed each time the use position of the pad d is changed, and the versatility of the semiconductor chip a is increased. , Which hinders mass production.

本発明はこのような問題に鑑みてなされたものであっ
て、保護膜に形成するパッド露出用の窓の配置を変えず
に量産性を高めることができる半導体装置の製造方法を
提供することを目的とする。The present invention has been made in view of such a problem, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving mass productivity without changing the arrangement of windows for exposing pads formed on a protective film. Aim.

〔課題を解決するための手段〕[Means for solving the problem]

上記した課題は、第１〜３図に例示するように、保護
膜４に設けた複数の窓５によって複数のパッド３の全て
を個々に露出させた半導体チップ１を用い、前記パッド
１のうち使用されないパッド３の上に線状導体12の一端
をボンディングした後に、該線状導体12を伸ばさずに切
断し、使用されない前記パッド１を前記線状導体12の一
部によって覆うことを特徴とする半導体装置の製造方
法、 または、保護膜４に設けた複数の窓５によって複数の
パッド３の全てを個々に露出させた半導体チップ１を、
チップ載置台７の上に取付ける工程と、前記チップ載置
台７周囲のリード８に接続されない前記パッド３の上に
線状導体12の一端を圧着した後に、該線状導体12を引き
伸ばさずに切断し、使用されない前記パッド３を前記線
状導体12の一部によって覆う工程と、前記リード８に接
続される前記パッド３の上に線状導体12の一端を接続し
た後に、該線状導体12を引き伸ばして前記リード８に圧
着し、使用される前記パッド３と前記リード８とを導通
させる工程とを備えたことを特徴とする半導体装置の製
造方法によって達成する。The above problem is solved by using a semiconductor chip 1 in which all of a plurality of pads 3 are individually exposed by a plurality of windows 5 provided in a protective film 4 as illustrated in FIGS. After bonding one end of the linear conductor 12 onto the unused pad 3, the linear conductor 12 is cut without being stretched, and the unused pad 1 is covered with a part of the linear conductor 12. The semiconductor chip 1 in which all of the plurality of pads 3 are individually exposed by the plurality of windows 5 provided in the protective film 4.
A step of attaching the linear conductor 12 on the chip mounting table 7 and crimping one end of the linear conductor 12 onto the pad 3 which is not connected to the lead 8 around the chip mounting table 7 without stretching the linear conductor 12 Covering the unused pad 3 with a part of the linear conductor 12, and connecting one end of the linear conductor 12 on the pad 3 connected to the lead 8. And pressing the lead 3 on the lead 8 to conduct the pad 3 and the lead 8 to be used.

〔作 用〕(Operation)

本発明によれば、半導体チップ１の表面に形成される
パッド３の全てを保護膜４から露出させるとともに、リ
ード８に接続されないパッド３を線状体状12（金線）に
よって覆うようにしている。According to the present invention, all of the pads 3 formed on the surface of the semiconductor chip 1 are exposed from the protective film 4 and the pads 3 not connected to the leads 8 are covered with the linear body 12 (gold wire). I have.

このため、リード８に接続されないパッド３は、ワイ
ヤボンディングの際に線状導体３の一部によって覆われ
ることになり、そのパッド３は腐食性物質との接触が断
たれることになり、腐食することがなくなる。For this reason, the pad 3 not connected to the lead 8 is covered by a part of the linear conductor 3 at the time of wire bonding, and the pad 3 loses contact with the corrosive substance, thereby causing corrosion. Will not be done.

しかも、リード８に繋げるパッド３を別なものに変更
したとしても、保護膜４に形成されるパッド露出用の窓
５を変更する必要がなくなり、半導体チップ１の汎用性
が高くなり、量産性を向上することが可能になる。In addition, even if the pad 3 connected to the lead 8 is changed to another one, it is not necessary to change the window 5 for exposing the pad formed on the protective film 4, so that the versatility of the semiconductor chip 1 is increased, and mass productivity is improved. Can be improved.

〔実施例〕〔Example〕

そこで、以下に本発明の詳細を図面に基づいて説明す
る。Therefore, the details of the present invention will be described below with reference to the drawings.

第１図は、本発明に使用される半導体チップの一例を
示す平面図及び部分拡大斜視図であって、図中符号１
は、内部に半導体集積回路を形成した半導体チップで、
この半導体チップ１の上面の活性領域２の周囲には入出
力信号電極用や電源電極となるアルミニウム製のパッド
３が複数形成されており、半導体チップ１上面を覆う保
護膜４に設けた窓５によって全てのパッド３が露出する
ように構成されている。FIG. 1 is a plan view and a partially enlarged perspective view showing an example of a semiconductor chip used in the present invention.
Is a semiconductor chip with a semiconductor integrated circuit formed inside,
Around the active region 2 on the upper surface of the semiconductor chip 1, a plurality of aluminum pads 3 for input / output signal electrodes and power supply electrodes are formed, and a window 5 provided on a protective film 4 covering the upper surface of the semiconductor chip 1 is formed. , All the pads 3 are exposed.

第２図は、本発明の方法により半導体チップを組込ん
だリードフレームを示す平面図であって、図中符号６
は、鉄ニッケル合金、銅合金等よりなるリードフレーム
で、その内部には、半導体チップを載置するダイパッド
７とこのダイパッド７を囲む複数のリード８が形成され
ており、ダイパッド７の上に半導体チップ１をボンディ
ングした状態で、半導体チップ１のパッド３の一部リー
ド８とを金線９によってワイヤボンディングするととも
に、使用しないパッド３をその金線９によって覆うよう
に構成されている。FIG. 2 is a plan view showing a lead frame incorporating a semiconductor chip according to the method of the present invention.
Is a lead frame made of an iron-nickel alloy, a copper alloy or the like, in which a die pad 7 for mounting a semiconductor chip and a plurality of leads 8 surrounding the die pad 7 are formed. In a state where the chip 1 is bonded, a part of the lead 3 of the pad 3 of the semiconductor chip 1 is wire-bonded with a gold wire 9, and the unused pad 3 is covered with the gold wire 9.

第３図は、半導体チップ１のパッド３とリード８にワ
イヤボンディングを行う工程を示す拡大断面図である。FIG. 3 is an enlarged sectional view showing a step of performing wire bonding to the pads 3 and the leads 8 of the semiconductor chip 1.

まず、半導体チップ１を300℃程度に加熱した状態
で、キャピラリ10の金線導入孔11から下方に金線12を出
し、この金線12の先端の球状に形成する（第３図
（ａ））。First, with the semiconductor chip 1 heated to about 300 ° C., a gold wire 12 is drawn out from the gold wire introduction hole 11 of the capillary 10 and formed into a spherical shape at the tip of the gold wire 12 (FIG. 3A). ).

そして、使用しないパッド３の上の位置にキャピラリ
10を移動して金線12の球状先端をパッド３に押しつけた
後に、金線12とパッド３とを熱圧着する（第３図
（ｂ））。Then, place the capillary at the position above the unused pad 3.
After moving 10 and pressing the spherical tip of the gold wire 12 against the pad 3, the gold wire 12 and the pad 3 are thermocompression-bonded (FIG. 3 (b)).

次に、キャピラリ10を上方に僅かに移動してから（第
３図（ｃ））、さらにそれを横方向に移動されて金線12
を引きちぎり（第３図（ｄ））、金線12の一部をパッド
３の上に残し、これによってパルス３を覆う。Next, after slightly moving the capillary 10 upward (FIG. 3 (c)), the capillary 10 is further moved in the lateral direction and the gold wire 12 is moved.
(FIG. 3 (d)), leaving a portion of the gold wire 12 on the pad 3, thereby covering the pulse 3.

一方、リード８に接続されるパッド３においては、第
３図（ｅ）に示すように、金線12をパッド３に熱圧着し
た後に、キャピラリ10を上方に引き上げると、金線12は
キャピラリ10内部の金線導入孔11を通って伸びてくるの
で（第３図（ｆ））、これにつづいてリード８の上方に
キャピラリ10を移動してその先端をリード８に熱圧着す
ることが可能になる。On the other hand, in the pad 3 connected to the lead 8, as shown in FIG. 3 (e), after the gold wire 12 is thermocompression-bonded to the pad 3, the capillary 10 is pulled up, and the gold wire 12 Since it extends through the internal gold wire introduction hole 11 (FIG. 3 (f)), the capillary 10 can be subsequently moved above the lead 8 and its tip can be thermocompression-bonded to the lead 8. become.

（第３図（ｇ））。(FIG. 3 (g)).

そして、金線12とリード８とを接続したあとに、キャ
ピラリ10を持ち上げてその先端にある金線12を水素等の
炎で焼き切ることになる。Then, after connecting the gold wire 12 and the lead 8, the capillary 10 is lifted, and the gold wire 12 at the end thereof is burned off with a flame such as hydrogen.

このように、半導体チップ１表面に形成したパッド３
のうちリード８に接続しようとするものは、金線12を介
してリード８に接続され、また、使用しないパッド３に
おいては、その上に熱圧着した金線12を殆ど伸ばさずに
そのまま切断するようにしているために、ワイヤボンデ
ィングの工程において全てのパッド３が金によって覆わ
れることになり、外部から供給される腐食性物質と反応
することがなくなる。Thus, the pads 3 formed on the surface of the semiconductor chip 1
Of the pads 3 to be connected to the leads 8 are connected to the leads 8 via the gold wires 12, and in the pads 3 not used, the gold wires 12 thermocompression-bonded thereon are cut off almost without being stretched. As a result, all the pads 3 are covered with gold in the wire bonding process, and do not react with corrosive substances supplied from the outside.

例えば、第１図（ｂ）に示すように、２つのパッド3
a、3bが繋がれて形成されている半導体チップ１におい
て、先端にある一方のパッド3aにリード８を圧着する場
合でも、活性領域２に近い他方のパッド3bは金によって
覆われるために腐食することはなく、一方のパッド3aか
ら活性領域２に到る配線経路が他方のパッド3bの腐食に
よって断線することはなくなる。For example, as shown in FIG.
In the semiconductor chip 1 formed by connecting the a and 3b, even when the lead 8 is pressed to one of the pads 3a at the tip, the other pad 3b near the active region 2 is corroded because it is covered with gold. The wiring path from one pad 3a to the active region 2 does not break due to corrosion of the other pad 3b.

以上のようなワイヤボンディングを終えた後に、リー
ド８の内端と半導体チップ１を樹脂材によって封止し、
ついでリード８をリードフレーム６から切り離すことに
なる。After the above wire bonding is completed, the inner ends of the leads 8 and the semiconductor chip 1 are sealed with a resin material.
Next, the lead 8 is separated from the lead frame 6.

なお、上記した実施例では、金線12の先端を球状にす
るボンディング法、即ち、ネイルヘッド法を用いたが、
ステッチボンディング法、ウェッジボンディング法、超
音波ボンディング法等によることもできる。In the above-described embodiment, the bonding method for making the tip of the gold wire 12 spherical is used, that is, the nail head method is used.
A stitch bonding method, a wedge bonding method, an ultrasonic bonding method, or the like can be used.

また、熱圧着の工程においては、半導体チップ１を加
熱してもよいし、キャピラリ10を加熱してもよい。In the thermocompression bonding step, the semiconductor chip 1 may be heated, or the capillary 10 may be heated.

〔発明の効果〕〔The invention's effect〕

以上述べたように本発明によれば、半導体チップの表
面に形成されるパッドの全てを保護膜から露出させると
ともに、リードに接続されないパッドを線状導体によっ
て覆うようにしたので、リードに接続されないパッド
は、ワイヤボンディングの際に線状導体の一部によって
覆われることになり、そのパッドと腐食物質との接触を
断って、使用しないパッドの腐食を防止することができ
る。As described above, according to the present invention, all the pads formed on the surface of the semiconductor chip are exposed from the protective film, and the pads not connected to the leads are covered with the linear conductors, so that the pads are not connected to the leads. The pad is covered by a part of the linear conductor at the time of wire bonding, and the contact between the pad and the corrosive substance is cut off, thereby preventing corrosion of an unused pad.

しかも、リードに繋げるパッドを別なものに変更した
としても、保護膜に形成されるパッド露出用の窓を変更
する必要がなくなり、半導体チップの汎用性を高めて量
産性を向上することが可能になる。In addition, even if the pad connected to the lead is changed to another, it is not necessary to change the window for exposing the pad formed on the protective film, and the versatility of the semiconductor chip can be increased and the mass productivity can be improved. become.

【図面の簡単な説明】[Brief description of the drawings]

第１図は、本発明の一実施例装置に使用される半導体チ
ップの一例を示す平面図及び部分拡大斜視図、 第２図は、本発明の一実施例方法によって形成された装
置の一例を示す平面図、 第３図は、本発明の一実施例方法の工程を示す断面図、 第４図は、従来方法によって形成される半導体装置の一
例を示す平面図、 第５図は、従来方法に用いられる半導体チップの一例を
示す平面図である。 （符号の説明） １……半導体チップ、 ２……活性領域、 ３……パッド、 ５……窓、 ６……リードフレーム、 ７……ダイパッド（チップ載置台）、 ８……リード、 10……キャピラリ、 11……金線導入孔、 12……金線（線状導体）。FIG. 1 is a plan view and a partially enlarged perspective view showing an example of a semiconductor chip used in an apparatus according to an embodiment of the present invention. FIG. 2 is an example of an apparatus formed by a method according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing steps of a method according to one embodiment of the present invention. FIG. 4 is a plan view showing an example of a semiconductor device formed by a conventional method. FIG. 2 is a plan view showing an example of a semiconductor chip used for the present invention. (Explanation of reference numerals) 1 ... Semiconductor chip, 2 ... Active area, 3 ... Pad, 5 ... Window, 6 ... Lead frame, 7 ... Die pad (chip mounting table), 8 ... Lead, 10 ... … Capillary, 11… Gold wire introduction hole, 12… Gold wire (linear conductor).

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】保護膜（４）に設けた複数の窓（５）によ
って複数のパッド（３）の全てを個々に露出させた半導
体チップ（１）を用い、前記パッド（３）のうち使用さ
れないパッド（３）の上に線状導体（12）の一端をボン
ディングした後に、該線状導体（12）を伸ばさずに切断
し、使用されない前記パッド（３）を前記線状導体（1
2）の一部によって覆うことを特徴とする半導体装置の
製造方法。A semiconductor chip (1) in which all of a plurality of pads (3) are individually exposed by a plurality of windows (5) provided in a protective film (4) is used among the pads (3). After bonding one end of the linear conductor (12) on the pad (3) that is not used, the linear conductor (12) is cut without extending, and the unused pad (3) is removed from the linear conductor (1).
2) A method for manufacturing a semiconductor device, wherein the semiconductor device is covered by a part of the method. 【請求項２】保護膜（４）に設けた複数の窓（５）によ
って複数のパッド（３）の全てを個々に露出させた半導
体チップ（１）を、チップ載置台（７）の上に取付ける
工程と、 前記チップ載置台（７）周囲のリード（８）に接続され
ない前記パッド（３）の上に線状導体（12）の一端を圧
着した後に、該線状導体（12）を引き伸ばさずに切断
し、使用されない前記パッド（３）を線状導体（12）の
一部によって覆う工程と、 前記リード（８）に接続される前記パッド（３）の上に
線状導体（12）の一端を接続した後に、該線状導体（1
2）を引き伸ばして前記リード（３）に圧着し、使用さ
れる前記パッド（３）と前記リード（８）とを導通させ
る工程とを備えたことを特徴とする半導体装置の製造方
法。2. A semiconductor chip (1) in which all of a plurality of pads (3) are individually exposed by a plurality of windows (5) provided in a protective film (4) is placed on a chip mounting table (7). Attachment step: After crimping one end of the linear conductor (12) onto the pad (3) that is not connected to the lead (8) around the chip mounting table (7), stretch the linear conductor (12). Covering the unused pad (3) with a part of the linear conductor (12), and cutting the linear conductor (12) on the pad (3) connected to the lead (8). After connecting one end of the linear conductor (1
2) stretching and pressing the leads (3) onto the leads (3) to conduct the pads (3) and the leads (8) to be used.
JP2270029A 1990-10-08 1990-10-08 Method for manufacturing semiconductor device Expired - Fee Related JP2846095B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2270029A JP2846095B2 (en) 1990-10-08 1990-10-08 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2270029A JP2846095B2 (en) 1990-10-08 1990-10-08 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH04145633A JPH04145633A (en) 1992-05-19
JP2846095B2 true JP2846095B2 (en) 1999-01-13

Family

ID=17480543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2270029A Expired - Fee Related JP2846095B2 (en) 1990-10-08 1990-10-08 Method for manufacturing semiconductor device

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Country Link
JP (1) JP2846095B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6758986B2 (en) * 2015-08-27 2020-09-23 住友化学株式会社 Slit processing Stretch film manufacturing method and manufacturing equipment

Also Published As

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JPH04145633A (en) 1992-05-19

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