JP2005150294A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2005150294A
JP2005150294A JP2003383785A JP2003383785A JP2005150294A JP 2005150294 A JP2005150294 A JP 2005150294A JP 2003383785 A JP2003383785 A JP 2003383785A JP 2003383785 A JP2003383785 A JP 2003383785A JP 2005150294 A JP2005150294 A JP 2005150294A
Authority
JP
Japan
Prior art keywords
lead
bonding
wires
wire
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003383785A
Other languages
Japanese (ja)
Other versions
JP2005150294A5 (en
Inventor
Hajime Hasebe
一 長谷部
Atsushi Fujisawa
敦 藤澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Renesas Technology Corp
Renesas Northern Japan Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Renesas Northern Japan Semiconductor Inc filed Critical Renesas Technology Corp
Priority to JP2003383785A priority Critical patent/JP2005150294A/en
Publication of JP2005150294A publication Critical patent/JP2005150294A/en
Publication of JP2005150294A5 publication Critical patent/JP2005150294A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48455—Details of wedge bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49425—Wedge bonds
    • H01L2224/49427—Wedge bonds outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability and manufacturing yield of a semiconductor device. <P>SOLUTION: The QFN package-type semiconductor device comprises a semiconductor chip, a plurality of leads 4, a plurality of bonding wires for electrically connecting the plurality of leads 4 and a plurality of electrodes on the surface of the semiconductor chip, and a sealing resin section for sealing these components. When connecting a plurality of bonding wires 6e and 6f to one lead 4 out of the plurality of leads 4, wire bonding is so carried out that tool marks 31e and 31f created on the top face of the lead 4 may planarly overlap each other to allow joints 32e and 32f of the bonding wires 6e and 6f on the top face of the lead 4 to overlap each other. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置およびその製造技術に関し、特に、ＱＦＮ（Quad Flat Non leaded package）パッケージ形態の半導体装置に適用して有効な技術に関する。   The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a technique effective when applied to a semiconductor device in a QFN (Quad Flat Non leaded package) package form.

リードフレームのダイパッド部（タブ）上に半導体チップを搭載し、リードフレームのリード部と半導体チップの表面の電極とをワイヤボンディングした後、樹脂封止を行い、各個片に切断してＱＦＮ（Quad Flat Non leaded package）パッケージ形態の半導体装置が製造される。リードフレームのリード部と半導体チップの電極とは、ボンディングワイヤを介して電気的に接続されている（例えば特許文献１参照）。
特開２０００−２４３８９１号公報 A semiconductor chip is mounted on the die pad part (tab) of the lead frame, the lead part of the lead frame and the electrode on the surface of the semiconductor chip are wire-bonded, and then sealed with resin, cut into individual pieces, and QFN (Quad Flat non leaded package) semiconductor devices are manufactured. The lead part of the lead frame and the electrode of the semiconductor chip are electrically connected via a bonding wire (see, for example, Patent Document 1).
JP 2000-243891 A

本発明者の検討によれば、次のことが分かった。   According to the study of the present inventor, the following has been found.

電気特性改善や向上のために、半導体チップの複数の電極に接続した複数のボンディングワイヤを一つのリード部に対して接続する多重ボンディング（いわゆるダブルボンディングやトリプルボンディング）が行われている。このような多重ボンディングを行う場合、ボンディングワイヤ接続の安定性を確保するためワイヤボンディング時に生じるツール（キャピラリ）痕を回避して次のワイヤボンディングを行う必要があるので、リードにおけるボンディング点間の距離はツールサイズを考慮して充分に間隔をとる必要がある。このため、多重ボンディングを行うには、リードのボンディング領域（ボンディングワイヤを接続するためのリードの平坦領域）を比較的広くしなければならず、半導体装置の小型化が困難になる。また、多重ボンディングを行うと、ボンディングワイヤのリードへの接続の信頼性が低下しやすく、半導体装置の信頼性が低下する可能性がある。   In order to improve or improve electrical characteristics, multiple bonding (so-called double bonding or triple bonding) is performed in which a plurality of bonding wires connected to a plurality of electrodes of a semiconductor chip are connected to one lead portion. When performing such multiple bonding, it is necessary to avoid the tool (capillary) trace generated during wire bonding in order to ensure the stability of the bonding wire connection, so that the next wire bonding must be performed. It is necessary to allow sufficient space in consideration of the tool size. For this reason, in order to perform multiple bonding, the bonding area of the leads (the flat area of the leads for connecting the bonding wires) must be relatively wide, and it is difficult to reduce the size of the semiconductor device. In addition, if multiple bonding is performed, the reliability of the connection of the bonding wire to the lead tends to be lowered, and the reliability of the semiconductor device may be lowered.

本発明の目的は、半導体装置の小型化を可能とする技術を提供することにある。   An object of the present invention is to provide a technology that enables a semiconductor device to be miniaturized.

本発明の他の目的は、半導体装置の信頼性を向上させることができる技術を提供することにある。   Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

本発明は、半導体チップの複数の電極と複数のリード部とをワイヤを介して電気的に接続し、同じリード部に複数のワイヤを接続する場合に、そのリード部における各ワイヤの接合部を重ねるものである。   In the present invention, when a plurality of electrodes of a semiconductor chip and a plurality of lead portions are electrically connected via wires, and a plurality of wires are connected to the same lead portion, the bonding portion of each wire in the lead portion is determined. It is something to be stacked.

また、本発明は、半導体チップの複数の電極と複数のリード部とをワイヤを介して電気的に接続し、同じリード部に複数のワイヤを接続する場合に、そのリード部におけるツールマークが重なるようにするものである。   Further, according to the present invention, when a plurality of electrodes of a semiconductor chip and a plurality of lead portions are electrically connected via wires and a plurality of wires are connected to the same lead portion, tool marks in the lead portions overlap. It is what you want to do.

また、本発明は、半導体チップの複数の電極と複数のリード部とをワイヤを介して電気的に接続し、同じリード部に複数のワイヤを接続する場合に、そのリード部におけるワイヤの接合部を、金を含む部材を介在して重ねるものである。   Further, the present invention provides a bonding portion of wires in a lead portion when a plurality of electrodes and a plurality of lead portions of a semiconductor chip are electrically connected via wires and a plurality of wires are connected to the same lead portion. Are stacked with a member including gold interposed therebetween.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。   Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

半導体チップの複数の電極と複数のリード部とをワイヤを介して電気的に接続し、同じリード部に複数のワイヤを接続する場合に、そのリード部における各ワイヤの接合部を重ねることにより、半導体装置を小型化することができる。また、半導体装置の信頼性を向上することができる。   By electrically connecting a plurality of electrodes and a plurality of lead portions of a semiconductor chip via wires, and connecting a plurality of wires to the same lead portion, by overlapping the joint portions of the wires in the lead portions, The semiconductor device can be reduced in size. In addition, the reliability of the semiconductor device can be improved.

また、半導体チップの複数の電極と複数のリード部とをワイヤを介して電気的に接続し、同じリード部に複数のワイヤを接続する場合に、そのリード部におけるツールマークが重なるようにすることにより、半導体装置を小型化することができる。また、半導体装置の信頼性を向上することができる。   In addition, when a plurality of electrodes and a plurality of leads of a semiconductor chip are electrically connected via wires, and a plurality of wires are connected to the same lead, the tool marks in the leads are overlapped. Thus, the semiconductor device can be reduced in size. In addition, the reliability of the semiconductor device can be improved.

また、半導体チップの複数の電極と複数のリード部とをワイヤを介して電気的に接続し、同じリード部に複数のワイヤを接続する場合に、そのリード部におけるワイヤの接合部を間に金を含む部材を介在して重ねることにより、半導体装置を小型化することができる。また、半導体装置の信頼性を向上することができる。   Further, when a plurality of electrodes of a semiconductor chip and a plurality of lead portions are electrically connected via wires, and a plurality of wires are connected to the same lead portion, the joint portion of the wire in the lead portion is interposed between The semiconductor device can be reduced in size by interposing a member including the element. In addition, the reliability of the semiconductor device can be improved.

以下の実施の形態においては便宜上その必要があるときは、複数のセクションに分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。   In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections. However, unless otherwise specified, they are not irrelevant to each other, and one is a part of the other or All the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

また、実施の形態で用いる図面においては、断面図であっても図面を見易くするためにハッチングを省略する場合もある。また、平面図であっても図面を見易くするためにハッチングを付す場合もある。   In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

（実施の形態１）
本実施の形態の半導体装置を図面を参照して説明する。 (Embodiment 1)
The semiconductor device of the present embodiment will be described with reference to the drawings.

図１は、本発明の一実施の形態である半導体装置１の平面（上面）透視図であり、図２はその断面図、図３はその底面図（裏面図）である。図１は、封止樹脂部２を透視したときの平面（上面）図に対応する。また、図１のＡ−Ａ線の断面が図２にほぼ対応する。   1 is a plan (top) perspective view of a semiconductor device 1 according to an embodiment of the present invention, FIG. 2 is a sectional view thereof, and FIG. 3 is a bottom view (back view) thereof. FIG. 1 corresponds to a plan view (upper surface) when the sealing resin portion 2 is seen through. A cross section taken along line AA in FIG. 1 substantially corresponds to FIG.

本実施の形態の半導体装置１は、樹脂封止形で、面実装形の半導体パッケージであり、例えばＱＦＮ（Quad Flat Non leaded package）形態の半導体装置である。   The semiconductor device 1 according to the present embodiment is a resin-encapsulated and surface-mounted semiconductor package, for example, a QFN (Quad Flat Non leaded package) semiconductor device.

図１〜図３示される本実施の形態の半導体装置１は、封止樹脂部（封止部）２と、封止樹脂部２によって封止された半導体チップ（半導体素子）３と、導電体によって形成された複数のリード（リード部）４と、封止樹脂部２によって封止されかつ複数のリード４と半導体チップ３の表面の複数の電極（ボンディングパッド、パッド電極）３ａとを電気的に接続する複数のボンディングワイヤ６と、半導体チップ３が搭載されたチップ搭載部であるタブ（ダイパッド部、チップ搭載部）７と、タブ７に接続された複数の吊りリード（導体部）８とを備えている。   1 to 3 includes a sealing resin part (sealing part) 2, a semiconductor chip (semiconductor element) 3 sealed with the sealing resin part 2, and a conductor. Electrically connecting a plurality of leads (lead portions) 4 formed by the above, a plurality of leads 4 sealed by the sealing resin portion 2 and a plurality of electrodes (bonding pads, pad electrodes) 3a on the surface of the semiconductor chip 3 A plurality of bonding wires 6 connected to the semiconductor chip, a tab (die pad portion, chip mounting portion) 7 which is a chip mounting portion on which the semiconductor chip 3 is mounted, and a plurality of suspension leads (conductor portions) 8 connected to the tab 7. It has.

封止樹脂部２は、例えば熱硬化性樹脂材料などの樹脂材料などからなり、フィラーなどを含むこともできる。例えば、フィラーを含むエポキシ樹脂などを用いて封止樹脂部２を形成することができる。封止樹脂部２により、半導体チップ３、リード４、ボンディングワイヤ６、タブ７および吊りリード８が封止され、保護される。封止樹脂部２の裏面（実装面）２ａが、半導体装置１の実装面である。   The sealing resin portion 2 is made of, for example, a resin material such as a thermosetting resin material, and can include a filler. For example, the sealing resin portion 2 can be formed using an epoxy resin containing a filler. With the sealing resin portion 2, the semiconductor chip 3, the lead 4, the bonding wire 6, the tab 7 and the suspension lead 8 are sealed and protected. A back surface (mounting surface) 2 a of the sealing resin portion 2 is a mounting surface of the semiconductor device 1.

半導体チップ３は、例えば、単結晶シリコンなどからなる半導体基板（半導体ウエハ）に種々の半導体素子または半導体集積回路を形成した後、必要に応じて半導体基板の裏面研削を行ってから、ダイシングなどにより半導体基板を各半導体チップ３に分離したものである。半導体チップ３は、その表面（半導体素子形成側の主面）が上方を向くようにタブ７上に搭載され、半導体チップ３の裏面（半導体素子形成側の面とは逆側の主面）が導電体からなるタブ７に、例えば銀ペーストまたは絶縁ペーストなどの接合材（図示せず）を介して接着（接合）されている。   For example, the semiconductor chip 3 is formed by forming various semiconductor elements or semiconductor integrated circuits on a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like, and then grinding the back surface of the semiconductor substrate as necessary, followed by dicing or the like. The semiconductor substrate is separated into each semiconductor chip 3. The semiconductor chip 3 is mounted on the tab 7 so that the front surface (main surface on the semiconductor element forming side) faces upward, and the back surface (main surface opposite to the surface on the semiconductor element forming side) of the semiconductor chip 3 is The tab 7 made of a conductor is bonded (bonded) via a bonding material (not shown) such as silver paste or insulating paste.

半導体チップ３の表面には、複数の電極３ａが形成されている。電極３ａは、半導体チップ３に形成された半導体素子または半導体集積回路に電気的に接続されている。半導体チップ３の表面の各電極３ａは、各リード４の上面４ａに、例えば金（Ａｕ）線などの金属細線などからなるボンディングワイヤ６を介して電気的に接続されている。   A plurality of electrodes 3 a are formed on the surface of the semiconductor chip 3. The electrode 3a is electrically connected to a semiconductor element or a semiconductor integrated circuit formed on the semiconductor chip 3. Each electrode 3a on the surface of the semiconductor chip 3 is electrically connected to the upper surface 4a of each lead 4 via a bonding wire 6 made of a fine metal wire such as a gold (Au) wire.

リード４はタブ７の周囲に、その一端がタブ７に対向するように配置されている。リード４は、封止樹脂部２に埋め込まれたインナリードと、封止樹脂部２の裏面２ａに露出するアウタリードとの両者の機能を兼ねている。すなわち、封止樹脂部２によって封止され、リード４のボンディング部として機能し得るリード４の上面４ａに、ボンディングワイヤ６が接続（接合）され、封止樹脂部２の裏面２ａに、外部接続用端子部として機能し得るリード４の下面の露出部である下部露出面４ｂが露出している。リード４の上面４ａには、ボンディングワイヤ６の接続を容易にするためにめっき層（例えば銀めっき層）を形成することもできる。リード４の下部露出面４ｂは、例えば略長方形状を有している。   The lead 4 is arranged around the tab 7 so that one end thereof faces the tab 7. The lead 4 functions as both an inner lead embedded in the sealing resin portion 2 and an outer lead exposed on the back surface 2a of the sealing resin portion 2. That is, the bonding wire 6 is connected (bonded) to the upper surface 4 a of the lead 4 that is sealed by the sealing resin portion 2 and can function as a bonding portion of the lead 4, and externally connected to the back surface 2 a of the sealing resin portion 2. A lower exposed surface 4b that is an exposed portion of the lower surface of the lead 4 that can function as a terminal portion for use is exposed. A plating layer (for example, a silver plating layer) may be formed on the upper surface 4a of the lead 4 in order to facilitate the connection of the bonding wire 6. The lower exposed surface 4b of the lead 4 has, for example, a substantially rectangular shape.

リード４のタブ７に対向する側の端部とは逆側の端部として、リード４の切断面（側面、端面）４ｃが封止樹脂部２の切断面（側面）２ｂで露出している。リード４の切断面４ｃおよび封止樹脂部２の切断面２ｂは、半導体装置を製造する際の切断工程により生じた側面（端面）である。   The cut surface (side surface, end surface) 4c of the lead 4 is exposed at the cut surface (side surface) 2b of the sealing resin portion 2 as the end portion opposite to the end portion of the lead 4 facing the tab 7. . The cut surface 4c of the lead 4 and the cut surface 2b of the sealing resin portion 2 are side surfaces (end surfaces) generated by a cutting process when manufacturing a semiconductor device.

リード４と半導体チップ３との間は封止樹脂部２を構成する材料で満たされており、リード４と半導体チップ３とが接触しないようになっている。また、隣り合うリード４間は封止樹脂部２を構成する材料により満たされており、互いに接触しないようになっている。   The space between the lead 4 and the semiconductor chip 3 is filled with the material constituting the sealing resin portion 2 so that the lead 4 and the semiconductor chip 3 do not come into contact with each other. Further, the space between the adjacent leads 4 is filled with the material constituting the sealing resin portion 2 so as not to contact each other.

封止樹脂部２の裏面２ａに対応する半導体装置１の裏面（底面）が、半導体装置１の実装面となり、各リード４の下部露出面４ｂが封止樹脂部２の裏面２ａ（すなわち半導体装置１の裏面）で露出して半導体装置１の外部端子（外部接続用端子）を構成する。また、封止樹脂部２の裏面２ａで露出するリード４の下部露出面４ｂ上にはめっき層（例えば半田めっき層）が形成されているが、理解を簡単にするために、めっき層の図示を省略している。リード４の下部露出面４ｂ上にめっき層が形成されていることで、半導体装置１を基板（外部基板、マザーボード）に実装する際に、基板上の端子または導体パターンと半導体装置１の端子（リード４の下部露出面４ｂ）との間の電気的接続の信頼性を向上することができる。   The back surface (bottom surface) of the semiconductor device 1 corresponding to the back surface 2a of the sealing resin portion 2 is the mounting surface of the semiconductor device 1, and the lower exposed surface 4b of each lead 4 is the back surface 2a of the sealing resin portion 2 (that is, the semiconductor device). 1 is exposed to form an external terminal (external connection terminal) of the semiconductor device 1. In addition, a plating layer (for example, a solder plating layer) is formed on the lower exposed surface 4b of the lead 4 exposed on the back surface 2a of the sealing resin portion 2, but for the sake of easy understanding, the plating layer is illustrated. Is omitted. Since the plating layer is formed on the lower exposed surface 4b of the lead 4, when the semiconductor device 1 is mounted on the substrate (external substrate, mother board), the terminal or conductor pattern on the substrate and the terminal of the semiconductor device 1 ( The reliability of electrical connection with the lower exposed surface 4b) of the lead 4 can be improved.

タブ７には、複数（ここでは４本）の吊りリード（導体部）８が接続されている。各吊りリード８は、導電体材料からなり、一端がタブ７に接続され、タブ７の外方に向かって延在している。吊りリード８は、半導体装置１の製造に用いられたリードフレーム（のフレーム枠）にタブ７を保持または支持するために設けられ、封止樹脂部２の形成後にリードフレームから切断され、吊りリード８の切断により生じた側面（すなわちタブ７に接続された側の端部とは逆側の端部）である切断面８ｃが封止樹脂部２の切断面（側面）２ｂで露出している。吊りリード８の下面の一部は封止樹脂部２の裏面２ａで露出しており、ここでは吊りリード８の切断面８ｃ近傍領域の下面である下部露出面８ｂが、封止樹脂部２の裏面２ａで露出している。吊りリード８には屈曲部が設けられており、吊りリード８のうち下部露出面８ｂよりもタブ７側の部分は上方に持ち上げられて、タブ７とともに封止樹脂部２内に封止されている。リード４、タブ７および吊りリード８は、いずれも導電体材料からなり、例えば半導体装置の製造の際にリードフレームに用いられた共通の導電体材料からなる。   A plurality of (here, four) suspension leads (conductor portions) 8 are connected to the tab 7. Each suspension lead 8 is made of a conductive material, and has one end connected to the tab 7 and extending outward from the tab 7. The suspension lead 8 is provided to hold or support the tab 7 on the lead frame (the frame frame) used for manufacturing the semiconductor device 1, and is cut from the lead frame after the sealing resin portion 2 is formed. 8 is exposed at the cut surface (side surface) 2 b of the sealing resin portion 2. The cut surface 8 c, which is a side surface generated by cutting 8 (that is, the end opposite to the end connected to the tab 7). . A part of the lower surface of the suspension lead 8 is exposed on the back surface 2 a of the sealing resin portion 2, and here, the lower exposed surface 8 b that is the lower surface of the region near the cut surface 8 c of the suspension lead 8 is the sealing resin portion 2. It is exposed at the back surface 2a. The suspension lead 8 is provided with a bent portion, and the portion of the suspension lead 8 that is closer to the tab 7 than the lower exposed surface 8 b is lifted upward and sealed in the sealing resin portion 2 together with the tab 7. Yes. The lead 4, the tab 7 and the suspension lead 8 are all made of a conductor material, for example, a common conductor material used for a lead frame in manufacturing a semiconductor device.

上記のように、半導体チップ３の複数の電極３ａと複数のリード４とが複数のボンディングワイヤ６を介して電気的に接続されている。半導体チップ３の各電極３ａにボンディングワイヤ６の一端が接続され、ボンディングワイヤ６の他端が各リード４の上面４ａに接続される。本実施の形態の半導体装置１では、電気特性改善や向上のために、半導体チップ３の複数の電極３ａにそれぞれ接続した複数のボンディングワイヤ６を同じ（一つの）リード４に対して接続する多重ボンディング（いわゆるダブルボンディングやトリプルボンディングなど）が行われている。例えば、図１では、それぞれ半導体チップ３の電極３ａに一端が接続された２本のボンディングワイヤ６の他端が、同じ（一つの）リード４ｄに接続（いわゆるダブルボンディング）され、それぞれ半導体チップ３の電極３ａに一端が接続された２本のボンディングワイヤ６の他端が、同じ（一つの）リード４ｅに接続（いわゆるダブルボンディング）され、それぞれ半導体チップ３の電極３ａに一端が接続された３本のボンディングワイヤ６の他端が、同じ（一つの）リード４ｆに接続（いわゆるトリプルボンディング）されている。図１では、複数のリード４のうち、リード４ｄには２本、リード４ｅには２本、リード４ｆには３本、他のリード４には１本のボンディングワイヤ６がそれぞれ接続されているが、一つのリード４に接続されるボンディングワイヤ６の数はこれに限定されるものではなく、例えば４本以上のボンディングワイヤ６を同じ（一つの）リード４に対して接続することもできる。   As described above, the plurality of electrodes 3 a of the semiconductor chip 3 and the plurality of leads 4 are electrically connected via the plurality of bonding wires 6. One end of the bonding wire 6 is connected to each electrode 3 a of the semiconductor chip 3, and the other end of the bonding wire 6 is connected to the upper surface 4 a of each lead 4. In the semiconductor device 1 according to the present embodiment, a plurality of bonding wires 6 respectively connected to the plurality of electrodes 3a of the semiconductor chip 3 are connected to the same (one) lead 4 in order to improve or improve electrical characteristics. Bonding (so-called double bonding, triple bonding, etc.) is performed. For example, in FIG. 1, the other ends of the two bonding wires 6 each having one end connected to the electrode 3a of the semiconductor chip 3 are connected to the same (one) lead 4d (so-called double bonding), and each of the semiconductor chips 3 is connected. The other ends of the two bonding wires 6 having one end connected to the electrode 3a are connected to the same (one) lead 4e (so-called double bonding), and one end is connected to the electrode 3a of the semiconductor chip 3, respectively. The other end of the bonding wire 6 is connected to the same (one) lead 4f (so-called triple bonding). In FIG. 1, of the plurality of leads 4, two are connected to the lead 4 d, two are connected to the lead 4 e, three are connected to the lead 4 f, and one bonding wire 6 is connected to the other leads 4. However, the number of bonding wires 6 connected to one lead 4 is not limited to this. For example, four or more bonding wires 6 can be connected to the same (one) lead 4.

本実施の形態では、リード４ｄ，４ｅ，４ｆのように同じ（一つの）リード４に複数のボンディングワイヤ６を接続する場合、後述するように、そのリード４の同じ位置にワイヤボンディングを行い、そのリード４（リード４ｄ，４ｅ，４ｆ）に接続する各ボンディングワイヤ６の接合部が重なる（積み重なる）ようにしている。このため、本実施の形態の半導体装置１では、リード４ｄ，４ｅ，４ｆのそれぞれにおいて、複数のボンディングワイヤ６の接合部が重なっている。   In the present embodiment, when a plurality of bonding wires 6 are connected to the same (single) lead 4 like the leads 4d, 4e, 4f, wire bonding is performed at the same position of the lead 4, as will be described later. The bonding portions of the bonding wires 6 connected to the leads 4 (leads 4d, 4e, 4f) are overlapped (stacked). For this reason, in the semiconductor device 1 of the present embodiment, the joints of the plurality of bonding wires 6 overlap each other in each of the leads 4d, 4e, and 4f.

次に、本実施の形態の半導体装置の製造工程について説明する。図４〜図７は、本実施の形態の半導体装置の製造工程を示す断面図（要部断面図）である。図４〜図７は、図２に対応する断面が示されている。また、図４〜図７には、リードフレーム１１の一つの半導体パッケージに対応する領域（そこから一つの半導体装置１が製造される領域）が示されている。   Next, the manufacturing process of the semiconductor device of this embodiment will be described. 4 to 7 are cross-sectional views (main-part cross-sectional views) showing the manufacturing process of the semiconductor device of the present embodiment. 4 to 7 show cross sections corresponding to FIG. 4 to 7 show a region corresponding to one semiconductor package of the lead frame 11 (a region from which one semiconductor device 1 is manufactured).

まず、図４に示されるように、半導体装置１の製造に用いられるリードフレーム１１を準備する。リードフレーム１１は、例えば、銅または銅合金、あるいは４２−アロイなどの導電体材料からなる。リードフレーム１１は、半導体チップ３を搭載するためのタブ７と、その一端がタブ７と離間して対向するように配置され他端がリードフレーム１１のフレーム枠（図示せず）と接続するリード４とを有している。また、図４の断面には示されていないけれども、タブ７の四隅に吊りリード８の一端が接続し吊りリード８の他端がフレーム枠に接続してタブ７がリードフレーム１１のフレーム枠に保持または支持されている。   First, as shown in FIG. 4, a lead frame 11 used for manufacturing the semiconductor device 1 is prepared. The lead frame 11 is made of, for example, a conductor material such as copper, a copper alloy, or 42-alloy. The lead frame 11 is a tab 7 for mounting the semiconductor chip 3, a lead that is arranged so that one end thereof is spaced apart and opposed to the tab 7, and the other end is connected to a frame frame (not shown) of the lead frame 11. 4. Although not shown in the cross section of FIG. 4, one end of the suspension lead 8 is connected to the four corners of the tab 7, the other end of the suspension lead 8 is connected to the frame frame, and the tab 7 becomes the frame frame of the lead frame 11. Retained or supported.

次に、図５に示されるように、リードフレーム１１のタブ７上に半導体チップ３を銀ペーストまたは絶縁ペーストなどの接合材（図示せず）を介して接着（接合）する。   Next, as shown in FIG. 5, the semiconductor chip 3 is bonded (bonded) to the tab 7 of the lead frame 11 via a bonding material (not shown) such as silver paste or insulating paste.

次に、図６に示されるように、ワイヤボンディング工程を行って、半導体チップ３の複数の電極３ａとリードフレーム１１の複数のリード４の上面４ａとを複数のボンディングワイヤ６を介してそれぞれ電気的に接続する。この際、ボンディングワイヤ６の一端を半導体チップ３の電極３ａに接続（ファーストボンディング）してから、ボンディングワイヤ６の他端をリード４に接続（セカンドボンディング）する。   Next, as shown in FIG. 6, a wire bonding step is performed to electrically connect the plurality of electrodes 3 a of the semiconductor chip 3 and the top surfaces 4 a of the plurality of leads 4 of the lead frame 11 through the plurality of bonding wires 6. Connect. At this time, one end of the bonding wire 6 is connected to the electrode 3a of the semiconductor chip 3 (first bonding), and the other end of the bonding wire 6 is connected to the lead 4 (second bonding).

次に、図７に示されるように、モールド工程（例えばトランスファモールド工程）を行って、半導体チップ３、ボンディングワイヤ６およびタブ７を封止樹脂部２によって封止する。封止樹脂部２は、例えば熱硬化性樹脂材料などの樹脂材料などからなり、フィラーなどを含むこともできる。例えば、フィラーを含むエポキシ樹脂などを用いて封止樹脂部２を形成することができる。また、封止樹脂工程では、封止樹脂部２の裏面２ａからリード４の下面である下部露出面４ｂが露出するように、封止樹脂部２を形成する。   Next, as shown in FIG. 7, a molding process (for example, a transfer molding process) is performed to seal the semiconductor chip 3, the bonding wire 6, and the tab 7 with the sealing resin portion 2. The sealing resin portion 2 is made of, for example, a resin material such as a thermosetting resin material, and can include a filler. For example, the sealing resin portion 2 can be formed using an epoxy resin containing a filler. In the sealing resin step, the sealing resin portion 2 is formed so that the lower exposed surface 4 b that is the lower surface of the lead 4 is exposed from the back surface 2 a of the sealing resin portion 2.

次に、必要に応じてリードフレーム１１の封止樹脂部２から露出する部分（導電体からなる部分）上にめっき層（図示せず）を形成した後、リードフレーム１１が所定の位置で切断されて、図１〜図３に示されるような個片に分割された半導体装置１が得られる（製造される）。   Next, after forming a plating layer (not shown) on a portion exposed from the sealing resin portion 2 of the lead frame 11 (a portion made of a conductor) as necessary, the lead frame 11 is cut at a predetermined position. Thus, the semiconductor device 1 divided into individual pieces as shown in FIGS. 1 to 3 is obtained (manufactured).

次に、本実施の形態の半導体装置の製造工程におけるワイヤボンディング工程について説明する。   Next, the wire bonding process in the manufacturing process of the semiconductor device of this embodiment will be described.

図８〜図１１は、ワイヤボンディング工程（半導体チップ３の電極３ａとリード４との間をボンディングワイヤ６で接続する工程）の一例を示す説明図である。   8 to 11 are explanatory views showing an example of a wire bonding step (step of connecting the electrode 3a of the semiconductor chip 3 and the lead 4 with the bonding wire 6).

まず、図８に示されるように、放電などによって先端に金球２１ａを形成した金線２１（ボンディングワイヤ６形成用の金線２１）がワイヤボンディング装置のキャピラリ（ボンディングツール）２２に保持され、半導体チップ３の電極３ａ上に待機している。金線２１の直径は例えば２５〜３０μｍ程度である。それから、図９に示されるように、待機していた金線２１をファーストボンディングである半導体チップ３の電極３ａ上に適切な荷重をもって接触させ、金球２１ａが電極３ａに接触した後、キャピラリ２２を超音波振動させ、このときの荷重や印加された超音波によるエネルギーで金球２１ａと電極３ａとを接合（接続）させる。   First, as shown in FIG. 8, a gold wire 21 (gold wire 21 for forming a bonding wire 6) having a gold ball 21a formed at the tip thereof by discharge or the like is held by a capillary (bonding tool) 22 of a wire bonding apparatus, Waiting on the electrode 3 a of the semiconductor chip 3. The diameter of the gold wire 21 is, for example, about 25 to 30 μm. Then, as shown in FIG. 9, the waiting gold wire 21 is brought into contact with the electrode 3a of the semiconductor chip 3 which is the first bonding with an appropriate load, and after the gold ball 21a contacts the electrode 3a, the capillary 22 Are vibrated ultrasonically, and the gold sphere 21a and the electrode 3a are joined (connected) with the load and energy of the applied ultrasonic wave.

次に、図１０に示されるように、キャピラリ２２が適切な軌跡を描きながら移動して、リード４の上面に移動する。この軌跡によって、ボンディングワイヤの適切なループ形状が得られる。そして、リード４の上面４ａに対してキャピラリ２２に保持された金線２１が適切な荷重をもって押し付けられ、キャピラリ２２が超音波振動する。このときの荷重や印加された超音波によるエネルギーで金線２１とリード４の上面４ａとを接合（接続）させる。   Next, as shown in FIG. 10, the capillary 22 moves while drawing an appropriate locus, and moves to the upper surface of the lead 4. With this trajectory, an appropriate loop shape of the bonding wire can be obtained. And the gold | metal wire 21 hold | maintained at the capillary 22 with respect to the upper surface 4a of the lead | read | reed 4 is pressed with an appropriate load, and the capillary 22 vibrates ultrasonically. The gold wire 21 and the upper surface 4a of the lead 4 are joined (connected) with the load and energy of the applied ultrasonic wave at this time.

その後、図１１に示されるように、キャピラリ２２が上昇する過程でワイヤクランパ２３で金線２１を保持し、金線２１をセカンドボンディング点（接合部）から切断する。このようにして、半導体チップ３の電極３ａとリード４の上面４ａとの間を金線２１（金球２１ａを含む金線２１）からなるボンディングワイヤ６で電気的に接続することができる。   Thereafter, as shown in FIG. 11, the gold wire 21 is held by the wire clamper 23 in the process of raising the capillary 22, and the gold wire 21 is cut from the second bonding point (joint portion). In this way, the electrode 3a of the semiconductor chip 3 and the upper surface 4a of the lead 4 can be electrically connected by the bonding wire 6 made of the gold wire 21 (the gold wire 21 including the gold ball 21a).

図１２は、上記のようにしてリード４の上面に金線２１（ボンディングワイヤ６）を接合した状態を示す説明図（斜視図）であり、リード４の先端部（タブ７に対向する側の端部）近傍領域が示されている。なお、図１２に示されるリード４の先端部近傍の上面４ａには、金線２１（ボンディングワイヤ６）の接続を容易にするためにめっき層（例えば銀めっき層）が形成されている。   FIG. 12 is an explanatory view (perspective view) showing a state in which the gold wire 21 (bonding wire 6) is bonded to the upper surface of the lead 4 as described above, and the tip of the lead 4 (on the side facing the tab 7). The (edge) vicinity region is shown. A plating layer (for example, a silver plating layer) is formed on the upper surface 4a near the tip of the lead 4 shown in FIG. 12 in order to facilitate the connection of the gold wire 21 (bonding wire 6).

セカンドボンディングにおいては、図１０に示されるように、金線２１を接続する面、ここではリード４の上面４ａにキャピラリ２２を押し付けるので、図１２に示されるように、リード４の上面４ａにはツールマーク（ボンディングツールの痕、ツール痕、キャピラリ痕）３１が残る。ツールマーク３１は、ワイヤボンディングの際にボンディングツールとしてのキャピラリ２２が押し付けられることによってリード４の上面（平坦面）４ａに生じた凹凸または窪みである。リード４の上面４ａに対する金線２１（ボンディングワイヤ６）の接合部（圧着部）３２は、ツールマーク３１内に位置することになる。ツールマーク３１の平面形状または平面寸法（外形寸法）は、リード４に接触するキャピラリ２２の先端部形状または寸法にほぼ対応し、例えば直径１００μｍ程度の略円形などである。   In the second bonding, as shown in FIG. 10, the capillary 22 is pressed against the surface to which the gold wire 21 is connected, here, the upper surface 4a of the lead 4, so that the upper surface 4a of the lead 4 is applied to the upper surface 4a of the lead 4 as shown in FIG. Tool marks (bonding tool marks, tool marks, capillary marks) 31 remain. The tool mark 31 is an unevenness or depression formed on the upper surface (flat surface) 4a of the lead 4 when the capillary 22 as a bonding tool is pressed during wire bonding. A joint portion (crimping portion) 32 of the gold wire 21 (bonding wire 6) to the upper surface 4a of the lead 4 is located in the tool mark 31. The planar shape or planar dimension (outer dimension) of the tool mark 31 substantially corresponds to the shape or dimension of the tip of the capillary 22 that contacts the lead 4 and is, for example, a substantially circular shape with a diameter of about 100 μm.

このようにして、半導体チップ３の複数の電極３ａとリードフレーム１１の複数のリード４の上面４ａとを複数のボンディングワイヤ６を介してそれぞれ電気的に接続することができる。   In this way, the plurality of electrodes 3 a of the semiconductor chip 3 and the upper surfaces 4 a of the plurality of leads 4 of the lead frame 11 can be electrically connected to each other via the plurality of bonding wires 6.

本実施の形態においては、図１に示されるように、電気特性改善や向上のために、半導体チップ３の複数の電極３ａにそれぞれ接続した複数のボンディングワイヤ６を同じ（一つの）リード４に対して接続する多重ボンディングが行われている。しかしながら、本発明者の検討によれば、同じ（一つの）リード４に対して複数のボンディングワイヤ６を接続した場合、次のような問題点が生じる可能性があることが分かった。   In the present embodiment, as shown in FIG. 1, a plurality of bonding wires 6 respectively connected to a plurality of electrodes 3 a of the semiconductor chip 3 are connected to the same (one) lead 4 in order to improve or improve electrical characteristics. Multiple bonding for connection is performed. However, according to the study of the present inventor, it has been found that when a plurality of bonding wires 6 are connected to the same (one) lead 4, the following problems may occur.

図１３は、同じ（一つの）リードに対して複数のボンディングワイヤを接続した場合に生じ得る問題点（第１の問題点）の説明図（斜視図）であり、第１の比較例のワイヤボンディング（リードに対するボンディングワイヤの接続工程）の説明図に対応する。   FIG. 13 is an explanatory view (perspective view) of a problem (first problem) that may occur when a plurality of bonding wires are connected to the same (one) lead, and the wire of the first comparative example It corresponds to an explanatory view of bonding (bonding wire connecting step to lead).

図１３では、一つのリード３４（本実施の形態のリード４に対応）に対して複数のボンディングワイヤ、ここでは２本のボンディングワイヤ６ａ，６ｂを接続している。ボンディングワイヤ６ａ，６ｂは、それぞれ、図８〜図１１のようにして形成される。図１３では、リード３４の上面３４ａ（上面４ａに対応）におけるボンディングワイヤ６ａ，６ｂの接合部（圧着部、ボンディング部）３２ａ，３２ｂを平面的に並べて、各ボンディングワイヤ６ａ，６ｂの接続の際のツールマーク３１ａ，３１ｂが重ならないようにしている。すなわち、リード３４の上面３４ａにボンディングワイヤ６ａを接続した後に、同じリード３４の上面３４ａにボンディングワイヤ６ｂを接続しているが、ボンディングワイヤ６ａの接続の際に生じたツールマーク３１ａに、ボンディングワイヤ６ｂの接続の際に生じるツールマーク３１ｂが重ならないようにしている。   In FIG. 13, a plurality of bonding wires, here two bonding wires 6a and 6b, are connected to one lead 34 (corresponding to the lead 4 of the present embodiment). The bonding wires 6a and 6b are formed as shown in FIGS. In FIG. 13, the bonding portions (crimped portions, bonding portions) 32a and 32b of the bonding wires 6a and 6b on the upper surface 34a (corresponding to the upper surface 4a) of the lead 34 are arranged in a plane, and the bonding wires 6a and 6b are connected. The tool marks 31a and 31b are not overlapped. That is, after the bonding wire 6a is connected to the upper surface 34a of the lead 34, the bonding wire 6b is connected to the upper surface 34a of the same lead 34, but the bonding wire 6a is connected to the tool mark 31a generated when the bonding wire 6a is connected. The tool mark 31b generated at the time of connection of 6b is prevented from overlapping.

ツールマーク３１ａ，３１ｂ同士が重ならず、凹凸面（窪み部分）であるツールマーク３１ａ外のリード３４の平坦な領域にボンディングワイヤ６ｂを接続（接合）できるので、ボンディングワイヤ６ａ，６ｂのリード３４の上面３４ａへの接続の信頼性（接続強度）を高めることができる。   Since the tool marks 31a and 31b do not overlap with each other and the bonding wire 6b can be connected (bonded) to the flat region of the lead 34 outside the tool mark 31a which is an uneven surface (dented portion), the leads 34 of the bonding wires 6a and 6b are connected. The reliability (connection strength) of the connection to the upper surface 34a can be increased.

しかしながら、図１３の場合は、ツールマーク３１ａ，３１ｂが重ならないようにボンディングワイヤ６ａ，６ｂをリード３４に接続するので、ボンディングワイヤ６ａの接合部３２ａとボンディングワイヤ６ｂの接合部３２ｂとの間が比較的大きな間隔を空けて離れることになり、リード３４の上面３４ａにおいてワイヤボンディングに要する領域が大きくなってしまう。このため、図１３では、リード３４の幅を広くし、ボンディングワイヤ６ａ，６ｂを接続するための平坦領域（上面３４ａ）を大きくする必要がある。このように、リード３４の面積（または幅）を比較的大きくする必要があるので、半導体装置の小型化が困難になるという第１の問題点が生じる。   However, in the case of FIG. 13, since the bonding wires 6a and 6b are connected to the lead 34 so that the tool marks 31a and 31b do not overlap, there is a gap between the bonding portion 32a of the bonding wire 6a and the bonding portion 32b of the bonding wire 6b. A relatively large space is left apart, and the area required for wire bonding on the upper surface 34a of the lead 34 becomes large. For this reason, in FIG. 13, it is necessary to increase the width of the lead 34 and increase the flat region (upper surface 34a) for connecting the bonding wires 6a and 6b. As described above, since the area (or width) of the lead 34 needs to be relatively large, the first problem that it is difficult to reduce the size of the semiconductor device occurs.

このため、リードの幅を比較的小さくして半導体装置の小型化を実現するために、一つのリードに対して複数のボンディングワイヤを接続する際に、ツールマークが部分的に重なるように、ワイヤボンディングを行うことが考えられる。図１４は、同じ（一つの）リードに対して複数のボンディングワイヤを接続した場合に生じ得る他の問題点（第２の問題点）の説明図（斜視図）であり、第２の比較例のワイヤボンディング（リードに対するボンディングワイヤの接続工程）の説明図に対応する。   For this reason, in order to achieve a reduction in the size of the semiconductor device by relatively reducing the width of the lead, when connecting a plurality of bonding wires to one lead, the wire is arranged so that the tool mark partially overlaps. It is conceivable to perform bonding. FIG. 14 is an explanatory diagram (perspective view) of another problem (second problem) that may occur when a plurality of bonding wires are connected to the same (one) lead, and is a second comparative example. This corresponds to an explanatory diagram of wire bonding (bonding wire connecting step to lead).

図１４では、一つのリード３５（本実施の形態のリード４に対応）に対して複数のボンディングワイヤ、ここでは２本のボンディングワイヤ６ｃ，６ｄを接続している。ボンディングワイヤ６ｃ，６ｄは、それぞれ、図８〜図１１のようにして形成される。図１４では、リード３５の上面３５ａ（上面４ａに対応）におけるボンディングワイヤ６ｃ，６ｄの接合部（圧着部、ボンディング部）３２ｃ，３２ｄを近づけて各ボンディングワイヤ６ｃ，６ｄのツールマーク３１ｃ，３１ｄが部分的に重なるようにしている。すなわち、リード３５の上面３５ａにボンディングワイヤ６ｃを接続した後に、同じリード３５の上面３５ａにボンディングワイヤ６ｄを接続しているが、ボンディングワイヤ６ｃの接続の際に生じたツールマーク３１ｃに、ボンディングワイヤ６ｄの接続の際に生じるツールマーク３１ｄの一部が重なるようにしている。   In FIG. 14, a plurality of bonding wires, here two bonding wires 6c and 6d, are connected to one lead 35 (corresponding to the lead 4 of the present embodiment). The bonding wires 6c and 6d are formed as shown in FIGS. In FIG. 14, the bonding portions 6c and 6d of the bonding wires 6c and 6d on the upper surface 35a (corresponding to the upper surface 4a) of the lead 35 are brought close to each other and the tool marks 31c and 31d of the bonding wires 6c and 6d are brought close to each other. It is made to overlap partially. That is, after the bonding wire 6c is connected to the upper surface 35a of the lead 35, the bonding wire 6d is connected to the upper surface 35a of the same lead 35, but the bonding wire 6c is connected to the tool mark 31c generated when the bonding wire 6c is connected. Part of the tool mark 31d generated when 6d is connected is overlapped.

図１４の場合は、ツールマーク３１ｃ，３１ｄ同士が部分的に重なるので、ボンディングワイヤ６ｃの接合部３２ｃとボンディングワイヤ６ｄの接合部３２ｄとの間が図１３の場合よりも小さな間隔を空けて離れることになる。このため、図１４の場合は、図１３の場合に比べて、リード３５の上面３５ａにおいてワイヤボンディングに要する領域を小さくすることができ、リード３５の幅をリード３４よりも小さくすることができ、半導体装置の小型化に有利である。しかしながら、図１４の場合は、ボンディングワイヤ６ｃの接続後に行うボンディングワイヤ６ｄの接続の際に、凹凸面（または窪み）であるツールマーク３１ｃにキャピラリ２２が部分的に重なり（ずれた状態で重なり）、更にツールマーク３１ｃの端部の段差にボンディングワイヤ６ｄの接合部（圧着部）３２ｄが重なってしまう。このため、ボンディングワイヤ６ｄの接続の接続強度が低下し、ボンディングワイヤ６ｄの接続の信頼性が低下する可能性がある。   In the case of FIG. 14, since the tool marks 31c and 31d partially overlap each other, the bonding portion 32c of the bonding wire 6c and the bonding portion 32d of the bonding wire 6d are separated with a smaller interval than in the case of FIG. It will be. Therefore, in the case of FIG. 14, the area required for wire bonding on the upper surface 35 a of the lead 35 can be made smaller than in the case of FIG. 13, and the width of the lead 35 can be made smaller than the lead 34. This is advantageous for miniaturization of semiconductor devices. However, in the case of FIG. 14, when the bonding wire 6d is connected after the bonding wire 6c is connected, the capillary 22 partially overlaps with the tool mark 31c which is an uneven surface (or a depression) (overlapping in a shifted state). Furthermore, the bonding portion (crimping portion) 32d of the bonding wire 6d overlaps the step at the end of the tool mark 31c. For this reason, the connection strength of the connection of the bonding wire 6d is lowered, and the reliability of the connection of the bonding wire 6d may be lowered.

図１５〜図１７は、本実施の形態におけるワイヤボンディング（リード４に対するボンディングワイヤ６の接続工程）の説明図である。図１５は、ボンディングワイヤ６のうちの２本のボンディングワイヤ６ｅ，６ｆを同じリード４に順に接続した後の状態を示す斜視図に対応し、図１６は、図１５の拡大図に対応する。図１７は、リード４にボンディングワイヤ６ｅを接続した後、そのリード４に次のボンディングワイヤ６ｆを接続する工程中の図１０の状態の概念的な側面断面図に対応する。このため、図１７では、ボンディングワイヤ６ｆはまだ切断されていない。また、図１５〜図１７に示されるリード４は、例えば図１のリード４ｄまたはリード４ｅに対応する。   15 to 17 are explanatory diagrams of wire bonding (a step of connecting the bonding wire 6 to the lead 4) in the present embodiment. 15 corresponds to a perspective view showing a state after two bonding wires 6e and 6f of the bonding wires 6 are sequentially connected to the same lead 4, and FIG. 16 corresponds to an enlarged view of FIG. FIG. 17 corresponds to a conceptual side cross-sectional view of the state of FIG. 10 in the process of connecting the bonding wire 6 e to the lead 4 and then connecting the next bonding wire 6 f to the lead 4. For this reason, in FIG. 17, the bonding wire 6f has not been cut yet. Further, the lead 4 shown in FIGS. 15 to 17 corresponds to, for example, the lead 4d or the lead 4e in FIG.

本実施の形態では、図１５〜図１７に示されるように、同じ（一つの）リード４に対して複数のボンディングワイヤ６（図１５〜図１７の例では２本のボンディングワイヤ６ｅ，６ｆ）を接続する際に、そのリード４の上面４ａにおける複数のボンディングワイヤ６（ボンディングワイヤ６ｅ，６ｆ）の接合部（図１５〜図１７の例では接合部３２ｅ，３２ｆ）がほぼ重なる（一致する）ようにワイヤボンディング（ボンディングワイヤ６ａ，６ｂの接続）を行っている。すなわち、同じ（一つの）リード４に対して複数のボンディングワイヤ６（ボンディングワイヤ６ａ，６ｂ）を接続する際に、そのリード４の上面４ａに生じるツールマーク（ツールマーク３１ｅ，３１ｆ）が平面的にほぼ重なる（一致する）ようにワイヤボンディング（ボンディングワイヤ６ａ，６ｂの接続）を行っている。   In the present embodiment, as shown in FIGS. 15 to 17, a plurality of bonding wires 6 (two bonding wires 6 e and 6 f in the examples of FIGS. 15 to 17) with respect to the same (one) lead 4. When connecting the bonding portions of the bonding wires 6 (bonding wires 6e and 6f) on the upper surface 4a of the lead 4 (bonding portions 32e and 32f in the examples of FIGS. 15 to 17) substantially overlap (match). Thus, wire bonding (connection of bonding wires 6a and 6b) is performed. That is, when a plurality of bonding wires 6 (bonding wires 6a and 6b) are connected to the same (one) lead 4, tool marks (tool marks 31e and 31f) generated on the upper surface 4a of the lead 4 are planar. Wire bonding (connection of bonding wires 6a and 6b) is performed so as to substantially overlap (match).

図１５〜図１７では、リード４の上面４ａにボンディングワイヤ６ｅを接続した後に、同じリード４の上面４ａにボンディングワイヤ６ｆを接続しているが、ボンディングワイヤ６ｅの接続の際に生じたツールマーク（ボンディングツールの痕、ツール痕、キャピラリ痕）３１ｅに、ボンディングワイヤ６ｆの接続の際に生じるツールマーク３１ｆが平面的にほぼ重なる（一致する）ようにしている。この際、上記図１４に示されるように、ツールマーク同士の重なり領域が少ないと、ボンディングワイヤの接続の信頼性が低下する可能性がある。それに対して、本実施の形態では、図１５〜図１７に示されるように、ツールマーク３１ｅ，３１ｆ同士の重なり領域を相対的に大きくしてツールマーク３１ｅ，３１ｆが実質的に重なる（一致する）ようにしており、リード４の上面４ａに対するボンディングワイヤ６ｅの接合部（圧着部、ボンディング部）３２ｅとボンディングワイヤ６ｆの接合部（圧着部、ボンディング部）３２ｆとが多段に（上下に）積み重なるようにしている。このため、ボンディングワイヤ６ｅの接続後に行うボンディングワイヤ６ｆの接続の際に、リード４の上面４ａに接触させた（押し付けた）キャピラリ２２が凹凸面（窪み）であるツールマーク３２ｅに実質的に重なってそれらの凹凸形状がほぼ一致する。しかも、ツールマーク３１ｅの端部の段差にボンディングワイヤ６ｆの接合部（圧着部）３２ｆが重ならない。このため、的確かつスムースにボンディングワイヤ６ｆをリード４に接合することができ、ボンディングワイヤ６ｆの接続の接続強度を向上し、ボンディングワイヤ６ｆの接続の信頼性を向上することができる。これにより、ボンディングワイヤ６e，６ｆを含むボンディングワイヤ６の接続の信頼性を向上でき、半導体装置１の信頼性を向上することができる。また、半導体装置の製造歩留りを向上することもできる。   15 to 17, after the bonding wire 6 e is connected to the upper surface 4 a of the lead 4, the bonding wire 6 f is connected to the upper surface 4 a of the same lead 4, but the tool mark generated when the bonding wire 6 e is connected. The tool mark 31f generated when the bonding wire 6f is connected is substantially overlapped (coincided) in plan with the bonding tool trace, tool trace, and capillary trace 31e. At this time, as shown in FIG. 14 described above, if the overlapping area between the tool marks is small, the reliability of the bonding wire connection may be lowered. On the other hand, in the present embodiment, as shown in FIGS. 15 to 17, the tool marks 31 e and 31 f substantially overlap (match) by relatively increasing the overlapping area between the tool marks 31 e and 31 f. The bonding portion (crimping portion, bonding portion) 32e of the bonding wire 6e to the upper surface 4a of the lead 4 and the bonding portion (crimping portion, bonding portion) 32f of the bonding wire 6f are stacked in multiple stages (up and down). I am doing so. For this reason, when the bonding wire 6f is connected after the bonding wire 6e is connected, the capillary 22 brought into contact (pressed) with the upper surface 4a of the lead 4 substantially overlaps the tool mark 32e which is an uneven surface (dent). The concave and convex shapes almost coincide with each other. Moreover, the bonding portion (crimping portion) 32f of the bonding wire 6f does not overlap the step at the end of the tool mark 31e. For this reason, the bonding wire 6f can be accurately and smoothly joined to the lead 4, the connection strength of the bonding wire 6f can be improved, and the connection reliability of the bonding wire 6f can be improved. Thereby, the connection reliability of the bonding wires 6 including the bonding wires 6e and 6f can be improved, and the reliability of the semiconductor device 1 can be improved. In addition, the manufacturing yield of the semiconductor device can be improved.

また、本実施の形態では、図１５および図１６に示されるように、リード４の上面４ａには、ボンディングワイヤ６ｅ，６ｆの接続を容易にするためにめっき層（例えば銀めっき層）３６が形成されており、ボンディングワイヤ６ｅ，６ｆは、このリード４の上面４ａのめっき層３６に接続されている。これにより、ボンディングワイヤ６ｅ，６ｆを含むボンディングワイヤ６の接続の信頼性をより向上することができる。   In this embodiment, as shown in FIGS. 15 and 16, a plating layer (for example, a silver plating layer) 36 is provided on the upper surface 4 a of the lead 4 in order to facilitate the connection of the bonding wires 6 e and 6 f. The bonding wires 6 e and 6 f are formed and connected to the plating layer 36 on the upper surface 4 a of the lead 4. Thereby, the connection reliability of the bonding wires 6 including the bonding wires 6e and 6f can be further improved.

また、本実施の形態では、図１３や図１４の場合に比べて、リード４の上面４ａにおいてワイヤボンディングに要する領域（面積）を小さくすることができる。このため、リード４の幅または平面寸法を比較的小さくすることができ、半導体装置１を小型化することができる。また、インナリード部（リード４）の平坦領域の省スペース化が可能になるので、例えばＱＦＮパッケージのようにインナリード部（リード４）の上面の平坦領域が小さい半導体装置においても、多重ボンディングが可能になる。   Further, in the present embodiment, the region (area) required for wire bonding can be reduced on the upper surface 4a of the lead 4 as compared with the cases of FIGS. For this reason, the width | variety or planar dimension of the lead | read | reed 4 can be made comparatively small, and the semiconductor device 1 can be reduced in size. Further, since it is possible to save the space of the flat region of the inner lead part (lead 4), multiple bonding can be performed even in a semiconductor device having a small flat region on the upper surface of the inner lead part (lead 4), such as a QFN package. It becomes possible.

また、本実施の形態では、上記のように、同じリード４に対して複数のボンディングワイヤ６ｅ，６ｆを接続する際に、各ワイヤボンディングで生じるツールマーク３１ｅ，３１ｆをほぼ一致させるが、若干ずれた場合でも、そのずれが小さければ上記のような効果を得ることは可能である。例えば、各ボンディングワイヤ６ｅ，６ｆの接合部３２ｅ，３２ｆが部分的に重なれば、有効である。各ツールマーク３１ｅ，３１ｆの中心位置のずれ（平面的なずれ）は、ボンディングワイヤ６の直径（例えば２５〜３０μｍ程度）以下であることが好ましく、ワイヤボンディング装置によるワイヤボンディング位置の制御の精度の範囲内（例えば１０μｍ程度以下）であればより好ましく、ツールマーク３１ｅ，３１ｆが実質的に一致すれば更に好ましい。これにより、上記のような効果（ボンディングワイヤの接続の信頼性向上や半導体装置の小型化など）を的確に得ることが可能になる。   Further, in the present embodiment, as described above, when a plurality of bonding wires 6e and 6f are connected to the same lead 4, the tool marks 31e and 31f generated in each wire bonding are substantially matched, but slightly shifted. Even if the deviation is small, it is possible to obtain the above effects. For example, it is effective if the bonding portions 32e and 32f of the bonding wires 6e and 6f partially overlap. The displacement (planar displacement) of the center positions of the tool marks 31e and 31f is preferably equal to or less than the diameter of the bonding wire 6 (for example, about 25 to 30 μm), and the accuracy of control of the wire bonding position by the wire bonding apparatus is improved. It is more preferable if it is within the range (for example, about 10 μm or less), and it is more preferable if the tool marks 31e and 31f substantially coincide. As a result, the above-described effects (such as improved bonding wire connection reliability and miniaturization of the semiconductor device) can be accurately obtained.

また、図１５〜図１７では、それぞれ半導体チップ３の電極３ａに一端が接続された２本のボンディングワイヤ６ｅ，６ｆの他端が、同じ（一つの）リード４に接続（いわゆるダブルボンディング）されているが、一つのリード４に接続されるボンディングワイヤ６の数はこれに限定されるものではなく、必要に応じて任意の数のボンディングワイヤ６を一つのリード４に対して接続することができる。例えば３本以上のボンディングワイヤ６を同じ（一つの）リード４に接続する場合でも、それらのボンディングワイヤ６のツールマークが互いにほぼ重なる（一致する）ようにし、各ボンディングワイヤ６の接合部が積み重なるように、各ボンディングワイヤ６のリード４への接続（ワイヤボンディング）を行う。   15 to 17, the other ends of the two bonding wires 6e and 6f, each having one end connected to the electrode 3a of the semiconductor chip 3, are connected to the same (one) lead 4 (so-called double bonding). However, the number of bonding wires 6 connected to one lead 4 is not limited to this, and an arbitrary number of bonding wires 6 can be connected to one lead 4 as required. it can. For example, even when three or more bonding wires 6 are connected to the same (one) lead 4, the tool marks of the bonding wires 6 are substantially overlapped (matched) with each other, and the joint portions of the bonding wires 6 are stacked. As described above, each bonding wire 6 is connected to the lead 4 (wire bonding).

本実施の形態では、半導体チップ３の複数の電極３ａと複数のリード４とを複数のボンディングワイヤ６を介して電気的に接続するが、あるリード４に対して複数のボンディングワイヤ６を接続する際に、そのリードに生じ得るツールマークが平面的に重なる（一致する）ようにする。ツールマークが重なるようにしボンディングワイヤ６の接合部（圧着部）を積み重ねていくので、ワイヤボンディングに要するリード４の上面の平坦部面積は、そのリードに接続されるボンディングワイヤ６の数に影響されない。このため、リード４の平坦部面積が狭い場合であっても、多重ボンディングが可能になる。   In the present embodiment, the plurality of electrodes 3 a of the semiconductor chip 3 and the plurality of leads 4 are electrically connected via the plurality of bonding wires 6, but the plurality of bonding wires 6 are connected to a certain lead 4. At this time, tool marks that may be generated on the leads are overlapped (matched) in a plane. Since the bonding portions (crimping portions) of the bonding wires 6 are stacked so that the tool marks overlap, the flat portion area of the upper surface of the lead 4 required for wire bonding is not affected by the number of bonding wires 6 connected to the leads. . For this reason, even when the flat part area of the lead 4 is narrow, multiple bonding is possible.

また、本実施の形態は、比較的幅が狭く長さが短いリードを用いるＱＦＮパッケージ形態の半導体装置に適用すれば特に有効であるが、ＱＦＰ（Quad Flat Package、Quad Flat gull wing leaded Package）形態の半導体装置などに適用しても効果がある。   The present embodiment is particularly effective when applied to a semiconductor device of a QFN package type using a lead having a relatively small width and a short length, but a QFP (Quad Flat Package, Quad Flat Gull Wing Leaded Package) type. The present invention is also effective when applied to such semiconductor devices.

（実施の形態２）
図１８は、本発明の他の実施の形態におけるワイヤボンディング（リード４に対するボンディングワイヤ６の接続工程）の説明図であり、上記実施の形態１における図１７に対応する。 (Embodiment 2)
FIG. 18 is an explanatory diagram of wire bonding (a step of connecting the bonding wire 6 to the lead 4) in another embodiment of the present invention, and corresponds to FIG. 17 in the first embodiment.

本実施の形態は、半導体装置の構造および半導体装置の製造工程のうち、ワイヤボンディング（リード４に対するボンディングワイヤ６の接続工程および接続構造）以外については上記実施の形態１と同様であるので、ここではその説明を省略する。   The present embodiment is the same as the first embodiment except for the wire bonding (the bonding process of the bonding wire 6 to the lead 4 and the connection structure) in the structure of the semiconductor device and the manufacturing process of the semiconductor device. Then, the explanation is omitted.

本実施の形態においても、上記実施の形態１と同様に、半導体チップ３の複数の電極３ａと複数のリード４とを複数のボンディングワイヤ６を介して電気的に接続するが、あるリード４に対して複数のボンディングワイヤ６を接続する。図１８の例では、同じ（一つの）リード４に対して２本のボンディングワイヤ６ｅ，６ｆを接続する。本実施の形態では、ボンディングワイヤ６ｅの接合部３２ｅとボンディングワイヤ６ｆの接合部３２ｆ間に金（Ａｕ）ボール（金を含む部材）４１を介在させる。   Also in the present embodiment, as in the first embodiment, the plurality of electrodes 3a of the semiconductor chip 3 and the plurality of leads 4 are electrically connected through the plurality of bonding wires 6, A plurality of bonding wires 6 are connected to it. In the example of FIG. 18, two bonding wires 6 e and 6 f are connected to the same (one) lead 4. In the present embodiment, a gold (Au) ball (a member including gold) 41 is interposed between the bonding portion 32e of the bonding wire 6e and the bonding portion 32f of the bonding wire 6f.

本実施の形態では、上記実施の形態１における図８〜図１１のようにしてリード４にボンディングワイヤ６ｅを接続（接合）した後、リード４の上面４ａにおけるボンディングワイヤ６ｅの接合部３２ｅ上に金ボール（圧着金ボール）４１を例えば圧着などにより形成する。金ボール４１は、ボンディングワイヤ６（ボンディングワイヤ６ｅ，６ｆ）と同じ材料（ここでは金（Ａｕ））からなることが好ましい。   In the present embodiment, the bonding wire 6e is connected (bonded) to the lead 4 as shown in FIGS. 8 to 11 in the first embodiment, and then on the bonding portion 32e of the bonding wire 6e on the upper surface 4a of the lead 4. A gold ball (compression gold ball) 41 is formed by, for example, pressure bonding. The gold ball 41 is preferably made of the same material (here, gold (Au)) as the bonding wire 6 (bonding wires 6e and 6f).

金ボール４１は、例えば、放電などによって先端に金球を形成した金線をワイヤボンディング装置のキャピラリ２２に保持し、ボンディングワイヤ６ｅが既に接続されたリード４上に金ボールを適切な荷重をもって接触させた後、キャピラリ２２を超音波振動させ、このときの荷重や印加された超音波によるエネルギーでボンディングワイヤ６ｅが接続されたリード４に金球を接着（接合）させ、金線を引きちぎってボンディングワイヤ６ａが接続されたリード４に残存する金球からなる金ボール４１を形成することができる。   For example, the gold ball 41 holds a gold wire having a gold ball formed at the tip thereof by discharge or the like in the capillary 22 of the wire bonding apparatus, and contacts the gold ball with an appropriate load on the lead 4 to which the bonding wire 6e is already connected. After that, the capillary 22 is ultrasonically vibrated, and a gold ball is bonded (bonded) to the lead 4 to which the bonding wire 6e is connected by the load and energy of the applied ultrasonic wave at this time, and the gold wire is torn and bonded. A gold ball 41 made of a gold ball remaining on the lead 4 to which the wire 6a is connected can be formed.

リード４の上面４ａにおけるボンディングワイヤ６ｅの接合部３２ｅ上に金ボール４１を形成した後、このリード４上にボンディングワイヤ６ｆを図８〜図１１のようにして接続する。この際、リード４の上面４ａのボンディングワイヤ６ｅの接合部３２ｅ上に金ボール４１を介してボンディングワイヤ６ｆを接合する。また、上記実施の形態１と同様に、リード４の上面４ａに生じるツールマークが平面的に重なる（一致する）ようにワイヤボンディングを行うことで、リード４の上面４ａのボンディングワイヤ６ｅ，６ｆの接合部（圧着部、ボンディング部）３２ｅ，３２ｆが重なるようにしている。このため、ボンディングワイヤ６ｅの接合部３２ｅとボンディングワイヤ６ｆの接合部３２ｆとの間には、ボンディングワイヤ６ｆの接合時に押しつぶされた金ボール４１が介在し、ボンディングワイヤ６ｅの接合部３２ｅ、押しつぶされた金ボール４１およびボンディングワイヤ６ｆの接合部３２ｆが上下方向に積み重なることになる。   After the gold ball 41 is formed on the bonding portion 32e of the bonding wire 6e on the upper surface 4a of the lead 4, the bonding wire 6f is connected to the lead 4 as shown in FIGS. At this time, the bonding wire 6 f is bonded via the gold ball 41 on the bonding portion 32 e of the bonding wire 6 e on the upper surface 4 a of the lead 4. Further, as in the first embodiment, wire bonding is performed so that tool marks generated on the upper surface 4a of the lead 4 overlap (coincide) with each other in plan view, whereby the bonding wires 6e and 6f on the upper surface 4a of the lead 4 are formed. The joining parts (crimping part, bonding part) 32e and 32f are made to overlap. For this reason, the gold ball 41 crushed when the bonding wire 6f is bonded is interposed between the bonding portion 32e of the bonding wire 6e and the bonding portion 32f of the bonding wire 6f, and the bonding portion 32e of the bonding wire 6e is crushed. The gold ball 41 and the bonding portion 32f of the bonding wire 6f are stacked in the vertical direction.

本実施の形態では、このように、リード４にボンディングワイヤ６ｅを接続した後、金ボール４１を形成し、この金ボール４１を介してボンディングワイヤ６ｆをリード４の上面４ａ（またはボンディングワイヤ６ｆの接合部３２ｆ）上に接合する。ボンディングワイヤ６ｅの接合部３２ｅとボンディングワイヤ６ｆの接合部３２ｆとの間の金ボール４１は、緩衝材（クッション）として機能することができる。このため、ボンディングワイヤ６ｆの接続時に、その下に位置するボンディングワイヤ６ｅ（の接合部３２ｅ）とリード４との間の接合がダメージを受けるのを抑制または防止することができる。これにより、ボンディングワイヤ６ｅの接続強度をより向上することができる。また、金ボール４１を設けたことにより、ボンディングワイヤ６ｆもリード４に、より確実に接続することができ、ボンディングワイヤ６ｆの接続強度をより向上することができる。従って、ボンディングワイヤ６ｅ，６ｆの接続強度や接続の信頼性をより向上することができる。これにより、半導体装置の信頼性をより向上し、製造歩留りをより向上することが可能になる。   In the present embodiment, after the bonding wire 6e is connected to the lead 4 as described above, the gold ball 41 is formed, and the bonding wire 6f is connected to the upper surface 4a of the lead 4 (or the bonding wire 6f) via the gold ball 41. Join on the joint 32f). The gold ball 41 between the bonding portion 32e of the bonding wire 6e and the bonding portion 32f of the bonding wire 6f can function as a cushioning material (cushion). For this reason, when the bonding wire 6f is connected, it is possible to suppress or prevent the bonding between the bonding wire 6e (the bonding portion 32e thereof) and the lead 4 from being damaged. Thereby, the connection strength of the bonding wire 6e can be further improved. Further, by providing the gold ball 41, the bonding wire 6f can be more reliably connected to the lead 4, and the connection strength of the bonding wire 6f can be further improved. Accordingly, the connection strength and connection reliability of the bonding wires 6e and 6f can be further improved. As a result, the reliability of the semiconductor device can be further improved and the manufacturing yield can be further improved.

また、ボンディングワイヤ６ｆを金ボール４１を介して接続したことにより、図１８に示されるように、ボンディングワイヤ６ｅ，６ｆ間の上下方向（リード４の上面４ａに垂直な方向）の間隔（距離）を金ボール４１がない場合に比べて相対的に大きくすることができる。このため、ボンディングワイヤ６ｅとボンディングワイヤ６ｆとが、金ボール４１を介した接続部以外の途中の領域で互いに接触することを防止することができる。ボンディングワイヤ６ｅ，６ｆ間の接触を防止することができるので、半導体装置の信頼性をより向上することができる。   Further, since the bonding wire 6f is connected via the gold ball 41, as shown in FIG. 18, the distance (distance) between the bonding wires 6e and 6f in the vertical direction (direction perpendicular to the upper surface 4a of the lead 4). Can be made relatively large as compared with the case without the gold ball 41. For this reason, it is possible to prevent the bonding wire 6e and the bonding wire 6f from contacting each other in a region in the middle other than the connection portion via the gold ball 41. Since the contact between the bonding wires 6e and 6f can be prevented, the reliability of the semiconductor device can be further improved.

また、本実施の形態においても、上記実施の形態１と同様に、ツールマーク同士がほぼ重なるように複数のボンディングワイヤ６ｅ，６ｆを同じ（一つの）リード４に接続することができるので、リード４の上面４ａにおいてワイヤボンディングに要する領域（面積）を小さくすることができる。このため、リード４の幅または平面寸法を比較的小さくすることができ、半導体装置１を小型化することができる。また、インナリード部（リード４）の平坦領域の省スペース化が可能になるので、例えばＱＦＮパッケージのようにインナリード部（リード４）の上面の平坦領域が小さい半導体装置においても、多重ボンディングが可能になる。   Also in the present embodiment, as in the first embodiment, since a plurality of bonding wires 6e and 6f can be connected to the same (one) lead 4 so that the tool marks substantially overlap each other, The area (area) required for wire bonding on the upper surface 4a of 4 can be reduced. For this reason, the width | variety or planar dimension of the lead | read | reed 4 can be made comparatively small, and the semiconductor device 1 can be reduced in size. Further, since it is possible to save the space of the flat region of the inner lead part (lead 4), multiple bonding can be performed even in a semiconductor device having a small flat region on the upper surface of the inner lead part (lead 4), such as a QFN package. It becomes possible.

また、本実施の形態は、比較的幅が狭く長さが短いリードを用いるＱＦＮパッケージ形態の半導体装置に適用すれば特に有効であるが、ＱＦＰ形態の半導体装置などに適用しても効果がある。   This embodiment is particularly effective when applied to a QFN package type semiconductor device using a lead having a relatively small width and a short length, but is also effective when applied to a QFP type semiconductor device or the like. .

以上、本発明者によってなされた発明をその実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

前記実施の形態では、ＱＦＮ（Quad Flat Non leaded package）形態の半導体装置に適用した場合について説明したが、本発明は、これに限定されるものではなく、ＱＦＰ（Quad Flat Package、Quad Flat gull wing leaded Package）など、半導体チップの複数の電極と複数のリード部とを複数のワイヤを介して電気的に接続した種々の半導体パッケージ形態の半導体装置に適用することができる。   In the above-described embodiment, the case where the present invention is applied to a semiconductor device of QFN (Quad Flat Non leaded package) type has been described, but the present invention is not limited to this, and QFP (Quad Flat Package, Quad Flat gull wing) The present invention can be applied to various semiconductor package semiconductor devices in which a plurality of electrodes of a semiconductor chip and a plurality of lead portions are electrically connected via a plurality of wires, such as a leaded package.

本発明は、半導体パッケージ形態の半導体装置に適用して有効である。   The present invention is effective when applied to a semiconductor device in the form of a semiconductor package.

本発明の一実施の形態である半導体装置の平面透視図である。It is a plane perspective view of the semiconductor device which is one embodiment of the present invention. 図１の半導体装置の断面図である。FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1. 図１の半導体装置の底面図である。FIG. 2 is a bottom view of the semiconductor device of FIG. 1. 本発明の一実施の形態である半導体装置の製造工程中の断面図である。It is sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. 図４に続く半導体装置の製造工程中の断面図である。FIG. 5 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 図５に続く半導体装置の製造工程中の断面図である。FIG. 6 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; 図６に続く半導体装置の製造工程中の断面図である。FIG. 7 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; ワイヤボンディング工程の説明図である。It is explanatory drawing of a wire bonding process. 図８に続くワイヤボンディング工程の説明図である。It is explanatory drawing of the wire bonding process following FIG. 図９に続くワイヤボンディング工程の説明図である。It is explanatory drawing of the wire bonding process following FIG. 図１０に続くワイヤボンディング工程の説明図である。It is explanatory drawing of the wire bonding process following FIG. リードの上面に金線を接合した状態を示す説明図である。It is explanatory drawing which shows the state which joined the gold wire to the upper surface of the lead | read | reed. 同じリードに対して複数のボンディングワイヤを接続した場合に生じ得る問題点の説明図である。It is explanatory drawing of the problem which may arise when a some bonding wire is connected with respect to the same lead. 同じリードに対して複数のボンディングワイヤを接続した場合に生じ得る他の問題点の説明図である。It is explanatory drawing of the other problem which may arise when a some bonding wire is connected with respect to the same lead. ワイヤボンディングの説明図である。It is explanatory drawing of wire bonding. ワイヤボンディングの説明図である。It is explanatory drawing of wire bonding. ワイヤボンディングの説明図である。It is explanatory drawing of wire bonding. 本発明の他の実施の形態におけるワイヤボンディングの説明図である。It is explanatory drawing of the wire bonding in other embodiment of this invention.

符号の説明Explanation of symbols

１ 半導体装置
２ 封止樹脂部
２ａ 裏面
２ｂ 切断面
３ 半導体チップ
３ａ 電極
４ リード
４ａ 上面
４ｂ 下部露出面
４ｃ 切断面
４ｄ リード
４ｅ リード
４ｆ リード
６ ボンディングワイヤ
６ａ ボンディングワイヤ
６ｂ ボンディングワイヤ
６ｃ ボンディングワイヤ
６ｄ ボンディングワイヤ
６ｅ ボンディングワイヤ
６ｆ ボンディングワイヤ
７ タブ
８ 吊りリード
８ｂ 下部露出面
８ｃ 切断面
１１ リードフレーム
１２ モールドライン
１３ フレーム枠
２１ａ 金球
２１ 金線
２１ｂ 接合部
２２ キャピラリ
２３ ワイヤクランパ
３１ ツールマーク
３１ａ ツールマーク
３１ｂ ツールマーク
３１ｃ ツールマーク
３１ｄ ツールマーク
３１ｅ ツールマーク
３１ｆ ツールマーク
３２ 接合部
３２ａ 接合部
３２ｂ 接合部
３２ｃ 接合部
３２ｄ 接合部
３２ｅ 接合部
３２ｆ 接合部
３４ リード
３４ａ 上面
３５ リード
３５ａ 上面
３６ めっき層
４１ 金ボール DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Sealing resin part 2a Back surface 2b Cut surface 3 Semiconductor chip 3a Electrode 4 Lead 4a Upper surface 4b Lower exposed surface 4c Cut surface 4d Lead 4e Lead 4f Lead 6 Bonding wire 6a Bonding wire 6b Bonding wire 6c Bonding wire 6d Bonding wire 6e Bonding wire 6f Bonding wire 7 Tab 8 Suspended lead 8b Lower exposed surface 8c Cut surface 11 Lead frame 12 Mold line 13 Frame frame 21a Gold ball 21 Gold wire 21b Joint 22 Capillary 23 Wire clamper 31 Tool mark 31a Tool mark 31b Tool mark 31c Tool mark 31d Tool mark 31e Tool mark 31f Tool mark 32 Joining part 32a Joining part 32b Joining part 32c Joining part 32d Joining part 32e Joining 32f junction 34 leads 34a upper surface 35 leads 35a upper surface 36 plating layer 41 gold ball

Claims (5)

複数の電極を有する半導体チップと、
導電体により形成された複数のリード部と、
前記複数のリード部と前記半導体チップの前記複数の電極とを電気的に接続する複数のワイヤと、
前記半導体チップ、前記複数のワイヤおよび前記複数のリード部を封止する封止樹脂部と、
を具備し、
前記複数のリード部のうちの第１リード部に前記複数のワイヤのうちの複数の第１ワイヤが接続され、前記第１リード部における前記各第１ワイヤの接合部が重なっていることを特徴とする半導体装置。 A semiconductor chip having a plurality of electrodes;
A plurality of lead portions formed of a conductor;
A plurality of wires that electrically connect the plurality of lead portions and the plurality of electrodes of the semiconductor chip;
A sealing resin portion for sealing the semiconductor chip, the plurality of wires, and the plurality of lead portions;
Comprising
A plurality of first wires of the plurality of wires are connected to a first lead portion of the plurality of lead portions, and a joint portion of the first wires in the first lead portion overlaps. A semiconductor device. （ａ）複数の電極を有する半導体チップを準備する工程、
（ｂ）導電体からなる複数のリード部と前記半導体チップの前記複数の電極とを複数のワイヤを介して電気的に接続し、前記複数のリード部のうちの第１リード部に前記複数のワイヤのうちの複数の第１ワイヤを接続する工程、
を有し、
前記（ｂ）工程では、前記第１リード部における前記各第１ワイヤの接合部が重なるように、前記複数の第１ワイヤを前記第１リード部に接続することを特徴とする半導体装置の製造方法。 (A) preparing a semiconductor chip having a plurality of electrodes;
(B) A plurality of lead portions made of a conductor and the plurality of electrodes of the semiconductor chip are electrically connected via a plurality of wires, and the plurality of lead portions are connected to a first lead portion of the plurality of lead portions. Connecting a plurality of first wires of the wires;
Have
In the step (b), the plurality of first wires are connected to the first lead portion so that the joint portions of the first wires in the first lead portion overlap each other. Method. （ａ）複数の電極を有する半導体チップを準備する工程、
（ｂ）導電体からなる複数のリード部と前記半導体チップの前記複数の電極とを複数のワイヤを介して電気的に接続し、前記複数のリード部のうちの第１リード部に前記複数のワイヤのうちの複数の第１ワイヤを接続する工程、
を有し、
前記（ｂ）工程では、前記各第１ワイヤを前記第１リード部に接続する際のツールマークが重なるように、前記複数の第１ワイヤを前記第１リード部に接続することを特徴とする半導体装置の製造方法。 (A) preparing a semiconductor chip having a plurality of electrodes;
(B) A plurality of lead portions made of a conductor and the plurality of electrodes of the semiconductor chip are electrically connected via a plurality of wires, and the plurality of lead portions are connected to a first lead portion of the plurality of lead portions. Connecting a plurality of first wires of the wires;
Have
In the step (b), the plurality of first wires are connected to the first lead portion so that tool marks for connecting the first wires to the first lead portion overlap each other. A method for manufacturing a semiconductor device. （ａ）複数の電極を有する半導体チップを準備する工程、
（ｂ）導電体からなる複数のリード部と前記半導体チップの前記複数の電極とを複数のワイヤを介して電気的に接続し、前記複数のリード部のうちの第１リード部に前記複数のワイヤのうちの複数の第１ワイヤを接続する工程、
を有し、
前記（ｂ）工程では、前記第１リード部における前記各第１ワイヤの接合部が間に金を含む部材を介在して重なるように、前記複数の第１ワイヤを前記第１リード部に接続することを特徴とする半導体装置の製造方法。 (A) preparing a semiconductor chip having a plurality of electrodes;
(B) A plurality of lead portions made of a conductor and the plurality of electrodes of the semiconductor chip are electrically connected via a plurality of wires, and the plurality of lead portions are connected to a first lead portion of the plurality of lead portions. Connecting a plurality of first wires of the wires;
Have
In the step (b), the plurality of first wires are connected to the first lead portion so that the joint portions of the first wires in the first lead portion overlap with a member including gold interposed therebetween. A method of manufacturing a semiconductor device. （ａ）複数の電極を有する半導体チップを準備する工程、
（ｂ）導電体からなる複数のリード部と前記半導体チップの前記複数の電極とを複数のワイヤを介して電気的に接続し、前記複数のリード部のうちの第１リード部に前記複数のワイヤのうちの第１および第２ワイヤを接続する工程、
を有し、
前記（ｂ）工程では、前記第１ワイヤを前記第１リード部に接続した後、前記第１リード部の前記第１ワイヤの接合部上に金を含む部材を形成し、前記金を含む部材を介して前記第２ワイヤを前記第１リード部に接続することを特徴とする半導体装置の製造方法。

(A) preparing a semiconductor chip having a plurality of electrodes;
(B) A plurality of lead portions made of a conductor and the plurality of electrodes of the semiconductor chip are electrically connected via a plurality of wires, and the plurality of lead portions are connected to a first lead portion of the plurality of lead portions. Connecting the first and second of the wires;
Have
In the step (b), after the first wire is connected to the first lead portion, a member including gold is formed on a joint portion of the first wire of the first lead portion, and the member including the gold A method of manufacturing a semiconductor device, wherein the second wire is connected to the first lead portion via a wire.

JP2003383785A 2003-11-13 2003-11-13 Semiconductor device and its manufacturing method Pending JP2005150294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003383785A JP2005150294A (en) 2003-11-13 2003-11-13 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003383785A JP2005150294A (en) 2003-11-13 2003-11-13 Semiconductor device and its manufacturing method

Publications (2)

Publication Number Publication Date
JP2005150294A true JP2005150294A (en) 2005-06-09
JP2005150294A5 JP2005150294A5 (en) 2006-12-21

Family

ID=34692407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003383785A Pending JP2005150294A (en) 2003-11-13 2003-11-13 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2005150294A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010024442A1 (en) * 2008-08-29 2010-03-04 京セラ株式会社 Circuit board, image forming device, thermal head and image sensor
CN106229307A (en) * 2016-08-01 2016-12-14 长电科技（宿迁）有限公司 The Welding Structure of aluminum steel pad surface secondary load and process thereof
EP2603929A4 (en) * 2010-08-10 2017-05-03 Cypress Semiconductor Corporation Stitch bump stacking design for overall package size reduction for multiple stack

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010024442A1 (en) * 2008-08-29 2010-03-04 京セラ株式会社 Circuit board, image forming device, thermal head and image sensor
US8525040B2 (en) 2008-08-29 2013-09-03 Kyocera Corporation Circuit board and its wire bonding structure
EP2603929A4 (en) * 2010-08-10 2017-05-03 Cypress Semiconductor Corporation Stitch bump stacking design for overall package size reduction for multiple stack
CN106229307A (en) * 2016-08-01 2016-12-14 长电科技（宿迁）有限公司 The Welding Structure of aluminum steel pad surface secondary load and process thereof

Similar Documents

Publication Publication Date Title
JP3205235B2 (en) Lead frame, resin-encapsulated semiconductor device, method of manufacturing the same, and mold for manufacturing semiconductor device used in the manufacturing method
US8222720B2 (en) Semiconductor device and manufacturing method thereof
KR0149798B1 (en) Semiconductor device and method of manufacture and lead frame
JP3736516B2 (en) Lead frame and manufacturing method thereof, resin-encapsulated semiconductor device and manufacturing method thereof
JP5001872B2 (en) Semiconductor device
US8421199B2 (en) Semiconductor package structure
JP2006318996A (en) Lead frame and resin sealed semiconductor device
JP2014220439A (en) Method of manufacturing semiconductor device and semiconductor device
JP2008277751A (en) Method of manufacturing semiconductor device, and semiconductor device
JP3851845B2 (en) Semiconductor device
TW381326B (en) Semiconductor device and lead frame therefor
US20050110121A1 (en) Lead frame, resin-encapsulated semiconductor device, and method of producing the same
JP4203925B2 (en) Resin-sealed semiconductor device
JP6909630B2 (en) Semiconductor device
JP2005150294A (en) Semiconductor device and its manufacturing method
JP2005109007A (en) Semiconductor device and its manufacturing method
JP2003007954A (en) Manufacturing method for resin-sealing semiconductor device
JP2010056325A (en) Semiconductor device and method of manufacturing same
JPH08279575A (en) Semiconductor package
JP2001015669A (en) Lead frame, resin sealed semiconductor device using the same, and its manufacture
JP2002164496A (en) Semiconductor device and method for manufacturing the same
JP2005142284A (en) Semiconductor device
JP3434633B2 (en) Resin-sealed semiconductor device
KR100357876B1 (en) semiconductor package and its manufacturing method
JP2003007953A (en) Resin-sealing semiconductor device and manufacturing method therefor

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061106

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061106

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081015

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090901

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100105