JP2008277751A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Method of manufacturing semiconductor device, and semiconductor device Download PDF

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Publication number
JP2008277751A
JP2008277751A JP2008029858A JP2008029858A JP2008277751A JP 2008277751 A JP2008277751 A JP 2008277751A JP 2008029858 A JP2008029858 A JP 2008029858A JP 2008029858 A JP2008029858 A JP 2008029858A JP 2008277751 A JP2008277751 A JP 2008277751A
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Japan
Prior art keywords
semiconductor device
bonding
wire
ball
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2008029858A
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Japanese (ja)
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JP2008277751A5 (en
Inventor
Akira Koga
彰 小賀
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Panasonic Corp
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Panasonic Corp
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Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to JP2008029858A priority Critical patent/JP2008277751A/en
Priority to US12/060,484 priority patent/US20080246129A1/en
Publication of JP2008277751A publication Critical patent/JP2008277751A/en
Priority to US12/929,160 priority patent/US20110151622A1/en
Publication of JP2008277751A5 publication Critical patent/JP2008277751A5/ja
Withdrawn legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can inhibit an increase in an electrode area in a structure where multiple wires are connected to the same electrode on a semiconductor chip. <P>SOLUTION: Firstly, as shown in Figs.3(a) to (d), ball bonding is performed on an electrode 3 on a semiconductor chip 1 to form a connection portion 7a, and then, as shown in Figs.3(e) to (g), wedge bonding is performed on an inner lead 4a. Subsequently, as shown in Figs.3(h) to (i), ball bonding is performed to press-bond a ball 11b onto the connection portion 7a from immediately above so as to form a connection portion 7b, and then, as shown in Figs.3(j) to (l), wedge bonding is performed on the inner lead 4a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置の製造方法、および半導体装置に関し、特にリードフレーム／配線基板を用いた半導体チップのパッケージ技術に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor chip packaging technique using a lead frame / wiring substrate.

近年、半導体装置の形態として、リードフレームを用いたＱＦＰ（クワッド・フラット・パッケージ）などが広く用いられてきている。以下、図面を用いて、従来の一般的なＱＦＰ型半導体装置について説明する。   In recent years, QFP (quad flat package) using a lead frame has been widely used as a form of a semiconductor device. Hereinafter, a conventional general QFP type semiconductor device will be described with reference to the drawings.

図１７は従来の一般的なＱＦＰ型半導体装置の断面図、図１８は同半導体装置のワイヤボンディング部分の内部構造図である。このＱＦＰ型半導体装置は、図１７、図１８に示すように、集積回路が形成された半導体チップ１がリードフレームのダイパッド部２に搭載されている。また、ダイパッド部２の周辺には放射状にリードフレームのリード４が配置されており、インナーリード４ａの先端がダイパッド部２に対して対向している。また、半導体チップ１の表面に形成された電極３とインナーリード４ａとがワイヤ５で接続されている。また、半導体チップ１、ワイヤ５、インナーリード４ａが一括して樹脂封止体６により樹脂封止され、インナーリード４ａに連続したリードフレームのアウターリード４ｂが樹脂封止体６の外部でガルウィング型に曲げ成形されている。また、図１８に示すダイパッドサポート２４は、ダイパッド部２をリードフレームに保持する部材である（例えば、非特許文献１参照。）。   FIG. 17 is a cross-sectional view of a conventional general QFP semiconductor device, and FIG. 18 is an internal structure diagram of a wire bonding portion of the semiconductor device. In this QFP type semiconductor device, as shown in FIGS. 17 and 18, a semiconductor chip 1 on which an integrated circuit is formed is mounted on a die pad portion 2 of a lead frame. Further, leads 4 of the lead frame are arranged radially around the die pad portion 2, and the tips of the inner leads 4 a are opposed to the die pad portion 2. In addition, the electrode 3 formed on the surface of the semiconductor chip 1 and the inner lead 4 a are connected by a wire 5. Further, the semiconductor chip 1, the wires 5, and the inner leads 4 a are collectively sealed with the resin sealing body 6, and the outer leads 4 b of the lead frame continuous to the inner leads 4 a are gull-wing type outside the resin sealing body 6. It is bent and molded. Further, the die pad support 24 shown in FIG. 18 is a member that holds the die pad portion 2 on the lead frame (see, for example, Non-Patent Document 1).

続いて、従来の一般的なＱＦＰ型半導体装置の製造方法について説明する。
まず、金属板で形成されたリードフレームのダイパッド部２に半導体チップ１を搭載する（ダイボンド工程）。なお、リードフレームは、複数個の半導体装置を同時に、あるいは順次形成するために、各半導体装置に対応する矩形のパターンをフレーム枠で連結して複数個、同一平面上の左右方向ないし上下方向に配列したものである。各パターンは、ダイパッド部２を中央に配置し、複数本のリード４の外端部をフレーム枠に接続し、ダイパッド部２をダイパッドサポート２４によりフレーム枠に保持する構造である。 Next, a conventional general QFP type semiconductor device manufacturing method will be described.
First, the semiconductor chip 1 is mounted on the die pad portion 2 of the lead frame formed of a metal plate (die bonding step). In order to form a plurality of semiconductor devices simultaneously or sequentially, a lead frame is formed by connecting a plurality of rectangular patterns corresponding to each semiconductor device with a frame frame in a horizontal direction or a vertical direction on the same plane. It is an arrangement. Each pattern has a structure in which the die pad portion 2 is arranged at the center, the outer end portions of the plurality of leads 4 are connected to the frame frame, and the die pad portion 2 is held on the frame frame by the die pad support 24.

次に、半導体チップ１の表面に形成された電極３と、ダイパッド部２の周囲に配置されたインナーリード４ａとをワイヤ５で接続する（ワイヤボンディング工程）。次に、半導体チップ１、ダイパッド部２、ワイヤ５、インナーリード４ａを一括して封止樹脂で樹脂封止して、樹脂封止体６を形成する（樹脂封止工程）。   Next, the electrode 3 formed on the surface of the semiconductor chip 1 and the inner lead 4a disposed around the die pad portion 2 are connected by the wire 5 (wire bonding step). Next, the semiconductor chip 1, the die pad portion 2, the wire 5, and the inner lead 4 a are collectively sealed with a sealing resin to form a resin sealing body 6 (resin sealing step).

最後に、アウターリード４ｂを所定の長さに合わせてフレーム枠から切断して個片に分離するとともに、アウターリード４ｂを所定の形状に加工して、半導体装置の完成品を得る。   Finally, the outer lead 4b is cut from the frame frame to a predetermined length and separated into individual pieces, and the outer lead 4b is processed into a predetermined shape to obtain a finished semiconductor device.

また、ワイヤボンディング方法としては、（１）キャピラリの先端から突出したワイヤの先端に放電によりボールを形成し、（２）熱と超音波を与えながら、そのボールをキャピラリで一方の接続点に押し付けて接続し（ボールボンディング）、（３）キャピラリからワイヤを引き出しながら他方の接続点に移動し、（４）熱と超音波を与えながらキャピラリの先端部でワイヤを他方の接続点にこすり付けて接続する（ウェッジボンディング）、超音波併用熱圧着ボンディング方式が現在の主流であり、一般的には半導体チップの電極側においてボールボンディングを行う。   The wire bonding method is as follows: (1) a ball is formed by discharge at the tip of the wire protruding from the tip of the capillary, and (2) the ball is pressed against one connection point with the capillary while applying heat and ultrasonic waves. (3) Move to the other connection point while pulling out the wire from the capillary, and (4) Rub the wire to the other connection point at the tip of the capillary while applying heat and ultrasonic waves. The connection method (wedge bonding) and the thermocompression bonding method using ultrasonic waves are the mainstream at present, and ball bonding is generally performed on the electrode side of the semiconductor chip.

以上のように構成されたＱＦＰ型半導体装置において、近年、集積回路の高集積化、高密度化に伴い、多ピン化およびリードの狭ピッチ化が進んできた。しかしながら、多ピン化およびリードの狭ピッチ化が進んできたといってもＱＦＰ型半導体装置の外形やピン数は業界で標準化されている。そこで、ＱＦＰ型半導体装置では、限られたピン数の中で高集積化された半導体チップを保持すべく、電源電極や接地電極などの共通化できる電極をまとめて同一のリードに接続している。図１９は同一のインナーリード４ａに複数の電極３からのワイヤ５を接続した状態を示す模式図である。図１９（ａ）では同一のインナーリード４ａに２本のワイヤ５を接続し、図１９（ｂ）では同一のインナーリード４ａに３本のワイヤ５を接続している。
香山 晋、成瀬 邦彦 監修、「実践講座 ＶＬＳＩパッケージング技術（下）」、株式会社日経ＢＰ、１９９３年５月３１日発行、Ｐ１６５〜Ｐ１７０ In the QFP type semiconductor device configured as described above, in recent years, the number of pins and the pitch of leads have been reduced along with the higher integration and higher density of integrated circuits. However, even if the number of pins and the pitch of leads have been reduced, the external shape and the number of pins of the QFP type semiconductor device are standardized in the industry. Therefore, in the QFP type semiconductor device, in order to hold a highly integrated semiconductor chip with a limited number of pins, common electrodes such as a power supply electrode and a ground electrode are collectively connected to the same lead. . FIG. 19 is a schematic view showing a state in which wires 5 from a plurality of electrodes 3 are connected to the same inner lead 4a. In FIG. 19A, two wires 5 are connected to the same inner lead 4a, and in FIG. 19B, three wires 5 are connected to the same inner lead 4a.
Supervised by Satoshi Kayama and Kunihiko Naruse, “Practical Course VLSI Packaging Technology (below)”, Nikkei Business Publications, Inc., May 31, 1993, P165-P170

以上のように、従来から、ＱＦＰ型半導体装置においては、電源電極や接地電極などの共通化できる電極をまとめて同一のリードに接続していた。一方、半導体チップ１個当たりの回路規模が飛躍的に大きくなったため、電源電極および接地電極への安定した電流供給を確保するための配線が必要となってきた。反面、半導体組立技術の進歩と低コスト化の要求から、半導体装置の配線材料であるＡｕワイヤに代表される金属ワイヤは細線化が図られてきた。これらの相反する２つの課題に対し、1個の電極と１本のインナーリードとの接続に複数本のワイヤを使用することが行われている。   As described above, conventionally, in the QFP type semiconductor device, common electrodes such as a power supply electrode and a ground electrode are collectively connected to the same lead. On the other hand, since the circuit scale per semiconductor chip has dramatically increased, wiring for securing a stable current supply to the power supply electrode and the ground electrode has become necessary. On the other hand, metal wires typified by Au wires, which are wiring materials for semiconductor devices, have been made thinner because of advances in semiconductor assembly technology and demands for cost reduction. For these two conflicting problems, the use of a plurality of wires for connecting one electrode and one inner lead has been performed.

しかしながら、通常、ワイヤの十分な接合を行うには一定以上の面積が必要になるため、複数本のワイヤを同一の電極に接続する場合、従来は、電極の面積を、複数本のワイヤをボールボンディングできる大きさにする必要があった。このことがチップ面積の縮小化を阻害していた。   However, since an area of a certain size or more is usually required for sufficient bonding of wires, when connecting a plurality of wires to the same electrode, conventionally, the area of the electrode is reduced to a number of wires. It was necessary to make it large enough for bonding. This hindered the reduction of the chip area.

また、リードフレームのリードや、ＢＧＡ(ボール・グリッド・アレイ)型半導体装置の配線基板の表層配線に、複数本のワイヤをボールボンディングにより接続する場合もあるが、この場合も同様に、リードまたは表層配線の面積を、複数本のワイヤをボールボンディングできる大きさにする必要があった。このことがパッケージ面積の縮小化を阻害していた。   In some cases, a plurality of wires are connected to the lead of the lead frame or the surface layer wiring of the wiring board of the BGA (Ball Grid Array) type semiconductor device by ball bonding. It was necessary to make the surface layer wiring area large enough to allow ball bonding of a plurality of wires. This hindered the reduction of the package area.

本発明は、上記問題点に鑑み、半導体チップ上の同一の電極又はリードフレームの同一のリードあるいは配線基板上の同一の表層配線に、複数本のワイヤを接続する構造において、電極面積またはパッケージ面積を抑制することができる半導体装置の製造方法、および半導体装置を提供することを目的とする。   In view of the above problems, the present invention provides a structure in which a plurality of wires are connected to the same electrode on a semiconductor chip, the same lead of a lead frame, or the same surface layer wiring on a wiring board. An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device capable of suppressing the above-described problem.

本発明の請求項１記載の半導体装置の製造方法は、ワイヤ供給装置から突出したワイヤの先端にボールを形成して、そのボールを半導体チップ上の電極に圧着するボールボンディングを行い、その後ワイヤ供給装置を移動させ、接続対象部材にウェッジボンディングを行う第１ボンディング工程と、ワイヤ供給装置から突出したワイヤの先端にボールを形成して、そのボールを、前記第１ボンディング工程においてボールボンディングを行った部分に直上から圧着するボールボンディングを行い、その後ワイヤ供給装置を移動させ、前記第１ボンディング工程における接続対象部材又はその接続対象部材とは異なる接続対象部材にウェッジボンディングを行う第２ボンディング工程と、を具備することを特徴とする。   According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a ball is formed at a tip of a wire protruding from a wire supply device, and the ball is bonded to an electrode on a semiconductor chip. A first bonding step of moving the device and performing wedge bonding on the connection target member, and forming a ball at the tip of the wire protruding from the wire supply device, and performing the ball bonding of the ball in the first bonding step A second bonding step in which ball bonding is performed to directly press onto the portion, and then the wire supply device is moved, and the bonding target member in the first bonding step or wedge bonding is performed on a connection target member different from the connection target member; It is characterized by comprising.

また、本発明の請求項２記載の半導体装置の製造方法は、請求項１記載の半導体装置の製造方法であって、前記第２ボンディング工程を２回以上繰り返し行い、前記電極に複数本のワイヤを接続させることを特徴とする。   A method for manufacturing a semiconductor device according to claim 2 of the present invention is the method for manufacturing a semiconductor device according to claim 1, wherein the second bonding step is repeated twice or more, and a plurality of wires are formed on the electrode. Are connected.

また、本発明の請求項３記載の半導体装置の製造方法は、請求項２記載の半導体装置の製造方法であって、繰り返し行う前記第２ボンディング工程に際し、前記第１ボンディング工程における接続対象部材に少なくとも１本のワイヤをウェッジボンディングにより接続させることを特徴とする。   According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the second aspect of the present invention, wherein the connection target member in the first bonding step is used when the second bonding step is repeatedly performed. At least one wire is connected by wedge bonding.

また、本発明の請求項４記載の半導体装置の製造方法は、請求項２記載の半導体装置の製造方法であって、繰り返し行う前記第２ボンディング工程に際し、前記第１ボンディング工程における接続対象部材とは異なる同一の接続対象部材に少なくとも２本のワイヤをウェッジボンディングにより接続させることを特徴とする。   According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second aspect of the present invention, wherein, in the second bonding step that is repeatedly performed, the connection target member in the first bonding step and Is characterized in that at least two wires are connected to different same connection target members by wedge bonding.

また、本発明の請求項５記載の半導体装置の製造方法は、請求項１記載の半導体装置の製造方法であって、ワイヤ供給装置から突出したワイヤの先端にボールを形成し、そのボールを、前記第１ボンディング工程ないし前記第２ボンディング工程においてウェッジボンディングを行う部分に圧着してバンプを形成するバンプ形成工程を具備し、前記第１ボンディング工程ないし前記第２ボンディング工程に際し、前記バンプにウェッジボンディングを行うことを特徴とする。   A method for manufacturing a semiconductor device according to claim 5 of the present invention is the method for manufacturing a semiconductor device according to claim 1, wherein a ball is formed at the tip of a wire protruding from the wire supply device, and the ball is A bump forming step of forming a bump by pressure-bonding to a portion where wedge bonding is performed in the first bonding step or the second bonding step; It is characterized by performing.

また、本発明の請求項６記載の半導体装置の製造方法は、ワイヤ供給装置から突出したワイヤの先端にボールを形成して、そのボールを半導体チップの周囲に配置されたリードあるいは配線部材に圧着するボールボンディングを行い、その後ワイヤ供給装置を移動させ、接続対象部材にウェッジボンディングを行う第１ボンディング工程と、ワイヤ供給装置から突出したワイヤの先端にボールを形成して、そのボールを、前記第１ボンディング工程においてボールボンディングを行った部分に直上から圧着するボールボンディングを行い、その後ワイヤ供給装置を移動させ、前記第１ボンディング工程における接続対象部材又はその接続対象部材とは異なる接続対象部材にウェッジボンディングを行う第２ボンディング工程と、を具備することを特徴とする。   According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a ball is formed at a tip of a wire protruding from a wire supply device, and the ball is crimped to a lead or a wiring member disposed around the semiconductor chip. Performing a ball bonding, and then moving the wire supply device to perform wedge bonding on the connection target member; forming a ball at the tip of the wire protruding from the wire supply device; Ball bonding is performed by directly pressing onto the portion where ball bonding has been performed in one bonding process, and then the wire supply device is moved so that the connection target member in the first bonding process or a connection target member different from the connection target member is wedged. A second bonding step for performing bonding. The features.

また、本発明の請求項７記載の半導体装置の製造方法は、請求項６記載の半導体装置の製造方法であって、前記第２ボンディング工程を２回以上繰り返し行い、前記リードあるいは前記配線部材に複数本のワイヤを接続させることを特徴とする。   According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the sixth aspect, wherein the second bonding step is repeated twice or more to form the lead or the wiring member. A plurality of wires are connected.

また、本発明の請求項８記載の半導体装置の製造方法は、請求項７記載の半導体装置の製造方法であって、繰り返し行う前記第２ボンディング工程に際し、前記第１ボンディング工程における接続対象部材に少なくとも１本のワイヤをウェッジボンディングにより接続させることを特徴とする。   Further, the method for manufacturing a semiconductor device according to claim 8 of the present invention is the method for manufacturing a semiconductor device according to claim 7, wherein the connection target member in the first bonding step is used in the second bonding step to be repeated. At least one wire is connected by wedge bonding.

また、本発明の請求項９記載の半導体装置の製造方法は、請求項７記載の半導体装置の製造方法であって、繰り返し行う前記第２ボンディング工程に際し、前記第１ボンディング工程における接続対象部材とは異なる同一の接続対象部材に少なくとも２本のワイヤをウェッジボンディングにより接続させることを特徴とする。   A method for manufacturing a semiconductor device according to claim 9 of the present invention is the method for manufacturing a semiconductor device according to claim 7, wherein, in the second bonding step that is repeatedly performed, the connection target member in the first bonding step and Is characterized in that at least two wires are connected to different same connection target members by wedge bonding.

また、本発明の請求項１０記載の半導体装置の製造方法は、請求項６記載の半導体装置の製造方法であって、ワイヤ供給装置から突出したワイヤの先端にボールを形成し、そのボールを、前記第１ボンディング工程ないし前記第２ボンディング工程においてウェッジボンディングを行う部分に圧着してバンプを形成するバンプ形成工程を具備し、前記第１ボンディング工程ないし前記第２ボンディング工程に際し、前記バンプにウェッジボンディングを行うことを特徴とする。   A method for manufacturing a semiconductor device according to claim 10 of the present invention is the method for manufacturing a semiconductor device according to claim 6, wherein a ball is formed at the tip of the wire protruding from the wire supply device, A bump forming step of forming a bump by pressure-bonding to a portion where wedge bonding is performed in the first bonding step or the second bonding step; It is characterized by performing.

また、本発明の請求項１１記載の半導体装置は、電極を有する半導体チップと、前記半導体チップが搭載されるチップ搭載部と、前記チップ搭載部の周囲に配置されるリード又は配線部材と、前記半導体チップが有する前記電極と前記リード又は配線部材とを接続するワイヤと、を備え、少なくとも前記半導体チップ、前記チップ搭載部、前記ワイヤおよび前記リード又は配線部材の前記ワイヤとの接続部分が樹脂封止された半導体装置であって、前記半導体チップが有する前記電極のうちの少なくとも１個に、複数本の前記ワイヤの一端の接続部が重ねて接続されており、それらの接続部はボールボンディング法特有の、厚みのあるコイン状に押しつぶされた突起部のほぼ中央からワイヤが導出される形状に形成されていることを特徴とする。   A semiconductor device according to claim 11 of the present invention is a semiconductor chip having electrodes, a chip mounting portion on which the semiconductor chip is mounted, a lead or wiring member disposed around the chip mounting portion, A wire for connecting the electrode of the semiconductor chip and the lead or the wiring member, and at least a connection portion of the semiconductor chip, the chip mounting portion, the wire and the wire of the lead or the wiring member is sealed with resin. A semiconductor device that is stopped, wherein at least one of the electrodes of the semiconductor chip is connected to a connecting portion of one end of the plurality of wires in an overlapping manner, and the connecting portion is connected by a ball bonding method. It is characterized in that the wire is led out from the approximate center of the peculiar, thick coin-shaped protrusion. .

また、本発明の請求項１２記載の半導体装置は、請求項１１記載の半導体装置であって、前記半導体チップが有する前記電極に一端が重ねて接続された複数本の前記ワイヤのうちの少なくとも一部は、その他端が、同一の前記リード又は配線部材に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする。   A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the eleventh aspect, wherein at least one of the plurality of wires connected at one end to the electrode of the semiconductor chip. The other end of the part is connected to the same lead or wiring member in the shape of a crescent or ellipse having no thickness peculiar to the wedge bonding method.

また、本発明の請求項１３記載の半導体装置は、請求項１１記載の半導体装置であって、前記半導体チップを複数個備え、少なくとも１箇の前記半導体チップが有する少なくとも１箇の前記電極に一端が重ねて接続された複数本の前記ワイヤのうちの少なくとも一部は、その他端が、他方の前記半導体チップが有する電極に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする。   A semiconductor device according to a thirteenth aspect of the present invention is the semiconductor device according to the eleventh aspect, comprising a plurality of the semiconductor chips, and one end of at least one of the electrodes of the at least one semiconductor chip. At least a part of the plurality of wires connected in a stacked manner has a crescent shape or an ellipse shape with no other thickness on the electrode of the other semiconductor chip at the other end. And are connected.

また、本発明の請求項１４記載の半導体装置は、請求項１１記載の半導体装置であって、前記半導体チップを複数個備え、少なくとも１箇の前記半導体チップが有する少なくとも１箇の前記電極に一端が重ねて接続された複数本の前記ワイヤの一部は、その他端が、他方の前記半導体チップが有する電極に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続され、他の一部は、その他端が、前記リード又は配線部材に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする。   A semiconductor device according to a fourteenth aspect of the present invention is the semiconductor device according to the eleventh aspect, comprising a plurality of the semiconductor chips, and one end of at least one electrode of the at least one semiconductor chip. A part of the plurality of wires connected to each other is connected at the other end to the electrode of the other semiconductor chip in a crescent or elliptical shape having no thickness peculiar to the wedge bonding method. The other part is characterized in that the other end is connected to the lead or the wiring member in the shape of a crescent or ellipse having no thickness peculiar to the wedge bonding method.

また、本発明の請求項１５記載の半導体装置は、請求項１１記載の半導体装置であって、前記チップ搭載部および前記リードは、金属板を加工して製作されるリードフレームの構成部材であることを特徴とする。   A semiconductor device according to a fifteenth aspect of the present invention is the semiconductor device according to the eleventh aspect, wherein the chip mounting portion and the lead are constituent members of a lead frame manufactured by processing a metal plate. It is characterized by that.

また、本発明の請求項１６記載の半導体装置は、請求項１１記載の半導体装置であって、前記チップ搭載部および前記配線部材は、配線基板の構成部材であることを特徴とする。   According to a sixteenth aspect of the present invention, there is provided the semiconductor device according to the eleventh aspect, wherein the chip mounting portion and the wiring member are constituent members of a wiring board.

また、本発明の請求項１７記載の半導体装置は、電極を有する半導体チップと、前記半導体チップが搭載されるチップ搭載部と、前記チップ搭載部の周囲に配置されるリード又は配線部材と、前記半導体チップが有する前記電極と前記リード又は配線部材とを接続するワイヤと、を備え、少なくとも前記半導体チップ、前記チップ搭載部、前記ワイヤおよび前記リード又は配線部材の前記ワイヤとの接続部分が樹脂封止された半導体装置であって、前記リード又は配線部材のうちの少なくとも１個に、複数本の前記ワイヤの一端の接続部が重ねて接続されており、それらの接続部はボールボンディング法特有の、厚みのあるコイン状に押しつぶされた突起部のほぼ中央からワイヤが導出される形状に形成されていることを特徴とする。   A semiconductor device according to claim 17 of the present invention is a semiconductor chip having electrodes, a chip mounting portion on which the semiconductor chip is mounted, a lead or wiring member disposed around the chip mounting portion, A wire for connecting the electrode of the semiconductor chip and the lead or the wiring member, and at least a connection portion of the semiconductor chip, the chip mounting portion, the wire and the wire of the lead or the wiring member is sealed with resin. A semiconductor device that is stopped, wherein at least one of the leads or wiring members is connected to a connecting portion of one end of a plurality of the wires, and these connecting portions are specific to the ball bonding method. The wire is led out from substantially the center of the protruding portion crushed into a thick coin shape.

また、本発明の請求項１８記載の半導体装置は、請求項１７記載の半導体装置であって、前記リード又は配線部材に一端が重ねて接続された複数本の前記ワイヤの一部は、その他端が他方の前記リード又は配線部材に、ウェッジボンディング法特有の、厚みの無い三日月状または楕円状の形状をなして接続され、他の一部は、その他端が前記半導体チップが有する前記電極に、ウェッジボンディング法特有の、先端が厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする。   The semiconductor device according to claim 18 of the present invention is the semiconductor device according to claim 17, wherein a part of the plurality of wires connected at one end to the lead or wiring member overlaps with the other end. Is connected to the other lead or wiring member in a non-thick crescent or oval shape unique to the wedge bonding method, and the other part is connected to the electrode that the other end of the semiconductor chip has, A characteristic feature of the wedge bonding method is that the tip is connected in a crescent or elliptical shape with no thickness.

また、本発明の請求項１９記載の半導体装置は、請求項１７記載の半導体装置であって、前記半導体チップを複数個備え、前記リード又は配線部材に一端が重ねて接続された複数本の前記ワイヤのうちの少なくとも一部は、その他端が互いに異なる前記半導体チップの各々が有する前記電極に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする。   The semiconductor device according to claim 19 of the present invention is the semiconductor device according to claim 17, comprising a plurality of the semiconductor chips, and a plurality of the plurality of the semiconductor chips, one end of which is overlapped and connected to the lead or wiring member. At least a part of the wires is connected to the electrodes of each of the semiconductor chips having other ends different from each other in a crescent-shaped or elliptical shape having no thickness unique to the wedge bonding method. And

また、本発明の請求項２０記載の半導体装置は、請求項１７記載の半導体装置であって、前記チップ搭載部および前記リードは、金属板を加工して製作されるリードフレームの構成部材であることを特徴とする。   A semiconductor device according to a twentieth aspect of the present invention is the semiconductor device according to the seventeenth aspect, wherein the chip mounting portion and the lead are constituent members of a lead frame manufactured by processing a metal plate. It is characterized by that.

また、本発明の請求項２１記載の半導体装置は、請求項１７記載の半導体装置であって、前記チップ搭載部および前記配線部材は、配線基板の構成部材であることを特徴とする。   A semiconductor device according to a twenty-first aspect of the present invention is the semiconductor device according to the seventeenth aspect, wherein the chip mounting portion and the wiring member are constituent members of a wiring board.

本発明の好ましい形態によれば、半導体チップ上の同一の電極に対して、電極の面積を拡大することなく２本以上のワイヤを接続することができる。よって、半導体チップ上の同一の電極に複数本のワイヤを接続する構造において、接続するワイヤ数にかかわらず常に電極の面積を最小にすることができ、チップ全体に占める電極の個数および面積を最小にすることが可能となる。通常、半導体チップにおいては、その外周部に電極が一列ないし複数列に配置されており、電極の個数および面積を最小にすることでチップサイズを小さくすることができる。また、複数本のワイヤを同一の電極に接続できるので、より細線化されたワイヤを用いながら、電源電極や接地電極への安定した電流容量を確保すると同時に、半導体チップの小型化を実現できるので、小型、高品質の半導体装置を安価に提供できるようになる。   According to the preferred embodiment of the present invention, two or more wires can be connected to the same electrode on the semiconductor chip without increasing the area of the electrode. Therefore, in the structure in which multiple wires are connected to the same electrode on the semiconductor chip, the area of the electrode can always be minimized regardless of the number of wires to be connected, and the number and area of the electrodes in the entire chip can be minimized. It becomes possible to. Usually, in a semiconductor chip, electrodes are arranged in one or more rows on the outer periphery thereof, and the chip size can be reduced by minimizing the number and area of the electrodes. In addition, since multiple wires can be connected to the same electrode, it is possible to reduce the size of the semiconductor chip while securing a stable current capacity to the power supply electrode and the ground electrode while using a finer wire. Therefore, a small-sized and high-quality semiconductor device can be provided at low cost.

また、近年、機器の小型化の要求から１個の半導体装置（パッケージ）の中に複数個の半導体チップを内蔵することが行われてきており、ＱＦＰ型の半導体装置では、各半導体チップ上の電極とリード（インナーリード）とをワイヤで接続すると共に、互いに異なる半導体チップ上の電極同士をワイヤで接続することが行われるようになってきた。同様に、配線基板を用いたＢＧＡ（ボール・グリッド・アレイ）型の半導体装置においても、１個のパッケージの中に複数個の半導体チップを内蔵して、各半導体チップ上の電極と配線基板上の表層配線（配線部材）とをワイヤで接続すると共に、互いに異なる半導体チップ上の電極同士をワイヤで接続することが行われるようになってきた。   In recent years, a plurality of semiconductor chips have been built in one semiconductor device (package) due to a demand for miniaturization of equipment. In a QFP type semiconductor device, each semiconductor chip has a built-in structure. An electrode and a lead (inner lead) are connected by a wire, and electrodes on different semiconductor chips are connected by a wire. Similarly, in a BGA (ball grid array) type semiconductor device using a wiring board, a plurality of semiconductor chips are built in one package, and electrodes on each semiconductor chip and the wiring board are mounted. In addition to connecting the surface layer wiring (wiring member) with wires, electrodes on different semiconductor chips have been connected with wires.

本発明の好ましい形態によれば、同一の電極からの複数本のワイヤをそれぞれ異なるリード（インナーリード）又は配線部材（配線基板の表層配線）に接続することや、同一の電極からの複数本のワイヤを互いに異なる半導体チップ上の電極同士の接続に用いることも可能となるため、チップサイズを大きくすることなく、複数本のワイヤが接続された電極を、例えば他方の半導体チップ上の電極とリードとの中継電極として使用することができるようになる。また、同一のリード（インナーリード）又は配線部材（配線基板の表層配線）からの複数本のワイヤをそれぞれ異なるリード又は配線部材に接続することや、同一のリード又は配線部材からの複数本のワイヤをそれぞれ異なる半導体チップ上の電極に接続することや、同一のリード又は配線部材からの複数本のワイヤをそれぞれ半導体チップ上の異なる電極に接続することが可能となるため、リードを大きくすることなく、すなわちパッケージを大きくすることなく、複数本のワイヤが接続されたリード又は配線部材を、例えば各半導体チップ上の複数の電極の電源として用いたり、互いに異なる半導体チップ上の電極同士の中継リード又は中継配線として使用することができるようになる。したがって、装置内の配線を簡略化することが可能となり、高集積、高密度、高品質な半導体装置をコンパクトかつ安価に提供できるようになる。   According to a preferred embodiment of the present invention, a plurality of wires from the same electrode are connected to different leads (inner leads) or wiring members (surface layer wiring of a wiring board), or a plurality of wires from the same electrode are connected. Since wires can be used to connect electrodes on different semiconductor chips, an electrode to which a plurality of wires are connected can be connected to, for example, an electrode on the other semiconductor chip without increasing the chip size. And can be used as a relay electrode. Also, a plurality of wires from the same lead (inner lead) or wiring member (surface wiring of the wiring board) are connected to different leads or wiring members, or a plurality of wires from the same lead or wiring member. Can be connected to electrodes on different semiconductor chips, and a plurality of wires from the same lead or wiring member can be connected to different electrodes on the semiconductor chip without increasing the leads. That is, without using a large package, a lead or a wiring member to which a plurality of wires are connected is used as a power source for a plurality of electrodes on each semiconductor chip, for example, or a relay lead between electrodes on different semiconductor chips or It can be used as a relay wiring. Therefore, the wiring in the device can be simplified, and a highly integrated, high-density, high-quality semiconductor device can be provided in a compact and inexpensive manner.

（実施の形態１）
以下、本発明の実施の形態１について、図面を参照しながら説明する。
図１は本発明の実施の形態１に係る半導体装置の断面図、図２（ａ）は同半導体装置のワイヤボンディング部分の内部構造を説明するための斜視図、図２（ｂ）は同半導体装置のワイヤボンディング部分の内部構造を説明するための上面図、図２（ｃ）は同半導体装置のワイヤボンディング部分の内部構造を説明するための断面図である。なお、以下の説明において同一の部材には同一符号を付して、適宜説明を省略する。 (Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings.
1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention, FIG. 2 (a) is a perspective view for explaining the internal structure of a wire bonding portion of the semiconductor device, and FIG. 2 (b) is the same semiconductor. FIG. 2C is a cross-sectional view for explaining the internal structure of the wire bonding portion of the semiconductor device, and FIG. 2C is a top view for explaining the internal structure of the wire bonding portion of the device. In the following description, the same members are denoted by the same reference numerals, and description thereof is omitted as appropriate.

この半導体装置はＱＦＰ型の半導体装置であり、図１に示すように、集積回路が形成された半導体チップ１がリードフレームのダイパッド部（チップ搭載部）２に搭載されている。また、ダイパッド部２の周辺には放射状にリードフレームのリード４が配置されており、インナーリード４ａの先端がダイパッド部２に対して対向している。また、半導体チップ１の表面に形成されている電極３とインナーリード４ａとがワイヤ５で接続されている。また、半導体チップ１、ダイパッド部２、ワイヤ５、インナーリード４ａ（リード４のワイヤ接続部分）が一括して樹脂封止体６により樹脂封止され、インナーリード４ａに連続したリードフレームのアウターリード４ｂが樹脂封止体６の外部でガルウィング型に曲げ成形されている。   This semiconductor device is a QFP type semiconductor device. As shown in FIG. 1, a semiconductor chip 1 on which an integrated circuit is formed is mounted on a die pad portion (chip mounting portion) 2 of a lead frame. Further, leads 4 of the lead frame are arranged radially around the die pad portion 2, and the tips of the inner leads 4 a are opposed to the die pad portion 2. In addition, the electrode 3 formed on the surface of the semiconductor chip 1 and the inner lead 4 a are connected by a wire 5. Further, the semiconductor chip 1, the die pad portion 2, the wire 5, and the inner lead 4a (the wire connecting portion of the lead 4) are collectively sealed with the resin sealing body 6, and the outer lead of the lead frame continuous to the inner lead 4a. 4 b is bent and formed into a gull wing type outside the resin sealing body 6.

この半導体装置が従来のものと異なるのは、図２に示すように、半導体チップ１上の少なくとも１個の電極３に２本のワイヤ５ａ、５ｂの一端の接続部が重ねて接続されており、それらの接続部が、ボールボンディング法特有の、厚みのあるコイン状に押しつぶされた突起部のほぼ中央からワイヤが導出される形状に形成されている点と、それらの２本のワイヤ５ａ、５ｂの他端が、同一のインナーリード４ａに、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されている点である。   As shown in FIG. 2, this semiconductor device is different from the conventional one in that a connection portion at one end of two wires 5a and 5b is overlapped and connected to at least one electrode 3 on a semiconductor chip 1. The connection portions are formed in a shape in which the wires are led out from substantially the center of the protruding portion crushed into a thick coin shape, which is peculiar to the ball bonding method, and the two wires 5a, The other end of 5b is connected to the same inner lead 4a in the shape of a crescent or ellipse having no thickness peculiar to the wedge bonding method.

続いて、同一の電極に２本のワイヤを接続する方法について、図３に示す工程断面図に沿って説明する。まず、図３（ａ）に示すように、ワイヤ供給装置であるキャピラリ９の先端から突出したワイヤ５ａの先端とトーチ１０との間で放電を行い、スパークによりボール１１ａを形成する。   Next, a method of connecting two wires to the same electrode will be described along the process cross-sectional view shown in FIG. First, as shown in FIG. 3A, electric discharge is performed between the tip of the wire 5a protruding from the tip of the capillary 9 as the wire supply device and the torch 10, and a ball 11a is formed by spark.

次に図３（ｂ）〜図３（ｄ）に示すように、半導体チップ１上の電極にボール１１ａを圧着して（ボールボンディング）、ボールボンディング側の接続部７ａを形成する。その後、図３（ｅ）〜図３（ｇ）に示すように、ワイヤ５ａを水平方向に折り曲げて引き出し、ワイヤ５ａが所定の軌跡に沿って配線されるようにキャピラリ９を移動させ、接続対象部材であるインナーリード４ａにワイヤ５ａをこすり付けて（ウェッジボンディング）、ウェッジボンディング側の接続部８ａを形成する。   Next, as shown in FIGS. 3B to 3D, a ball 11a is pressure-bonded to an electrode on the semiconductor chip 1 (ball bonding) to form a connection portion 7a on the ball bonding side. Thereafter, as shown in FIGS. 3 (e) to 3 (g), the wire 5a is bent and pulled out in the horizontal direction, and the capillary 9 is moved so that the wire 5a is wired along a predetermined trajectory. The wire 5a is rubbed on the inner lead 4a which is a member (wedge bonding) to form the connection portion 8a on the wedge bonding side.

以上の第１ボンディング工程を行った後、第２ボンディング工程を行う。すなわち、まず、図３（ｈ）に示すように、キャピラリ９の先端から突出したワイヤ５ｂの先端とトーチ１０との間で放電を行い、スパークによりボール１１ｂを形成する。   After performing the first bonding step, the second bonding step is performed. That is, first, as shown in FIG. 3 (h), discharge is performed between the tip of the wire 5b protruding from the tip of the capillary 9 and the torch 10, and a ball 11b is formed by spark.

次に図３（ｉ）に示すように、接続部７ａ（第１ボンディング工程においてボールボンディングを行った部分）に直上からボール１１ｂを圧着して（ボールボンディング）、ボールボンディング側の接続部７ｂを形成する。その後、図３（ｊ）〜図３（ｌ）に示すように、ワイヤ５ｂを垂直方向に引き出して折り曲げ、ワイヤ５ｂが所定の軌跡に沿って配線されるようにキャピラリ９を移動させ、接続対象部材であるインナーリード４ａにワイヤ５ｂをこすり付けて（ウェッジボンディング）、ウェッジボンディング側の接続部８ｂを形成する。なお、ここでは、第１ボンディング工程と第２ボンディング工程における接続対象部材は同一のインナーリード４ａである。   Next, as shown in FIG. 3 (i), the ball 11b is pressure-bonded to the connecting portion 7a (the portion where ball bonding has been performed in the first bonding step) from directly above (ball bonding), and the connecting portion 7b on the ball bonding side is connected. Form. Thereafter, as shown in FIGS. 3 (j) to 3 (l), the wire 5b is pulled out in the vertical direction and bent, and the capillary 9 is moved so that the wire 5b is routed along a predetermined trajectory. The wire 5b is rubbed (wedge bonding) on the inner lead 4a which is a member to form the connection portion 8b on the wedge bonding side. Here, the connection target members in the first bonding process and the second bonding process are the same inner lead 4a.

以上のように第１および第２ボンディング工程を行うことで、同一の電極に２本のワイヤの一端をボールボンディング法により重ねて接続することができる。ワイヤボンディング工程で使用するワイヤには、一般的に、金や銅等の金属を原料とする直径φ１５〜４０μｍのものが使われる。ボールボンディング法においてワイヤの一端に形成されるボールの直径はワイヤの直径の１．５倍〜４倍程度であり、接続点に接合されるときキャピラリの先端部で厚さが５〜６０μｍ程度になるまで押しつぶされるので、ボールボンディング側の接続部は、厚みのあるコイン状に押しつぶされた突起部のほぼ中央からワイヤが導出される形状になる。一方、ワイヤの他端は、キャピラリの先端周辺部で接続点にこすり付けるように潰すので、ウェッジボンディング側の接続部は、厚みの無い三日月状または楕円状の形状になる。   By performing the first and second bonding steps as described above, one end of two wires can be overlapped and connected to the same electrode by the ball bonding method. As a wire used in the wire bonding process, generally, a wire having a diameter of 15 to 40 μm made of a metal such as gold or copper is used. In the ball bonding method, the diameter of the ball formed at one end of the wire is about 1.5 to 4 times the diameter of the wire, and the thickness at the tip of the capillary is about 5 to 60 μm when bonded to the connection point. As a result, the connecting portion on the ball bonding side has a shape in which the wire is led out from substantially the center of the protruding portion crushed into a thick coin shape. On the other hand, the other end of the wire is crushed so as to be rubbed against the connection point around the tip of the capillary, so that the connection part on the wedge bonding side has a crescent or elliptical shape with no thickness.

また、例えば図３（ｇ）に示すように、ボールボンディング側の接続部７ａの上部にはワイヤ５ａの一部が存在しているため、その上から圧着するボール１１ｂとの接続ズレを防止するために、キャピラリ９によってボール１１ｂを確実に保持しておく必要がある。これに対して、以下で説明する方法を実施すれば、容易に接続ズレを防止することができる。図４は、同一の電極に複数本のワイヤを重ねて接続するに際して接続ズレを防止する方法を説明するための工程断面図である。   Further, for example, as shown in FIG. 3G, since a part of the wire 5a exists at the upper part of the connection part 7a on the ball bonding side, misalignment with the ball 11b to be crimped from above is prevented. Therefore, it is necessary to securely hold the ball 11b by the capillary 9. On the other hand, if the method described below is performed, it is possible to easily prevent the connection shift. FIG. 4 is a process cross-sectional view for explaining a method of preventing connection misalignment when a plurality of wires are overlapped and connected to the same electrode.

まず、第１ボンディング工程後、図４（ａ）に示すように、キャピラリ９の先端から突出したワイヤ５ｂの先端とトーチ１０との間で放電を行い、スパークによりボール１１ｂを形成する。次に図４（ｂ）に示すように、平坦部１２上にボール１１ｂを押し付けて、ボール１１ｂの下面に平坦面を形成する。次に図４（ｃ）〜図４（ｄ）に示すように、接続部７ａに直上からボール１１ｂを圧着してボールボンディング側の接続部７ｂを形成する。   First, after a 1st bonding process, as shown to Fig.4 (a), it discharges between the front-end | tip of the wire 5b which protruded from the front-end | tip of the capillary 9, and the torch 10, and forms the ball | bowl 11b by a spark. Next, as shown in FIG. 4B, the ball 11b is pressed onto the flat portion 12 to form a flat surface on the lower surface of the ball 11b. Next, as shown in FIGS. 4C to 4D, the ball 11b is pressure-bonded to the connecting portion 7a from directly above to form the connecting portion 7b on the ball bonding side.

このように、第２ボンディング工程に際し、キャピラリ９から突出したワイヤ５ｂの先端にボール１１ｂを形成した後、平坦部１２にボール１１ｂを押し付け、ボール１１ｂの下面に平坦面を形成してボールボンディングを行う。   Thus, in the second bonding step, after forming the ball 11b on the tip of the wire 5b protruding from the capillary 9, the ball 11b is pressed against the flat portion 12, and a flat surface is formed on the lower surface of the ball 11b to perform ball bonding. Do.

この方法によれば、ボール１１ｂの下面を平坦面としたので、接続部７ａの上部に存在するワイヤ５ａと接触しても接触ズレを防止することができ、確実な接合を実現できる。なお、平坦部１２としては、例えばリードフレームの一部やワイヤボンド設備の一部の平坦面を用いることができる。また、後述するように本発明をＢＧＡ型の半導体装置に適用する場合には、配線基板の一部の平坦面を用いることができる。   According to this method, since the lower surface of the ball 11b is a flat surface, contact displacement can be prevented even if it contacts the wire 5a existing above the connection portion 7a, and reliable bonding can be realized. As the flat part 12, for example, a part of a flat surface of a part of a lead frame or a part of wire bond equipment can be used. As will be described later, when the present invention is applied to a BGA type semiconductor device, a part of the flat surface of the wiring board can be used.

また、以下で説明する方法により接続ズレを防止してもよい。すなわち、図５（ａ）〜図５（ｃ）に示すように、第１ボンディング工程後、まず、接続部７ａに直上から、先端が円錐型の突起形状をしている加圧ツール１３を押し当てて接続部７ａを押し潰す。次に、図５（ｄ）、図５（ｅ）に示すように、押し潰した接続部７ａに直上からボール１１ｂを圧着してボールボンディング側の接続部７ｂを形成する。加圧ツール１３の先端部が押し当てられた接続部７ａの上部には円錐型の窪みができるため、ボール１１ｂは確実にその窪みの中央に位置合わせされる。これにより更に確実な接合を実現できる。なお、加圧ツール１３の先端部の円錐の開き角度は１２０〜１７０°の鈍角に設定するのが望ましい。   Further, the connection shift may be prevented by the method described below. That is, as shown in FIG. 5A to FIG. 5C, after the first bonding step, first, the pressing tool 13 whose tip has a conical protrusion shape is pressed from directly above the connecting portion 7a. The contact portion 7a is crushed by applying. Next, as shown in FIGS. 5D and 5E, the ball 11b is pressure-bonded to the crushed connection portion 7a from directly above to form the ball bonding side connection portion 7b. Since a conical depression is formed in the upper part of the connection portion 7a against which the tip of the pressing tool 13 is pressed, the ball 11b is reliably aligned with the center of the depression. Thereby, more reliable joining is realizable. The opening angle of the cone at the tip of the pressing tool 13 is preferably set to an obtuse angle of 120 to 170 °.

このように、第２ボンディング工程においてボールボンディングを行う部分（接続部７ａ）に直上から加圧ツールを押し当てて該部分（接続部７ａ）を押し潰す工程をさらに含み、第２ボンディング工程に際し、その押し潰した部分にボールボンディングを行う。   As described above, the method further includes a step of pressing the pressure tool from directly above the portion (connecting portion 7a) for performing ball bonding in the second bonding step and crushing the portion (connecting portion 7a). Ball bonding is performed on the crushed portion.

また、以下で説明する方法により接続ズレを防止してもよい。この方法は、加圧ツールの先端が球面型の突起形状をしている点のみが、上記した方法と異なる。すなわち、図６（ａ）〜図６（ｃ）に示すように、第１ボンディング工程後、まず、接続部７ａに直上から、先端が球面型の突起形状をしている加圧ツール１４を押し当てて接続部７ａを押し潰す。次に、図６（ｄ）、図６（ｅ）に示すように、押し潰した接続部７ａに直上からボール１１ｂを圧着してボールボンディング側の接続部７ｂを形成する。加圧ツール１３の先端部が押し当てられた接続部７ａの上部には球面型の窪みができ、接続部７ａにボール１１ｂを圧着する際に、まず、その窪みの中心部とボール１１ｂが点接触するので、確実に位置合わせすることができる。また、窪みを球面型にすることで、空隙のない確実な接合を実現できる。なお、加圧ツール１４の先端部の球面の半径はボール１１ｂの半径の１．５〜５倍の範囲で設定することが望ましい。   Further, the connection shift may be prevented by the method described below. This method differs from the above-described method only in that the tip of the pressing tool has a spherical protrusion shape. That is, as shown in FIG. 6A to FIG. 6C, after the first bonding step, first, the pressing tool 14 whose tip has a spherical projection shape is pressed from directly above the connecting portion 7a. The contact portion 7a is crushed by applying. Next, as shown in FIGS. 6D and 6E, a ball 11b is pressure-bonded to the crushed connecting portion 7a from directly above to form a connecting portion 7b on the ball bonding side. A spherical recess is formed in the upper portion of the connection portion 7a against which the tip of the pressing tool 13 is pressed. When the ball 11b is pressure-bonded to the connection portion 7a, first, the center portion of the recess and the ball 11b are pointed. Since it contacts, it can align reliably. In addition, by making the recess spherical, it is possible to realize reliable joining without a gap. The radius of the spherical surface at the tip of the pressing tool 14 is desirably set in a range of 1.5 to 5 times the radius of the ball 11b.

以上説明した方法によれば、ボールボンディング法によって形成した接続部上に、さらに他のワイヤの一端をボールボンディング法によって接続するに際し、接触ズレを防止することができる。   According to the method described above, contact misalignment can be prevented when one end of another wire is connected to the connecting portion formed by the ball bonding method by the ball bonding method.

なお、本実施の形態１では、同一の電極からの複数本のワイヤを同一のインナーリードに接続する場合について説明したが、それらのワイヤをそれぞれ異なるインナーリードに接続してもよい。   In the first embodiment, the case where a plurality of wires from the same electrode are connected to the same inner lead has been described. However, these wires may be connected to different inner leads.

（実施の形態２）
続いて、本発明の実施の形態２について、図面を参照しながら説明する。図７は本発明の実施の形態２に係る半導体装置のワイヤボンディング部分の内部構造を説明するための断面図である。但し、前述した実施の形態１にて説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 2)
Next, Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 7 is a cross-sectional view for explaining the internal structure of the wire bonding portion of the semiconductor device according to the second embodiment of the present invention. However, the same members as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

この半導体装置は、半導体チップ上の少なくとも１個の電極に３本のワイヤの一端がボールボンディング法により重ねて接続され、その３本のワイヤ５の他端が同一のインナーリード上の異なる位置にウェッジボンディング法により接続されている点が、前述した実施の形態１と異なる。すなわち、図７に示すように、半導体チップ１上の同一の電極には、ワイヤ５ａ〜５ｃのボールボンディング側の接続部７ａ〜７ｃが重ねて形成されている。また、同一のインナーリード４ａ上の異なる位置に、ワイヤ５ａ〜５ｃのウェッジボンディング側の接続部８ａ〜８ｃが形成されている。この接続は、実施の形態１で説明した第２ボンディング工程を２回繰り返すことで実現できる。この構成により、必要に応じて電流容量を調整することが可能となり、更に小型・高品質で低コストな半導体装置を提供することが可能となる。   In this semiconductor device, one end of three wires is overlapped and connected to at least one electrode on a semiconductor chip by a ball bonding method, and the other ends of the three wires 5 are at different positions on the same inner lead. The connection point by the wedge bonding method is different from the first embodiment described above. That is, as shown in FIG. 7, the same electrodes on the semiconductor chip 1 are formed by overlapping the connection portions 7a to 7c on the ball bonding side of the wires 5a to 5c. Further, connection portions 8a to 8c on the wedge bonding side of the wires 5a to 5c are formed at different positions on the same inner lead 4a. This connection can be realized by repeating the second bonding step described in the first embodiment twice. With this configuration, it is possible to adjust the current capacity as necessary, and it is possible to provide a semiconductor device that is small in size, high quality, and low cost.

なお、本実施の形態２では、同一の電極に３本のワイヤを接続する場合について説明したが、第２ボンディング工程を２回以上繰り返すことで、同一の電極に３本以上のワイヤを接続することが出来る。   In the second embodiment, the case where three wires are connected to the same electrode has been described. However, by repeating the second bonding step twice or more, three or more wires are connected to the same electrode. I can do it.

（実施の形態３）
続いて、本発明の実施の形態３について、図面を参照しながら説明する。図８は本発明の実施の形態３に係る半導体装置のワイヤボンディング部分の内部構造を説明するための断面図である。但し、前述した実施の形態１、２にて説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 3)
Subsequently, Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 8 is a cross-sectional view for explaining the internal structure of the wire bonding portion of the semiconductor device according to the third embodiment of the present invention. However, the same members as those described in the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted.

この半導体装置は、半導体チップ上の少なくとも１個の電極に２本のワイヤの一端がボールボンディング法により重ねて接続され、その２本のワイヤの他端が、同一のインナーリード上の同一の接続点に、バンプを介して、ウェッジボンディング法により重ねて接続されている点が、前述した実施の形態１と異なる。   In this semiconductor device, one end of two wires is overlapped and connected to at least one electrode on a semiconductor chip by a ball bonding method, and the other end of the two wires is connected to the same inner lead. This is different from the first embodiment described above in that the bumps are overlapped and connected by the wedge bonding method.

すなわち、図８に示すように、ワイヤ５ａのウェッジボンディング側の接続部上にバンプ１５を形成し、そのバンプ１５上に、ワイヤ５ｂのウェッジボンディング側の接続部を形成した構成となっている。このバンプ１５は、キャピラリから突出したワイヤの先端にボールを形成し、そのボールを、第２ボンディング工程においてウェッジボンディングを行う部分に圧着することで形成することができる。よって、このバンプ形成工程を、ワイヤ５ｂのウェッジボンディングを行う前に実行しておき、第２ボンディング工程に際し、そのバンプ１５上にウェッジボンディングを行うことで、バンプ１５上にワイヤ５ｂのウェッジボンディング側の接続部を形成することができる。   That is, as shown in FIG. 8, the bump 15 is formed on the connection portion on the wedge bonding side of the wire 5a, and the connection portion on the wedge bonding side of the wire 5b is formed on the bump 15. The bump 15 can be formed by forming a ball at the tip of the wire protruding from the capillary and pressing the ball on a portion where wedge bonding is performed in the second bonding step. Therefore, this bump forming step is executed before the wedge bonding of the wire 5b, and the wedge bonding is performed on the bump 15 in the second bonding step. Can be formed.

本実施の形態３によれば、ボールボンディング側とウェッジボンディング側の両方において、従来、１本のワイヤしか接続することができなかった面積に複数本のワイヤを接続することが可能となり、半導体チップの縮小化と共にリードフレームの縮小化が可能となる。よって、配線の自由度が向上し、半導体装置の小型化に大きく寄与する。また、ウェッジボンディング法によって形成された接続部は前述したように厚みの無い三日月状または楕円状の形状であるので、これをそのまま垂直に重ねてボンディングする場合は各々のワイヤの接続状態を安定化することが重要である。これに対し、本実施の形態３のように、バンプを形成し、そのバンプ上にウェッジボンディングを行えば、ウェッジボンディングにより積み重ねられた各ワイヤの接続部はバンプを介し強固に接合されることになるので、接合信頼性の向上を実現することができる。   According to the third embodiment, on both the ball bonding side and the wedge bonding side, it is possible to connect a plurality of wires to an area where conventionally only one wire can be connected. As a result, the lead frame can be reduced. Therefore, the degree of freedom of wiring is improved, which greatly contributes to downsizing of the semiconductor device. In addition, since the connection part formed by the wedge bonding method has a crescent or elliptical shape with no thickness as described above, the connection state of each wire is stabilized when bonding it vertically as it is. It is important to. On the other hand, if the bump is formed and wedge bonding is performed on the bump as in the third embodiment, the connecting portions of the wires stacked by the wedge bonding are firmly bonded via the bump. Therefore, it is possible to improve the bonding reliability.

なお、本実施の形態３では、ウェッジボンディング側の接続部を２つ重ねて接続する場合について説明したが、上記したバンプ形成工程を繰り返して、先に形成した接続部上にバンプを形成することで、ウェッジボンディング側の接続部を３つ以上重ねて接続することもできる。   In addition, in this Embodiment 3, although the case where two connection parts on the wedge bonding side were overlapped and connected was described, bumps are formed on the previously formed connection parts by repeating the bump formation process described above. Thus, three or more connection portions on the wedge bonding side can be stacked and connected.

（実施の形態４）
続いて、本発明の実施の形態４について、図面を参照しながら説明する。図９（ａ）は本発明の実施の形態４に係る半導体装置のワイヤボンディング部分の内部構造を説明するための上面図、図９（ｂ）は同半導体装置のワイヤボンディング部分の内部構造を説明するための断面図である。但し、前述した実施の形態１〜３にて説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 4)
Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 9A is a top view for explaining the internal structure of the wire bonding portion of the semiconductor device according to the fourth embodiment of the present invention, and FIG. 9B shows the internal structure of the wire bonding portion of the semiconductor device. It is sectional drawing for doing. However, the same members as those described in the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted.

この半導体装置は、垂直方向に積層された２個の半導体チップがダイパッド部に搭載されており、同一の電極からの複数本のワイヤがそれぞれ異なる接続対象部材に接続されている点が、前述した実施の形態１〜３と異なる。   In this semiconductor device, two semiconductor chips stacked in the vertical direction are mounted on the die pad portion, and a plurality of wires from the same electrode are connected to different connection target members as described above. Different from the first to third embodiments.

すなわち、図９に示すように、上方の半導体チップ１ａ上の同一の電極３ａに２本のワイヤ５ａ、５ｂの一端がボールボンディング法により重ねて接続されており、ワイヤ５ａの他端は、下方の半導体チップ１ｂ上の電極３ｂにウェッジボンディング法により接続され、ワイヤ５ｂの他端は、インナーリード４ａにウェッジボンディング法により接続されている。   That is, as shown in FIG. 9, one end of two wires 5a and 5b are overlapped and connected to the same electrode 3a on the upper semiconductor chip 1a by a ball bonding method, and the other end of the wire 5a is The other end of the wire 5b is connected to the inner lead 4a by the wedge bonding method.

また、ここでは、キャピラリから突出したワイヤの先端にボールを形成し、そのボールを、第１ボンディング工程においてウェッジボンディングを行う部分（電極３ｂ）に圧着してバンプ１５を形成するバンプ形成工程を、ワイヤ５ａのウェッジボンディングを行う前に実行しておき、バンプ１５上にワイヤ５ａのウェッジボンディング側の接続部８ａを形成している。   Further, here, a bump forming step of forming a bump 15 by forming a ball at the tip of the wire protruding from the capillary and pressing the ball to a portion (electrode 3b) to be wedge-bonded in the first bonding step, This is performed before the wedge bonding of the wire 5a, and the connection portion 8a on the wedge bonding side of the wire 5a is formed on the bump 15.

また、図１０に示すように、下方の半導体チップ上の同一の電極に２本のワイヤを接続してもよい。すなわち、図１０に示す半導体装置では、下方の半導体チップ１ｂ上の同一の電極３ｂに２本のワイヤ５ａ、５ｂの一端がボールボンディング法により重ねて接続されており、ワイヤ５ａの他端は、インナーリード４ａにウェッジボンディング法により接続され、ワイヤ５ｂの他端は、上方の半導体チップ１ａ上の電極３ａにウェッジボンディング法により接続されている。   Further, as shown in FIG. 10, two wires may be connected to the same electrode on the lower semiconductor chip. That is, in the semiconductor device shown in FIG. 10, one end of two wires 5a and 5b are overlapped and connected to the same electrode 3b on the lower semiconductor chip 1b by a ball bonding method, and the other end of the wire 5a is The wire 5b is connected to the inner lead 4a by the wedge bonding method, and the other end of the wire 5b is connected to the electrode 3a on the upper semiconductor chip 1a by the wedge bonding method.

また、ここでは、キャピラリから突出したワイヤの先端にボールを形成し、そのボールを、第２ボンディング工程においてウェッジボンディングを行う部分（電極３ａ）に圧着してバンプ１５を形成するバンプ形成工程を、ワイヤ５ｂのウェッジボンディングを行う前に実行しておき、バンプ１５上にワイヤ５ｂのウェッジボンディング側の接続部８ｂを形成している。   Further, here, a bump forming step is performed in which a ball is formed at the tip of the wire protruding from the capillary, and the ball is crimped to a portion (electrode 3a) where wedge bonding is performed in the second bonding step to form the bump 15. This is performed before the wedge bonding of the wire 5b, and the connection portion 8b on the wedge bonding side of the wire 5b is formed on the bump 15.

なお、半導体チップ上の同一の電極に２本のワイヤを重ねて接続する場合について説明したが、無論、同一の電極に３本以上のワイヤを重ねて接続することもできる。また、同一の電極からの２本のワイヤのうちの一方を他の半導体チップ上の電極に接続し、他方をインナーリードに接続したが、この接続形態に限定されるものではなく、同一の電極からの複数本のワイヤ各々のウェッジボンディング側の接続対象部材は、他の半導体チップ上の同一の電極であってもよいし、他の半導体チップ上の異なる電極であってもよいし、同一のインナーリードであってもよいし、異なるインナーリードであってもよい。また、ウェッジボンディング側の接続対象部材が同一の場合、実施の形態３において説明したようにランドを形成することで、ウェッジボンディング側の接続部を同一の接続点に重ねて接続してもよい。   Although the case where two wires are overlapped and connected to the same electrode on the semiconductor chip has been described, of course, three or more wires can be overlapped and connected to the same electrode. In addition, one of the two wires from the same electrode is connected to an electrode on another semiconductor chip and the other is connected to the inner lead. However, the connection is not limited to this, and the same electrode The connection target member on the wedge bonding side of each of the plurality of wires from the same wire may be the same electrode on another semiconductor chip, or may be a different electrode on another semiconductor chip, or the same It may be an inner lead or a different inner lead. Further, when the connection target members on the wedge bonding side are the same, the connection portions on the wedge bonding side may be overlapped and connected to the same connection point by forming lands as described in the third embodiment.

また、ここでは、２個の半導体チップが垂直方向に配置されている場合について説明したが、２個の半導体チップが同一面上に並列に配置された構成においても同様に実施できる。また、３個以上の半導体チップが垂直方向に配置された構成や同一面上に並列に配置された構成においても同様に実施できる。また、並列配置と垂直方向の配置を組み合わせた構成においても同様に実施できる。   Although the case where two semiconductor chips are arranged in the vertical direction has been described here, the present invention can be similarly applied to a configuration in which two semiconductor chips are arranged in parallel on the same surface. Further, the present invention can be similarly applied to a configuration in which three or more semiconductor chips are arranged in the vertical direction or a configuration in which they are arranged in parallel on the same plane. Moreover, it can implement similarly in the structure which combined the parallel arrangement | positioning and the arrangement | positioning of a perpendicular direction.

本実施の形態４によれば、電源電極や接地電極への安定した電流容量の確保を図りながらワイヤの細線化を図ることができ、電極の数や面積、リードの本数やワイヤ接続部の面積、並びにチップ間接続のための中継リードなどを削減することができる。よって、半導体チップのサイズ縮小化・高集積化や、半導体装置の小型化・高集積化を行うことができ、低コストで高集積・高品質な半導体装置を提供することができる。   According to the fourth embodiment, it is possible to reduce the thickness of the wire while ensuring a stable current capacity to the power supply electrode and the ground electrode. The number and area of the electrodes, the number of leads, and the area of the wire connection portion In addition, it is possible to reduce relay leads and the like for chip-to-chip connection. Accordingly, the size and integration of the semiconductor chip can be reduced, and the semiconductor device can be reduced in size and integration, and a highly integrated and high quality semiconductor device can be provided at low cost.

（実施の形態５）
以下、本発明の実施の形態５について、図面を参照しながら説明する。図１１は本発明の実施の形態５に係る半導体装置の断面図である。但し、前述した実施の形態１〜４にて説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 5)
Embodiment 5 of the present invention will be described below with reference to the drawings. FIG. 11 is a sectional view of a semiconductor device according to the fifth embodiment of the present invention. However, the same members as those described in the first to fourth embodiments are denoted by the same reference numerals, and description thereof is omitted.

この半導体装置はＢＧＡ型の半導体装置であり、図１１に示すように、樹脂基材からなり、少なくとも主面および主面とは反対側の底面に金属配線１８を有する配線基板１６のダイパッド部（チップ搭載部）１７に、集積回路が形成された半導体チップ１が搭載されている。このダイパッド部１７は、表層配線である主面側の金属配線１８からなる。また、ダイパッド部１７の周辺には放射状に接続パッド１９が配置されており、接続パッド１９の先端がダイパッド部１７に対して対向している。この接続パッド１９は、表層配線である主面側の金属配線（配線部材）１８からなる。また、半導体チップ１の表面に形成されている電極３と接続パッド１９とがワイヤ５で接続されている。また、主面側の金属配線１８は、貫通ビア２０を介して、底面側の金属配線１８に電気的に接続している。また、樹脂封止体２１が、少なくとも半導体チップ１、ダイパッド部１７、ワイヤ５および表層配線（配線部材）のワイヤ５との接続部分（接続パッド１９）を樹脂封止している。また、底面には半田ボール２２が形成されており、この半田ボール２２は、底面側の金属配線１８に電気的に接続している。また、底面上の金属配線１８が形成されていない領域には、レジスト２３が形成されている。   This semiconductor device is a BGA type semiconductor device, as shown in FIG. 11, made of a resin base material and having a die pad portion of a wiring substrate 16 having metal wiring 18 on at least a main surface and a bottom surface opposite to the main surface ( A semiconductor chip 1 on which an integrated circuit is formed is mounted on a chip mounting portion) 17. The die pad portion 17 includes a metal wiring 18 on the main surface side that is a surface layer wiring. Further, the connection pads 19 are arranged radially around the die pad portion 17, and the tips of the connection pads 19 face the die pad portion 17. The connection pad 19 includes a metal wiring (wiring member) 18 on the main surface side which is a surface layer wiring. Further, the electrode 3 formed on the surface of the semiconductor chip 1 and the connection pad 19 are connected by a wire 5. Further, the metal wiring 18 on the main surface side is electrically connected to the metal wiring 18 on the bottom surface side through the through via 20. Further, the resin sealing body 21 is resin-sealing at least a connection portion (connection pad 19) of the semiconductor chip 1, the die pad portion 17, the wire 5 and the surface layer wiring (wiring member) with the wire 5. A solder ball 22 is formed on the bottom surface, and the solder ball 22 is electrically connected to the metal wiring 18 on the bottom surface side. Further, a resist 23 is formed in a region on the bottom surface where the metal wiring 18 is not formed.

この半導体装置は、前述した実施の形態１と同様に、半導体チップ１上の少なくとも１個の電極３に２本のワイヤ５の一端がボールボンディング法により重ねて接続され、その２本のワイヤ５の他端が同一の接続パッド１９（配線部材）にウェッジボンディング法により接続されている点で、従来のものと異なる。   In this semiconductor device, as in the first embodiment, one end of two wires 5 are overlapped and connected to at least one electrode 3 on the semiconductor chip 1 by a ball bonding method, and the two wires 5 are connected. The other end is different from the conventional one in that it is connected to the same connection pad 19 (wiring member) by the wedge bonding method.

また、この半導体装置は、半導体装置の構成材料の一つである配線材料がリードフレームではなく配線基板であるという点のみで、前述した実施の形態１〜４と異なる。よって、前述した実施の形態１〜４におけるインナーリードを接続ランド（配線部材）に置き換えることで、前述した実施の形態１〜４における半導体装置と同様の構造を有する半導体装置を実施することができる。   Further, this semiconductor device is different from the first to fourth embodiments described above only in that the wiring material which is one of the constituent materials of the semiconductor device is not a lead frame but a wiring board. Therefore, by replacing the inner leads in the first to fourth embodiments described above with connection lands (wiring members), a semiconductor device having the same structure as the semiconductor device in the first to fourth embodiments described above can be implemented. .

すなわち、ＢＧＡ型の半導体装置において、実施の形態１と同様に、同一の電極に２本のワイヤを重ねて接続することができる（図３を参照）。また、その際、実施の形態１と同様に、ボールの下面に平坦面を形成してもよいし（図４を参照）、第２ボンディング工程においてボールボンディングを行う部分に直上から加圧ツールを押し当てて該部分を押し潰してもよい（図５、６を参照）。   That is, in the BGA type semiconductor device, two wires can be overlapped and connected to the same electrode as in the first embodiment (see FIG. 3). At that time, as in the first embodiment, a flat surface may be formed on the lower surface of the ball (see FIG. 4), or a pressure tool is applied to the portion where ball bonding is performed in the second bonding step. The portion may be crushed by pressing (see FIGS. 5 and 6).

また、ＢＧＡ型の半導体装置において、実施の形態２と同様に、半導体チップ上の少なくとも１個の電極に複数本のワイヤの一端をボールボンディング法により重ねて接続することができる（図７を参照）。   Further, in the BGA type semiconductor device, as in the second embodiment, one end of a plurality of wires can be overlapped and connected to at least one electrode on the semiconductor chip by a ball bonding method (see FIG. 7). ).

また、ＢＧＡ型の半導体装置において、実施の形態３と同様に、半導体チップ上の少なくとも１個の電極からの複数本のワイヤの他端を、同一の接続パッド（配線部材）上の同一の接続点に、バンプを介して、ウェッジボンディング法により重ねて接続することができる（図８を参照）。   In the BGA type semiconductor device, as in the third embodiment, the other ends of the plurality of wires from at least one electrode on the semiconductor chip are connected to the same connection pad (wiring member). It can be connected to the point by bump bonding via the bump bonding method (see FIG. 8).

また、パッケージ内に複数の半導体チップが内蔵されたＢＧＡ型の半導体装置において、実施の形態４と同様に、同一の電極からの複数本のワイヤをそれぞれ異なる接続対象部材に接続することができる（図９、１０を参照）。   Further, in the BGA type semiconductor device in which a plurality of semiconductor chips are incorporated in a package, a plurality of wires from the same electrode can be connected to different connection target members as in the fourth embodiment ( (See FIGS. 9 and 10).

したがって、ＢＧＡに代表される配線基板を配線材料に使用した半導体装置においても、低コストで高集積・高品質な半導体装置を提供することができる。   Therefore, even in a semiconductor device using a wiring board typified by BGA as a wiring material, a highly integrated and high quality semiconductor device can be provided at low cost.

（実施の形態６）
以下、本発明の実施の形態６について、図面を参照しながら説明する。図１２は本発明の実施の形態６に係る半導体装置の断面図、図１３（ａ）は同半導体装置のワイヤボンディング部分の内部構造を説明するための上面図、図１３（ｂ）は同半導体装置のワイヤボンディング部分の内部構造を説明するための断面図である。但し、前述した実施の形態１〜５にて説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 6)
Embodiment 6 of the present invention will be described below with reference to the drawings. 12 is a cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention, FIG. 13A is a top view for explaining the internal structure of the wire bonding portion of the semiconductor device, and FIG. 13B is the same semiconductor. It is sectional drawing for demonstrating the internal structure of the wire bonding part of an apparatus. However, the same members as those described in the first to fifth embodiments are denoted by the same reference numerals, and description thereof is omitted.

この半導体装置は、配線基板の同一の接続パッド（配線部材）に、２本のワイヤの一端がボールボンディング法により重ねて接続されており、それらのワイヤがそれぞれ異なる半導体チップ上の電極に接続されている点で、前述した実施の形態５と異なる。   In this semiconductor device, one end of two wires is overlapped and connected to the same connection pad (wiring member) of a wiring board by a ball bonding method, and these wires are connected to electrodes on different semiconductor chips, respectively. This is different from the fifth embodiment described above.

すなわち本実施の形態６では、図１２および図１３に示すように、同一の接続パッド１９に２本のワイヤ５ａ、５ｂの一端の接続部が重ねて接続されており、それらの接続部が、ボールボンディング法特有の、厚みのあるコイン状に押しつぶされた突起部のほぼ中央からワイヤが導出される形状に形成されている。また、ダイパッド部（チップ搭載部）１７には、垂直方向に積層された２個の半導体チップ１ａ、１ｂが搭載されている。そして、ワイヤ５ａの他端が、下方の半導体チップ１ｂの電極３ｂに、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されており、ワイヤ５ｂの他端が、上方の半導体チップ１ａの電極３ａに、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されている。   That is, in the sixth embodiment, as shown in FIGS. 12 and 13, the connection portions at one ends of the two wires 5 a and 5 b are overlapped and connected to the same connection pad 19, and these connection portions are It is formed in a shape in which the wire is led out from almost the center of the protruding portion crushed into a thick coin shape, which is unique to the ball bonding method. The die pad portion (chip mounting portion) 17 has two semiconductor chips 1a and 1b stacked in the vertical direction. The other end of the wire 5a is connected to the electrode 3b of the lower semiconductor chip 1b in a crescent-like or elliptical shape without a thickness unique to the wedge bonding method, and the other end of the wire 5b is connected to the upper side. The semiconductor chip 1a is connected to the electrode 3a in a crescent or elliptical shape having no thickness peculiar to the wedge bonding method.

またここでは、キャピラリから突出したワイヤの先端にボールを形成し、そのボールを、第１ボンディング工程においてウェッジボンディングを行う部分（電極３ｂ）に圧着してバンプ１５を形成するバンプ形成工程を、ワイヤ５ａのウェッジボンディングを行う前に実行しておき、バンプ１５上にワイヤ５ａのウェッジボンディング側の接続部８ａを形成している。さらに、キャピラリから突出したワイヤの先端にボールを形成し、そのボールを、第２ボンディング工程においてウェッジボンディングを行う部分（電極３ａ）に圧着してバンプ１５を形成するバンプ形成工程を、ワイヤ５ｂのウェッジボンディングを行う前に実行しておき、バンプ１５上にワイヤ５ｂのウェッジボンディング側の接続部８ｂを形成している。   Also, here, a bump forming step is performed in which a ball is formed at the tip of the wire protruding from the capillary, and the ball is crimped to a portion (electrode 3b) where wedge bonding is performed in the first bonding step to form the bump 15. This is performed before the wedge bonding of 5a, and the connection portion 8a on the wedge bonding side of the wire 5a is formed on the bump 15. Further, a bump forming step of forming a bump 15 by forming a ball at the tip of the wire protruding from the capillary and pressing the ball to a portion (electrode 3a) where wedge bonding is performed in the second bonding step is performed. This is performed before the wedge bonding, and the connection portion 8b on the wedge bonding side of the wire 5b is formed on the bump 15.

続いて、同一の接続パッドに２本のワイヤを接続する方法について、図１４に示す工程断面図に沿って説明する。なお、ここでは、各ボンディング工程における接続対象部材である半導体チップ１ａ、１ｂの電極３ａ、３ｂの各々に予めランド１５が形成されている場合について説明するが、ランド１５を形成するタイミングは、各ボンディング工程におけるウェッジボンディングの実行前であればよい。   Next, a method for connecting two wires to the same connection pad will be described with reference to a process cross-sectional view shown in FIG. In addition, although the case where the land 15 is previously formed in each of the electrodes 3a and 3b of the semiconductor chips 1a and 1b, which are connection target members in each bonding process, will be described here. It may be before execution of wedge bonding in the bonding process.

まず、図１４（ａ）に示すように、ワイヤ供給装置であるキャピラリ９の先端から突出したワイヤ５ａの先端とトーチ１０との間で放電を行い、スパークによりボール１１ａを形成する。   First, as shown in FIG. 14A, electric discharge is performed between the tip of the wire 5a protruding from the tip of the capillary 9 as a wire supply device and the torch 10, and a ball 11a is formed by spark.

次に図１４（ｂ）〜図１４（ｄ）に示すように、配線基板１６の接続パッド１９にボール１１ａを圧着して（ボールボンディング）、ボールボンディング側の接続部７ａを形成する。その後、図１４（ｅ）〜図１４（ｇ）に示すように、ワイヤ５ａを水平方向に折り曲げて引き出し、ワイヤ５ａが所定の軌跡に沿って配線されるようにキャピラリ９を移動させ、接続対象部材である半導体チップ１ｂの電極３ｂ上に形成したランド１５にワイヤ５ａをこすり付けて（ウェッジボンディング）、ウェッジボンディング側の接続部８ａを形成する。   Next, as shown in FIGS. 14B to 14D, the balls 11a are pressure-bonded to the connection pads 19 of the wiring board 16 (ball bonding) to form the connection portions 7a on the ball bonding side. Thereafter, as shown in FIGS. 14 (e) to 14 (g), the wire 5a is bent in the horizontal direction and pulled out, and the capillary 9 is moved so that the wire 5a is routed along a predetermined trajectory. The wire 5a is rubbed (wedge bonding) on the land 15 formed on the electrode 3b of the semiconductor chip 1b, which is a member, to form the connection portion 8a on the wedge bonding side.

以上の第１ボンディング工程を行った後、第２ボンディング工程を行う。すなわち、まず、図１４（ｈ）に示すように、キャピラリ９の先端から突出したワイヤ５ｂの先端とトーチ１０との間で放電を行い、スパークによりボール１１ｂを形成する。   After performing the first bonding step, the second bonding step is performed. That is, first, as shown in FIG. 14 (h), discharge is performed between the tip of the wire 5b protruding from the tip of the capillary 9 and the torch 10, and a ball 11b is formed by spark.

次に図１４（ｉ）に示すように、接続部７ａ（第１ボンディング工程においてボールボンディングを行った部分）に直上からボール１１ｂを圧着して（ボールボンディング）、ボールボンディング側の接続部７ｂを形成する。その後、図１４（ｊ）〜図１４（ｌ）に示すように、ワイヤ５ｂを垂直方向に引き出して折り曲げ、ワイヤ５ｂが所定の軌跡に沿って配線されるようにキャピラリ９を移動させ、接続対象部材である半導体チップ１ａの電極３ａ上に形成したランド１５にワイヤ５ｂをこすり付けて（ウェッジボンディング）、ウェッジボンディング側の接続部８ｂを形成する。   Next, as shown in FIG. 14 (i), the ball 11b is pressure-bonded to the connecting portion 7a (the portion where the ball bonding is performed in the first bonding step) from directly above (ball bonding), and the connecting portion 7b on the ball bonding side is connected. Form. Thereafter, as shown in FIGS. 14 (j) to 14 (l), the wire 5b is pulled out and bent in the vertical direction, and the capillary 9 is moved so that the wire 5b is routed along a predetermined locus. The wire 5b is rubbed (wedge bonding) on the land 15 formed on the electrode 3a of the semiconductor chip 1a, which is a member, to form the connection portion 8b on the wedge bonding side.

このように第１および第２ボンディング工程を行うことで、同一の接続パッド（配線部材）に２本のワイヤの一端をボールボンディング法により重ねて接続することができる。なお、複数本のワイヤの一端を重ねて接続する際に、実施の形態１と同様に、ボールの下面に平坦面を形成してもよいし（図４を参照）、第２ボンディング工程においてボールボンディングを行う部分に直上から加圧ツールを押し当てて該部分を押し潰してもよい（図５、６を参照）。   By performing the first and second bonding steps in this way, one end of two wires can be overlapped and connected to the same connection pad (wiring member) by a ball bonding method. In addition, when one end of a plurality of wires is overlapped and connected, a flat surface may be formed on the lower surface of the ball as in the first embodiment (see FIG. 4), or in the second bonding step A pressing tool may be pressed onto the portion to be bonded from directly above to crush the portion (see FIGS. 5 and 6).

以上のように、この半導体装置は、配線基板の同一の接続パッド（配線部材）に複数本のワイヤの一端がボールボンディング法により重ねて接続されており、その同一の接続パッドからのワイヤがそれぞれ異なる接続対象部材に接続されている点で、従来のものと異なる。   As described above, in this semiconductor device, one end of a plurality of wires is overlapped and connected to the same connection pad (wiring member) of the wiring board by the ball bonding method, and the wires from the same connection pad are respectively connected. It is different from the conventional one in that it is connected to a different connection object member.

なお、実施の形態２と同様に、同一の接続パッドに複数本のワイヤの一端をボールボンディング法により重ねて接続することができる（図７を参照）。また、実施の形態３と同様に、同一の接続パッドからの複数本のワイヤの他端を、同一の半導体チップ上の同一の電極、または配線基板上の他の接続パッドに、バンプを介して、ウェッジボンディング法により重ねて接続することができる（図８を参照）。   As in the second embodiment, one end of a plurality of wires can be overlapped and connected to the same connection pad by a ball bonding method (see FIG. 7). Similarly to the third embodiment, the other ends of the plurality of wires from the same connection pad are connected to the same electrode on the same semiconductor chip or other connection pads on the wiring board via bumps. And can be connected by overlapping by the wedge bonding method (see FIG. 8).

本実施の形態６によれば、ＢＧＡに代表される配線基板を配線材料に使用した半導体装置において配線基板上のワイヤ接続部の面積を容易に縮小することができ、低コストで高高品質な半導体装置を提供することができる。   According to the sixth embodiment, the area of the wire connection portion on the wiring board can be easily reduced in a semiconductor device using a wiring board typified by BGA as a wiring material. A semiconductor device can be provided.

（実施の形態７）
以下、本発明の実施の形態７について、図面を参照しながら説明する。図１５は本発明の実施の形態７に係る半導体装置の断面図、図１６（ａ）は同半導体装置のワイヤボンディング部分の内部構造を説明するための上面図、図１６（ｂ）は同半導体装置のワイヤボンディング部分の内部構造を説明するための断面図である。但し、前述した実施の形態１〜６にて説明した部材と同一の部材には同一符号を付して、説明を省略する。 (Embodiment 7)
Embodiment 7 of the present invention will be described below with reference to the drawings. 15 is a cross-sectional view of the semiconductor device according to the seventh embodiment of the present invention, FIG. 16A is a top view for explaining the internal structure of the wire bonding portion of the semiconductor device, and FIG. It is sectional drawing for demonstrating the internal structure of the wire bonding part of an apparatus. However, the same members as those described in the first to sixth embodiments are denoted by the same reference numerals, and the description thereof is omitted.

この半導体装置は、ＱＦＮ（クワッド・フラット・ノンリード・パッケージ）型またはＳＯＮ（スモール・アウトライン・ノンリード・パッケージ）型の半導体装置であり、図１５および図１６に示すように、垂直方向に積層された半導体チップ１ａ、１ｂがリードフレームのダイパッド部（チップ搭載部）２５に搭載されている。また、ダイパッド部２５の周辺には放射状にリードフレームのインナーリード（リード）２６が配置されており、それらのインナーリード２６の先端がダイパッド部２５に対して対向している。また、半導体チップ１ａ、１ｂの表面に形成されている電極３ａ、３ｂとインナーリード（リード）２６とがワイヤ５で接続されている。また、半導体チップ１、ダイパッド部２５、ワイヤ５、インナーリード２６が一括して樹脂封止体６により樹脂封止され、インナーリード２６の下面は樹脂封止体６の下面から露出している。   This semiconductor device is a QFN (quad flat non-lead package) type or SON (small outline non-lead package) type semiconductor device, and is stacked in the vertical direction as shown in FIGS. Semiconductor chips 1a and 1b are mounted on a die pad portion (chip mounting portion) 25 of the lead frame. In addition, inner leads (leads) 26 of the lead frame are radially arranged around the die pad portion 25, and the tips of the inner leads 26 face the die pad portion 25. Further, the electrodes 3 a and 3 b formed on the surfaces of the semiconductor chips 1 a and 1 b and the inner leads (leads) 26 are connected by wires 5. Further, the semiconductor chip 1, the die pad portion 25, the wire 5, and the inner lead 26 are collectively sealed with the resin sealing body 6, and the lower surface of the inner lead 26 is exposed from the lower surface of the resin sealing body 6.

この半導体装置は、配線材料が配線基板ではなくリードフレームであるという点のみで、前述した実施の形態６と異なる。すなわち本実施の形態７では、図１５および図１６に示すように、同一のインナーリード（リード）２６に２本のワイヤ５ａ、５ｂの一端の接続部が重ねて接続されており、それらの接続部が、ボールボンディング法特有の、厚みのあるコイン状に押しつぶされた突起部のほぼ中央からワイヤが導出される形状に形成されている。そして、ワイヤ５ａの他端が、下方の半導体チップ１ｂの電極３ｂに、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されており、ワイヤ５ｂの他端が、上方の半導体チップ１ａの電極３ａに、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されている。   This semiconductor device differs from the above-described sixth embodiment only in that the wiring material is not a wiring board but a lead frame. That is, in the seventh embodiment, as shown in FIGS. 15 and 16, the connecting portions at one ends of the two wires 5 a and 5 b are overlapped and connected to the same inner lead (lead) 26, and their connection The portion is formed in a shape in which the wire is led out from substantially the center of the protruding portion crushed into a thick coin shape, which is unique to the ball bonding method. The other end of the wire 5a is connected to the electrode 3b of the lower semiconductor chip 1b in a crescent-like or elliptical shape without a thickness unique to the wedge bonding method, and the other end of the wire 5b is connected to the upper side. The semiconductor chip 1a is connected to the electrode 3a in a crescent or elliptical shape having no thickness peculiar to the wedge bonding method.

なお、このＱＦＮ型またはＳＯＮ型の半導体装置において、同一のインナーリード（リード）に複数本のワイヤを重ねて接続する際に、実施の形態１と同様に、ボールの下面に平坦面を形成してもよいし（図４を参照）、第２ボンディング工程においてボールボンディングを行う部分に直上から加圧ツールを押し当てて該部分を押し潰してもよい（図５、６を参照）。   In this QFN type or SON type semiconductor device, when a plurality of wires are overlapped and connected to the same inner lead (lead), a flat surface is formed on the lower surface of the ball as in the first embodiment. Alternatively (see FIG. 4), a pressure tool may be pressed from directly above the portion where ball bonding is performed in the second bonding step to crush the portion (see FIGS. 5 and 6).

また、このＱＦＮ型またはＳＯＮ型の半導体装置において、実施の形態２と同様に、同一のインナーリード（リード）に複数本のワイヤの一端をボールボンディング法により重ねて接続することができる（図７を参照）。   Further, in this QFN type or SON type semiconductor device, similarly to the second embodiment, one end of a plurality of wires can be overlapped and connected to the same inner lead (lead) by the ball bonding method (FIG. 7). See).

また、このＱＦＮ型またはＳＯＮ型の半導体装置において、実施の形態３と同様に、同一のインナーリード（リード）からの複数本のワイヤの他端を、同一の半導体チップ上の同一の電極、または他方のインナーリード（リード）に、バンプを介して、ウェッジボンディング法により重ねて接続することができる（図８を参照）。   Further, in this QFN type or SON type semiconductor device, as in the third embodiment, the other ends of a plurality of wires from the same inner lead (lead) are connected to the same electrode on the same semiconductor chip, or The other inner lead (lead) can be overlapped and connected via a bump by a wedge bonding method (see FIG. 8).

またここでは、ＱＦＮ型またはＳＯＮ型の半導体装置について説明したが、ＱＦＮ型またはＳＯＮ型の半導体装置と同様の内部構造を有するＱＦＰ型半導体装置などのリードフレームを用いた樹脂封止型半導体装置においても同様に、同一のリードに複数本のワイヤの一端をボールボンディング法により重ねて接続して、その同一のリードからのワイヤをそれぞれ異なる接続対象部材または同一の接続対象部材に接続することができる。   Although the QFN type or SON type semiconductor device has been described here, in a resin-encapsulated semiconductor device using a lead frame such as a QFP type semiconductor device having the same internal structure as the QFN type or SON type semiconductor device. Similarly, one end of a plurality of wires can be overlapped and connected to the same lead by the ball bonding method, and the wires from the same lead can be connected to different connection target members or the same connection target member, respectively. .

本実施の形態７によれば、ＱＦＮ、ＳＯＮ、ＱＦＰに代表されるリードフレームを配線材料に使用した半導体装置においてリード上のワイヤ接続部の面積を容易に縮小することができ、低コストで高品質な半導体装置を提供することができる。   According to the seventh embodiment, in a semiconductor device using a lead frame represented by QFN, SON, and QFP as a wiring material, the area of the wire connecting portion on the lead can be easily reduced, and the cost is high. A quality semiconductor device can be provided.

本発明にかかる半導体装置の製造方法、および半導体装置によれば、半導体チップ上の同一の電極又はリードフレームの同一のリードあるいは配線基板上の同一の表層配線に複数本のワイヤを接続する構造において、電極面積又はパッケージ面積を抑制することができ、高集積、高密度な半導体チップを用いた半導体パッケージを高品質かつコンパクトに構成でき、ＱＦＰやＢＧＡなどの半導体パッケージに有用である。   According to the method for manufacturing a semiconductor device and the semiconductor device according to the present invention, in the structure in which a plurality of wires are connected to the same electrode on the semiconductor chip or the same lead of the lead frame or the same surface layer wiring on the wiring board. The electrode area or the package area can be suppressed, and a semiconductor package using a highly integrated and high-density semiconductor chip can be configured with high quality and compactness, which is useful for semiconductor packages such as QFP and BGA.

本発明の実施の形態１に係る半導体装置の断面図Sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention 同実施の形態１に係る半導体装置のワイヤボンディング部分の内部構造を説明するための図The figure for demonstrating the internal structure of the wire bonding part of the semiconductor device which concerns on the same Embodiment 1 同実施の形態１に係る半導体装置のワイヤボンディング工程を説明するための工程断面図Process sectional drawing for demonstrating the wire bonding process of the semiconductor device which concerns on the same Embodiment 1 同実施の形態１に係る半導体装置のワイヤボンディング工程の他の例を説明するための工程断面図Process sectional view for explaining another example of the wire bonding process of the semiconductor device according to the first embodiment 同実施の形態１に係る半導体装置のワイヤボンディング工程の他の例を説明するための工程断面図Process sectional view for explaining another example of the wire bonding process of the semiconductor device according to the first embodiment 同実施の形態１に係る半導体装置のワイヤボンディング工程の他の例を説明するための工程断面図Process sectional view for explaining another example of the wire bonding process of the semiconductor device according to the first embodiment 本発明の実施の形態２に係る半導体装置のワイヤボンディング部分の内部構造を説明するための断面図Sectional drawing for demonstrating the internal structure of the wire bonding part of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体装置のワイヤボンディング部分の内部構造を説明するための断面図Sectional drawing for demonstrating the internal structure of the wire bonding part of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る半導体装置のワイヤボンディング部分の内部構造を説明するための図（その１）The figure for demonstrating the internal structure of the wire bonding part of the semiconductor device which concerns on Embodiment 4 of this invention (the 1) 同実施の形態４に係る半導体装置のワイヤボンディング部分の内部構造を説明するための図（その２）The figure for demonstrating the internal structure of the wire bonding part of the semiconductor device which concerns on the same Embodiment 4 (the 2) 本発明の実施の形態５に係る半導体装置の断面図Sectional drawing of the semiconductor device which concerns on Embodiment 5 of this invention. 本発明の実施の形態６に係る半導体装置の断面図Sectional drawing of the semiconductor device which concerns on Embodiment 6 of this invention. 同実施の形態６に係る半導体装置のワイヤボンディング部分の内部構造を説明するための図The figure for demonstrating the internal structure of the wire bonding part of the semiconductor device which concerns on the same Embodiment 6 同実施の形態６に係る半導体装置のワイヤボンディング工程を説明するための工程断面図Process sectional view for explaining the wire bonding process of the semiconductor device according to the sixth embodiment 本発明の実施の形態７に係る半導体装置の断面図Sectional drawing of the semiconductor device concerning Embodiment 7 of this invention 同実施の形態７に係る半導体装置のワイヤボンディング部分の内部構造を説明するための図The figure for demonstrating the internal structure of the wire bonding part of the semiconductor device based on the Embodiment 7 従来の一般的なＱＦＰ型半導体装置の断面図Sectional view of a conventional general QFP type semiconductor device 従来の一般的なＱＦＰ型半導体装置のワイヤボンディング部分の内部構造図Internal structure diagram of wire bonding part of conventional general QFP type semiconductor device 従来の一般的なＱＦＰ型半導体装置において同一のインナーリードに複数の電極からのワイヤを接続した状態を示す模式図Schematic diagram showing a state in which wires from a plurality of electrodes are connected to the same inner lead in a conventional general QFP type semiconductor device

符号の説明Explanation of symbols

１、１ａ、１ｂ 半導体チップ
２、２５ リードフレームのダイパッド部
３、３ａ、３ｂ 電極
４ リードフレームのリード
４ａ、２６ リードフレームのインナーリード
４ｂ リードフレームのアウターリード
５、５ａ、５ｂ、５ｃ ワイヤ
６、２１ 樹脂封止体
７ａ、７ｂ、７ｃ ボールボンディング側の接続部
８ａ、８ｂ、８ｃ ウェッジボンディング側の接続部
９ キャピラリ
１０ トーチ
１１ａ、１１ｂ ボール
１２ 平坦部
１３ 加圧ツール（円錐型）
１４ 加圧ツール（球面型）
１５ バンプ
１６ 配線基板
１７ 配線基板のダイパッド部
１８ 配線基板の金属配線
１９ 接続パッド
２０ 貫通ビア
２２ 半田ボール
２３ レジスト
２４ ダイパッドサポート 1, 1a, 1b Semiconductor chip 2, 25 Lead pad die pad 3, 3a, 3b Electrode 4 Lead frame lead 4a, 26 Lead frame inner lead 4b Lead frame outer lead 5, 5a, 5b, 5c Wire 6, 21 Resin sealing body 7a, 7b, 7c Connection part on ball bonding side 8a, 8b, 8c Connection part on wedge bonding side 9 Capillary 10 Torch 11a, 11b Ball 12 Flat part 13 Pressure tool (conical type)
14 Pressurizing tool (spherical type)
DESCRIPTION OF SYMBOLS 15 Bump 16 Wiring board 17 Die pad part of wiring board 18 Metal wiring of wiring board 19 Connection pad 20 Through-via 22 Solder ball 23 Resist 24 Die pad support

Claims (21)

ワイヤ供給装置から突出したワイヤの先端にボールを形成して、そのボールを半導体チップ上の電極に圧着するボールボンディングを行い、その後ワイヤ供給装置を移動させ、接続対象部材にウェッジボンディングを行う第１ボンディング工程と、
ワイヤ供給装置から突出したワイヤの先端にボールを形成して、そのボールを、前記第１ボンディング工程においてボールボンディングを行った部分に直上から圧着するボールボンディングを行い、その後ワイヤ供給装置を移動させ、前記第１ボンディング工程における接続対象部材又はその接続対象部材とは異なる接続対象部材にウェッジボンディングを行う第２ボンディング工程と、
を具備することを特徴とする半導体装置の製造方法。 A ball is formed on the tip of the wire protruding from the wire supply device, ball bonding is performed to press the ball against an electrode on the semiconductor chip, and then the wire supply device is moved to perform wedge bonding on the connection target member. Bonding process;
A ball is formed at the tip of the wire protruding from the wire supply device, and the ball is bonded to the portion where the ball bonding was performed in the first bonding step from directly above, and then the wire supply device is moved, A second bonding step of performing wedge bonding on a connection target member in the first bonding step or a connection target member different from the connection target member;
A method for manufacturing a semiconductor device, comprising: 請求項１記載の半導体装置の製造方法であって、前記第２ボンディング工程を２回以上繰り返し行い、前記電極に複数本のワイヤを接続させることを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second bonding step is repeated twice or more to connect a plurality of wires to the electrode. 請求項２記載の半導体装置の製造方法であって、繰り返し行う前記第２ボンディング工程に際し、前記第１ボンディング工程における接続対象部材に少なくとも１本のワイヤをウェッジボンディングにより接続させることを特徴とする半導体装置の製造方法。   3. The semiconductor device manufacturing method according to claim 2, wherein at least one wire is connected to a connection target member in the first bonding step by wedge bonding in the second bonding step that is repeatedly performed. Device manufacturing method. 請求項２記載の半導体装置の製造方法であって、繰り返し行う前記第２ボンディング工程に際し、前記第１ボンディング工程における接続対象部材とは異なる同一の接続対象部材に少なくとも２本のワイヤをウェッジボンディングにより接続させることを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 2, wherein at the time of the second bonding step to be repeated, at least two wires are connected to the same connection target member different from the connection target member in the first bonding step by wedge bonding. A method of manufacturing a semiconductor device, characterized by being connected. 請求項１記載の半導体装置の製造方法であって、ワイヤ供給装置から突出したワイヤの先端にボールを形成し、そのボールを、前記第１ボンディング工程ないし前記第２ボンディング工程においてウェッジボンディングを行う部分に圧着してバンプを形成するバンプ形成工程を具備し、前記第１ボンディング工程ないし前記第２ボンディング工程に際し、前記バンプにウェッジボンディングを行うことを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein a ball is formed at a tip of a wire protruding from the wire supply device, and the ball is subjected to wedge bonding in the first bonding step or the second bonding step. A method of manufacturing a semiconductor device, comprising: a bump forming step of forming a bump by pressure bonding to the bump, and performing wedge bonding on the bump during the first bonding step or the second bonding step. ワイヤ供給装置から突出したワイヤの先端にボールを形成して、そのボールを半導体チップの周囲に配置されたリードあるいは配線部材に圧着するボールボンディングを行い、その後ワイヤ供給装置を移動させ、接続対象部材にウェッジボンディングを行う第１ボンディング工程と、
ワイヤ供給装置から突出したワイヤの先端にボールを形成して、そのボールを、前記第１ボンディング工程においてボールボンディングを行った部分に直上から圧着するボールボンディングを行い、その後ワイヤ供給装置を移動させ、前記第１ボンディング工程における接続対象部材又はその接続対象部材とは異なる接続対象部材にウェッジボンディングを行う第２ボンディング工程と、
を具備することを特徴とする半導体装置の製造方法。 A ball is formed at the tip of the wire protruding from the wire supply device, and the ball is bonded to a lead or wiring member arranged around the semiconductor chip, and then the wire supply device is moved to connect the target member. A first bonding step in which wedge bonding is performed;
A ball is formed at the tip of the wire protruding from the wire supply device, and the ball is bonded to the portion where the ball bonding was performed in the first bonding step from directly above, and then the wire supply device is moved, A second bonding step of performing wedge bonding on a connection target member in the first bonding step or a connection target member different from the connection target member;
A method for manufacturing a semiconductor device, comprising: 請求項６記載の半導体装置の製造方法であって、前記第２ボンディング工程を２回以上繰り返し行い、前記リードあるいは前記配線部材に複数本のワイヤを接続させることを特徴とする半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, wherein the second bonding step is repeated twice or more to connect a plurality of wires to the lead or the wiring member. . 請求項７記載の半導体装置の製造方法であって、繰り返し行う前記第２ボンディング工程に際し、前記第１ボンディング工程における接続対象部材に少なくとも１本のワイヤをウェッジボンディングにより接続させることを特徴とする半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein at least one wire is connected to the connection target member in the first bonding step by wedge bonding in the second bonding step that is repeatedly performed. Device manufacturing method. 請求項７記載の半導体装置の製造方法であって、繰り返し行う前記第２ボンディング工程に際し、前記第１ボンディング工程における接続対象部材とは異なる同一の接続対象部材に少なくとも２本のワイヤをウェッジボンディングにより接続させることを特徴とする半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein at the time of the second bonding step performed repeatedly, at least two wires are connected to the same connection target member different from the connection target member in the first bonding step by wedge bonding. A method of manufacturing a semiconductor device, characterized by being connected. 請求項６記載の半導体装置の製造方法であって、ワイヤ供給装置から突出したワイヤの先端にボールを形成し、そのボールを、前記第１ボンディング工程ないし前記第２ボンディング工程においてウェッジボンディングを行う部分に圧着してバンプを形成するバンプ形成工程を具備し、前記第１ボンディング工程ないし前記第２ボンディング工程に際し、前記バンプにウェッジボンディングを行うことを特徴とする半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, wherein a ball is formed at the tip of the wire protruding from the wire supply device, and the ball is subjected to wedge bonding in the first bonding step or the second bonding step. A method of manufacturing a semiconductor device, comprising: a bump forming step of forming a bump by pressure bonding to the bump, and performing wedge bonding on the bump during the first bonding step or the second bonding step. 電極を有する半導体チップと、
前記半導体チップが搭載されるチップ搭載部と、
前記チップ搭載部の周囲に配置されるリード又は配線部材と、
前記半導体チップが有する前記電極と前記リード又は配線部材とを接続するワイヤと、
を備え、少なくとも前記半導体チップ、前記チップ搭載部、前記ワイヤおよび前記リード又は配線部材の前記ワイヤとの接続部分が樹脂封止された半導体装置であって、
前記半導体チップが有する前記電極のうちの少なくとも１個に、複数本の前記ワイヤの一端の接続部が重ねて接続されており、それらの接続部はボールボンディング法特有の、厚みのあるコイン状に押しつぶされた突起部のほぼ中央からワイヤが導出される形状に形成されていることを特徴とする半導体装置。 A semiconductor chip having electrodes;
A chip mounting portion on which the semiconductor chip is mounted;
Leads or wiring members arranged around the chip mounting portion;
A wire connecting the electrode of the semiconductor chip and the lead or wiring member;
A semiconductor device in which at least the semiconductor chip, the chip mounting portion, the wire and the connection portion of the lead or wiring member with the wire are sealed with a resin,
At least one of the electrodes of the semiconductor chip is connected to a connecting portion of one end of the plurality of wires in an overlapping manner, and these connecting portions are formed in a thick coin shape peculiar to the ball bonding method. A semiconductor device, wherein the wire is led out from substantially the center of the crushed protrusion. 請求項１１記載の半導体装置であって、前記半導体チップが有する前記電極に一端が重ねて接続された複数本の前記ワイヤのうちの少なくとも一部は、その他端が、同一の前記リード又は配線部材に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする半導体装置。   12. The semiconductor device according to claim 11, wherein at least a part of the plurality of wires connected at one end to the electrode of the semiconductor chip is the same at the other end. In addition, the semiconductor device is connected in a crescent or elliptical shape without a thickness peculiar to the wedge bonding method. 請求項１１記載の半導体装置であって、前記半導体チップを複数個備え、少なくとも１箇の前記半導体チップが有する少なくとも１箇の前記電極に一端が重ねて接続された複数本の前記ワイヤのうちの少なくとも一部は、その他端が、他方の前記半導体チップが有する電極に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする半導体装置。   12. The semiconductor device according to claim 11, wherein a plurality of the semiconductor chips are provided, and one end of the plurality of wires is connected to at least one of the electrodes of at least one of the semiconductor chips. 2. A semiconductor device, wherein at least a part of the other end is connected to an electrode of the other semiconductor chip in a crescent or elliptical shape having no thickness peculiar to the wedge bonding method. 請求項１１記載の半導体装置であって、前記半導体チップを複数個備え、少なくとも１箇の前記半導体チップが有する少なくとも１箇の前記電極に一端が重ねて接続された複数本の前記ワイヤの一部は、その他端が、他方の前記半導体チップが有する電極に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続され、他の一部は、その他端が、前記リード又は配線部材に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする半導体装置。   12. The semiconductor device according to claim 11, wherein a plurality of the semiconductor chips are provided, and a part of the plurality of wires each having one end overlapped and connected to at least one of the electrodes of the at least one semiconductor chip. The other end is connected to the electrode of the other semiconductor chip in the shape of a crescent or ellipse having no thickness peculiar to the wedge bonding method, and the other end is connected to the lead or the other end. A semiconductor device characterized in that it is connected to a wiring member in a crescent or elliptical shape without a thickness peculiar to the wedge bonding method. 前記チップ搭載部および前記リードは、金属板を加工して製作されるリードフレームの構成部材であることを特徴とする請求項１１記載の半導体装置。   12. The semiconductor device according to claim 11, wherein the chip mounting portion and the lead are constituent members of a lead frame manufactured by processing a metal plate. 前記チップ搭載部および前記配線部材は、配線基板の構成部材であることを特徴とする請求項１１記載の半導体装置。   12. The semiconductor device according to claim 11, wherein the chip mounting portion and the wiring member are constituent members of a wiring board. 電極を有する半導体チップと、
前記半導体チップが搭載されるチップ搭載部と、
前記チップ搭載部の周囲に配置されるリード又は配線部材と、
前記半導体チップが有する前記電極と前記リード又は配線部材とを接続するワイヤと、
を備え、少なくとも前記半導体チップ、前記チップ搭載部、前記ワイヤおよび前記リード又は配線部材の前記ワイヤとの接続部分が樹脂封止された半導体装置であって、
前記リード又は配線部材のうちの少なくとも１個に、複数本の前記ワイヤの一端の接続部が重ねて接続されており、それらの接続部はボールボンディング法特有の、厚みのあるコイン状に押しつぶされた突起部のほぼ中央からワイヤが導出される形状に形成されていることを特徴とする半導体装置。 A semiconductor chip having electrodes;
A chip mounting portion on which the semiconductor chip is mounted;
Leads or wiring members arranged around the chip mounting portion;
A wire connecting the electrode of the semiconductor chip and the lead or wiring member;
A semiconductor device in which at least the semiconductor chip, the chip mounting portion, the wire and the connection portion of the lead or wiring member with the wire are sealed with a resin,
At least one of the leads or the wiring member is connected to a connecting portion of one end of the plurality of wires, and these connecting portions are crushed into a thick coin shape peculiar to the ball bonding method. A semiconductor device characterized in that the wire is led out from substantially the center of the protruding portion. 請求項１７記載の半導体装置であって、前記リード又は配線部材に一端が重ねて接続された複数本の前記ワイヤの一部は、その他端が他方の前記リード又は配線部材に、ウェッジボンディング法特有の、厚みの無い三日月状または楕円状の形状をなして接続され、他の一部は、その他端が前記半導体チップが有する前記電極に、ウェッジボンディング法特有の、先端が厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする半導体装置。   18. The semiconductor device according to claim 17, wherein a part of the plurality of wires, one end of which is overlapped and connected to the lead or the wiring member, is unique to the wedge bonding method with the other end being the other lead or the wiring member. Are connected in the shape of a crescent or ellipse with no thickness, and the other part is a crescent shape with a thin tip at the tip, which is peculiar to the wedge bonding method or the other end of the electrode of the semiconductor chip. A semiconductor device which is connected in an elliptical shape. 請求項１７記載の半導体装置であって、前記半導体チップを複数個備え、前記リード又は配線部材に一端が重ねて接続された複数本の前記ワイヤのうちの少なくとも一部は、その他端が互いに異なる前記半導体チップの各々が有する前記電極に、ウェッジボンディング法特有の厚みの無い三日月状または楕円状の形状をなして接続されていることを特徴とする半導体装置。   18. The semiconductor device according to claim 17, wherein at least some of the plurality of wires each including a plurality of the semiconductor chips and having one end overlapped and connected to the lead or the wiring member are different from each other. A semiconductor device, characterized in that it is connected to the electrodes of each of the semiconductor chips in a crescent or elliptical shape without a thickness peculiar to the wedge bonding method. 前記チップ搭載部および前記リードは、金属板を加工して製作されるリードフレームの構成部材であることを特徴とする請求項１７記載の半導体装置。   The semiconductor device according to claim 17, wherein the chip mounting portion and the lead are constituent members of a lead frame manufactured by processing a metal plate. 前記チップ搭載部および前記配線部材は、配線基板の構成部材であることを特徴とする請求項１７記載の半導体装置。   18. The semiconductor device according to claim 17, wherein the chip mounting portion and the wiring member are constituent members of a wiring board.
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