WO2014132826A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
WO2014132826A1
WO2014132826A1 PCT/JP2014/053649 JP2014053649W WO2014132826A1 WO 2014132826 A1 WO2014132826 A1 WO 2014132826A1 JP 2014053649 W JP2014053649 W JP 2014053649W WO 2014132826 A1 WO2014132826 A1 WO 2014132826A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
semiconductor chip
semiconductor device
electrode terminal
semiconductor
Prior art date
Application number
PCT/JP2014/053649
Other languages
French (fr)
Japanese (ja)
Inventor
貴弘 杉村
浩史 野津
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Publication of WO2014132826A1 publication Critical patent/WO2014132826A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49425—Wedge bonds
    • H01L2224/49426—Wedge bonds on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49425—Wedge bonds
    • H01L2224/49427—Wedge bonds outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10254—Diamond [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device.
  • Non-Patent Document 1 a resin-encapsulated semiconductor device is known (see Non-Patent Document 1).
  • a semiconductor chip mounted on a die pad is connected to an electrode terminal via a wire.
  • the semiconductor chip may be connected to the source electrode terminal via a plurality of thin wires instead of a single thick wire.
  • the end portions of the plurality of wires can be distributed and arranged in the source electrode pads provided on the surface of the semiconductor chip, it is possible to suppress local concentration of current on the surface of the semiconductor chip. Further, the load applied to the semiconductor chip by ultrasonic waves or pressure during wire bonding can be dispersed on the surface of the semiconductor chip.
  • An object of the present application is to provide a semiconductor device capable of increasing the number of wirings for connecting a semiconductor chip to electrode terminals in a limited region.
  • a semiconductor device of the present application includes a semiconductor chip, a chip mounting substrate having a chip mounting surface on which the semiconductor chip is mounted, and electrode terminals electrically connected to the semiconductor chip via first and second wirings.
  • the second wiring is overlapped with and connected to the first wiring on at least one of the semiconductor chip and the electrode terminal.
  • FIG. 1 is a plan view schematically showing a semiconductor device according to a first embodiment. It is a figure which shows typically a part of semiconductor device seen from the X direction of FIG. It is a figure which shows typically a part of semiconductor device which concerns on 2nd Embodiment. It is a figure which shows typically the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows typically the semiconductor device which concerns on 4th Embodiment.
  • a semiconductor device of the present application includes a semiconductor chip, a chip mounting substrate having a chip mounting surface on which the semiconductor chip is mounted, and electrode terminals electrically connected to the semiconductor chip via first and second wirings.
  • the second wiring is overlapped with and connected to the first wiring on at least one of the semiconductor chip and the electrode terminal.
  • the second wiring is connected over the first wiring on at least one of the semiconductor chip and the electrode terminal, a region for connecting the second wiring becomes unnecessary. Therefore, the number of wirings between the semiconductor chip and the electrode terminals can be increased in a limited region.
  • the electrode terminal may be a source electrode terminal, an emitter electrode terminal, or an anode electrode terminal.
  • the material of the semiconductor chip may include a wide band gap semiconductor.
  • silicon allows only a small current to flow through a semiconductor chip, it is not necessary to use a large number of wires.
  • the current flowing through the semiconductor chip is larger than that in silicon, so that there is a high need to increase the number of wirings in order to suppress current concentration.
  • the wide band gap semiconductor it is difficult to increase the size of the semiconductor chip due to the manufacturing yield lower than that of silicon. For this reason, in the wide band gap semiconductor, a large number of wirings are connected to a small semiconductor chip. Therefore, it is particularly important to increase the number of wirings in the wide band gap semiconductor.
  • At least one of the first wiring and the second wiring may be a bonding ribbon.
  • connection stability between the first wiring and the second wiring can be improved.
  • the first wiring may be a bonding ribbon.
  • connection stability between at least one of the semiconductor chip and the electrode terminal, the first wiring, and the second wiring can be improved.
  • the material of the first wiring and the second wiring may include aluminum or copper.
  • FIG. 1 is a plan view schematically showing the semiconductor device according to the first embodiment.
  • FIG. 1 shows an XYZ orthogonal coordinate system.
  • FIG. 2 is a diagram schematically showing a part of the semiconductor device viewed from the X direction of FIG.
  • a semiconductor device 10 shown in FIGS. 1 and 2 is a resin-encapsulated semiconductor device.
  • the semiconductor device 10 includes a die pad 12 as a chip mounting substrate, a semiconductor chip (or semiconductor element) 14, and leads 20 as electrode terminals.
  • the semiconductor device 10 may include leads 16 and 18 as other electrode terminals.
  • the leads 16, 18, and 20 are arranged along the X direction.
  • the lead 16 is located between the leads 18 and 20.
  • the leads 16, 18, 20 and the die pad 12 may constitute a lead frame.
  • the semiconductor device 10 is a power semiconductor device used for a power source or the like, for example.
  • An example of the package form of the semiconductor device 10 is a general TO series. Examples of TO series include TO-247, TO-220, TO-263 (D2-PAK), and TO-252 (D-PAK).
  • the die pad 12 has a chip mounting surface 12a on which the semiconductor chip 14 is mounted.
  • the die pad 12 can be electrically connected to the semiconductor chip 14.
  • the die pad 12 has a plate shape, for example.
  • the chip mounting surface 12a is, for example, a rectangle.
  • Examples of the material of the die pad 12 include metals such as copper (Cu) and a copper alloy.
  • a through-hole 26 that penetrates the die pad 12 in the thickness direction can be formed in the die pad 12.
  • the through hole 26 is a hole through which a screw is passed when the semiconductor device 10 is fixed to another member by, for example, a screw.
  • the semiconductor chip 14 is mounted at a predetermined position on the chip mounting surface 12a.
  • Examples of the semiconductor chip 14 include transistors such as bipolar transistors, MOS-FETs, insulated gate bipolar transistors (IGBTs), and diodes.
  • the semiconductor chip 14 can be mounted on the chip mounting surface 12a via an adhesive layer 32 made of a material containing lead-containing metal solder, lead-free metal solder, conductive resin, or the like.
  • Examples of the material of the semiconductor chip 14 include a wide band gap semiconductor, silicon and other semiconductors.
  • a wide band gap semiconductor has a band gap larger than that of silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and diamond.
  • the inner end of the lead 16 is mechanically and integrally connected to the die pad 12. Since the die pad 12 has conductivity, the lead 16 and the die pad 12 are electrically connected. Examples of the material of the lead 16 include the same material as that of the die pad 12.
  • the lead 18 is connected to the semiconductor chip 14 via the wiring 30.
  • One end of the wiring 30 is connected to the electrode pad GP of the semiconductor chip 14.
  • the other end of the wiring 30 is connected to the inner end of the lead 18.
  • the lead 20 is electrically connected to the semiconductor chip 14 via the first to fourth wirings 22a to 22d.
  • the wirings 22a to 22d include first end portions E1a to E1d that are electrically connected to the electrode pads SP of the semiconductor chip 14, and second end portions E2a to E2a that are electrically connected to the inner end portions of the leads 20. And E2d.
  • the second wiring 22b is overlaid on the first wiring 22a and connected, and the fourth wiring 22d is overlaid on the third wiring 22c.
  • the ends E1a to E1d of the wirings 22a to 22d are distributed on the surface of the electrode pad SP.
  • the end E1a of the wiring 22a can be disposed at a position closer to the lead 20 than the end E1b of the wiring 22b.
  • the end E1c of the wiring 22c can be disposed at a position closer to the lead 20 than the end E1d of the wiring 22d.
  • the ends E1a and E1c are arranged in this order in the X direction.
  • the ends E1b and E1d are arranged in this order in the X direction.
  • the end E2a of the wiring 22a is disposed between the end E2b of the wiring 22b and the lead 20.
  • the end E2c of the wiring 22c is disposed between the end E2d of the wiring 22d and the lead 20.
  • the end E2a of the wiring 22a can be disposed at a position closer to the semiconductor chip 14 than the end E2c of the wiring 22c.
  • the ends E2a and E2c are arranged in this order in the X direction.
  • the lead 16 corresponds to the drain electrode terminal
  • the lead 18 corresponds to the gate electrode terminal
  • the lead 20 corresponds to the source electrode terminal
  • the electrode pad GP corresponds to the gate electrode pad.
  • the electrode pad SP corresponds to the source electrode pad.
  • the semiconductor chip 14 includes an IGBT
  • the lead 16 corresponds to the collector electrode terminal
  • the lead 18 corresponds to the gate electrode terminal
  • the lead 20 corresponds to the emitter electrode terminal
  • the electrode pad GP corresponds to the gate electrode pad
  • the electrode pad SP corresponds to the emitter electrode pad.
  • the lead 16 corresponds to the cathode electrode terminal
  • the lead 20 corresponds to the anode electrode terminal
  • the electrode pad SP corresponds to the anode electrode pad.
  • the semiconductor device 10 does not include the lead 18 and the electrode pad GP.
  • Examples of the material of the leads 18 and 20 include metals such as copper and copper alloys.
  • the wirings 22a to 22d and 30 may be wires or bonding ribbons.
  • the cross-sectional shapes of the wirings 22a to 22d and 30 are, for example, circular.
  • the diameters of the wirings 22a to 22d and 30 are, for example, 100 to 500 ⁇ m.
  • the diameter of the wiring 22a may be larger than the diameter of the wiring 22b. This facilitates wire bonding of the wiring 22b on the wiring 22a.
  • the contact area between the wiring 22a and the lead 20 is, for example, 50,000 to 2500,000 ⁇ m 2 .
  • Examples of the material of the wirings 22a to 22d and 30 include metals such as aluminum, gold, and copper.
  • the wirings 22a to 22d and 30 are electrically connected to the leads 18 and 20 and the semiconductor chip 14 by wire bonding using, for example, ultrasonic waves or pressure.
  • the die pad 12 and the semiconductor chip 14 can be sealed by the resin portion 24.
  • Inner ends of the leads 16, 18, and 20 are fixed to the resin portion 24.
  • the portion inside the resin portion 24 is a so-called inner lead portion.
  • the portion outside the resin portion 24 is an outer lead portion.
  • An example of the outer shape of the resin portion 24 is a substantially rectangular parallelepiped.
  • the material of the resin portion 24 include thermoplastic resins such as polyphenylene sulfide resin (PPS resin) and liquid crystal polymer.
  • the resin portion 24 can be formed by molding the die pad 12 and the semiconductor chip 14 with a thermoplastic resin.
  • a through hole 28 is formed in the resin portion 24 with the central axis of the through hole 26 of the die pad 12 as the central axis.
  • the through hole 28 is a hole through which a screw is passed in the case of screwing or the like, like the through hole 26.
  • the diameter of the through hole 28 is smaller than the diameter of the through hole 26.
  • the bottom surface 12f of the die pad 12 opposite to the chip mounting surface 12a can be opened.
  • the bottom surface 12 f may be a surface that is not covered by the resin portion 24.
  • the bottom surface 12f can function as a heat dissipation surface.
  • the second wiring 22b is overlapped and connected to the first wiring 22a on the lead 20
  • an area for connecting the second wiring 22b is not necessary.
  • the fourth wiring 22d is overlapped and connected to the third wiring 22c, an area for connecting the fourth wiring 22d is not necessary. Therefore, the number of wirings 22a to 22d between the semiconductor chip 14 and the lead 20 can be increased in a limited region of the lead 20. As a result, a large current can flow from the lead 20 to the semiconductor chip 14. Furthermore, the lead 20 can be reduced in size.
  • the lead 20 is a source electrode terminal, an emitter electrode terminal, or an anode electrode terminal
  • a large current flows between the semiconductor chip 14 and the lead 20.
  • the current flowing through the wirings 22a to 22d can be dispersed by increasing the number of wirings 22a to 22d between the semiconductor chip 14 and the leads 20.
  • FIG. 3 is a diagram schematically showing a part of the semiconductor device according to the second embodiment.
  • FIG. 3 corresponds to FIG.
  • the semiconductor device according to the second embodiment has the same configuration as that of the semiconductor device 10 except that the arrangement of the wirings 22a to 22d is different.
  • the semiconductor device according to the second embodiment on the semiconductor chip 14, the second wiring 22b is overlaid on the first wiring 22a and the fourth wiring 22d is overlaid on the third wiring 22c. Is done.
  • the end E1a of the wiring 22a is disposed between the end E1b of the wiring 22b and the semiconductor chip 14.
  • the end E1c of the wiring 22c is disposed between the end E1d of the wiring 22d and the semiconductor chip 14.
  • the ends E2a to E2d of the wirings 22a to 22d are arranged in this order in the X direction.
  • the semiconductor device since the second wiring 22b is connected to the first wiring 22a in an overlapping manner on the semiconductor chip 14, an area for connecting the second wiring 22b is unnecessary. Become. Since the fourth wiring 22d is overlapped and connected to the third wiring 22c, an area for connecting the fourth wiring 22d is not necessary. Therefore, the number of wirings 22a to 22d between the semiconductor chip 14 and the leads 20 can be increased in a limited region of the semiconductor chip 14. As a result, a large current can flow from the lead 20 to the semiconductor chip 14. Furthermore, the semiconductor chip 14 can be reduced in size.
  • FIG. 4 is a diagram schematically showing a semiconductor device according to the third embodiment.
  • FIG. 4 corresponds to FIG.
  • the semiconductor device according to the third embodiment has the same configuration as that of the semiconductor device 10 except that a bonding ribbon 22e is provided instead of the first wiring 22a and the third wiring 22c.
  • the bonding ribbon 22e has a first end E1e electrically connected to the electrode pad SP of the semiconductor chip 14 and a second end E2e electrically connected to the inner end of the lead 20. May be.
  • the second wiring 22b and the fourth wiring 22d are overlapped and connected to the bonding ribbon 22e.
  • the end E2e of the bonding ribbon 22e is disposed between the end 20E2b of the wiring 22b and the end E2d of the wiring 22d and the lead 20.
  • the semiconductor device according to the third embodiment can obtain at least the same effects as the semiconductor device 10. Furthermore, connection stability among the lead 20, the bonding ribbon 22e, and the wirings 22b and 22d can be improved. It is easy to wire-bond the wirings 22b and 22d on the bonding ribbon 22e.
  • FIG. 5 is a diagram schematically showing a semiconductor device according to the fourth embodiment.
  • a semiconductor device 110 shown in FIG. 5 is a case-type semiconductor device.
  • the semiconductor device 110 includes a wiring substrate 40 as a chip mounting substrate, a semiconductor chip 14, electrode terminals 420, and a case 52.
  • the wiring board 40 has a chip mounting surface 46a on which the semiconductor chip 14 is mounted.
  • the semiconductor chip 14 is mounted on the chip mounting surface 46 a via the adhesive layer 32.
  • the electrode terminal 420 is connected to the semiconductor chip 14 via the first and second wirings 22a and 22b.
  • the second wiring 22b is overlapped with and connected to the first wiring 22a.
  • the wiring substrate 40 includes an insulating substrate 42, a wiring layer 46 provided on the surface of the insulating substrate 42, and a heat dissipation layer 44 provided on the back surface of the insulating substrate 42.
  • Examples of the material of the wiring layer 46 include metals such as copper and copper alloys.
  • An example of the material of the insulating substrate 42 includes ceramic such as alumina.
  • Examples of the material of the heat dissipation layer 44 include metals such as copper and copper alloys.
  • the heat dissipation layer 44 is bonded to the heat sink 50 via an adhesive layer 48 including, for example, solder.
  • An example of the material of the heat sink 50 includes a metal.
  • the semiconductor chip 14 and the wiring board 40 are accommodated in the case 52.
  • the case 52 has a cylindrical shape, for example.
  • One opening of the case 52 can be sealed by the heat sink 50.
  • the other opening of the case 52 can be sealed by a lid 54.
  • the material of the case 52 include resins such as engineering plastics such as polybutylene terephthalate (PBT) or polyphenylene sulfide (PPS) resin.
  • An example of the material of the lid 54 includes a thermoplastic resin.
  • a gel 56 such as a silicone gel may be injected for stress relaxation.
  • the semiconductor device 110 may include an electrode terminal 418.
  • the electrode terminal 418 is connected to the semiconductor chip 14 via the wiring 30.
  • the electrode terminal 418 and the electrode terminal 420 are attached to the inner wall of the case 52.
  • the electrode terminal 418 and the electrode terminal 420 extend along the inner wall of the case 52 and project outside through an opening formed in the lid 54.
  • the electrode terminal 418 and the electrode terminal 420 can be manufactured by press working or the like.
  • the electrode terminal 418 corresponds to the gate electrode terminal, and the electrode terminal 420 corresponds to the source electrode terminal.
  • the drain electrode terminal is not shown.
  • the electrode terminal 418 corresponds to a gate electrode terminal, and the electrode terminal 420 corresponds to an emitter electrode terminal.
  • the collector electrode terminal is not shown.
  • the electrode terminal 420 corresponds to the anode electrode terminal.
  • the cathode electrode terminal is not shown. In this case, the semiconductor device 110 does not include the electrode terminal 418.
  • the semiconductor device 10 of FIGS. 1 and 2 may not include the wirings 22c and 22d, or may include a further wiring provided between the semiconductor chip 14 and the lead 20. On the lead 20, a further wiring may be overlapped and connected on the second wiring 22b and the fourth wiring 22d.
  • a plurality of wirings 30 may be provided between the electrode pad GP and the lead 18.
  • a further wiring 30 may be overlaid on the wiring 30, or on the lead 18, the further wiring 30 may be overlaid on the wiring 30.
  • the second wiring 22 b is also connected to the first wiring 22 a so as to overlap the lead 20 on the lead 20.
  • the wiring 22d may be overlapped with and connected to the third wiring 22c.
  • the second wiring 22b and the fourth wiring 22d may be replaced with a bonding ribbon.
  • the bonding ribbon 22e may be replaced with the first wiring 22a and the third wiring 22c.
  • the bonding ribbon is overlapped and connected on the first wiring 22a and the third wiring 22c. Even in such a case, the connection stability between the bonding ribbon and the first wiring 22a and the third wiring 22c can be improved.
  • the wirings 22b and 22d may be overlapped on and connected to the bonding ribbon 22e.
  • the wiring 22b may be overlapped and connected on the wiring 22a on the semiconductor chip 14 as in the second embodiment. Similar to the third embodiment, at least one of the wirings 22a and 22b may be replaced with a bonding ribbon.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device is provided with a semiconductor chip, a chip-equipped substrate having a chip-equipped surface on which the semiconductor chip is equipped, and an electrode terminal electrically connected to the semiconductor chip via first and second lines. Upon the semiconductor chip and/or the electrode terminal, a second line is connected upon the first line so as to overlap.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.
　半導体装置の例として、樹脂封止型の半導体装置が知られている（非特許文献１参照）。このような半導体装置では、ダイパッドに搭載された半導体チップが、ワイヤを介して電極端子に接続される。 As an example of a semiconductor device, a resin-encapsulated semiconductor device is known (see Non-Patent Document 1). In such a semiconductor device, a semiconductor chip mounted on a die pad is connected to an electrode terminal via a wire.
　半導体チップは、１本の太いワイヤの代わりに複数の細いワイヤを介してソース電極端子に接続されることがある。この場合、複数のワイヤの端部が半導体チップの表面に設けられたソース電極パッドおいて分散配置され得るので、半導体チップの表面において局所的に電流が集中することを抑制できる。また、ワイヤボンディングの際に超音波又は加圧等により半導体チップが受ける荷重を半導体チップの表面において分散させることができる。 The semiconductor chip may be connected to the source electrode terminal via a plurality of thin wires instead of a single thick wire. In this case, since the end portions of the plurality of wires can be distributed and arranged in the source electrode pads provided on the surface of the semiconductor chip, it is possible to suppress local concentration of current on the surface of the semiconductor chip. Further, the load applied to the semiconductor chip by ultrasonic waves or pressure during wire bonding can be dispersed on the surface of the semiconductor chip.
　上記半導体装置では、半導体チップ及びソース電極端子において、ワイヤを接続するための領域がワイヤ毎に必要であるので、限られた領域に接続されるワイヤの本数を増やすことは難しい。 In the semiconductor device, since a region for connecting wires is required for each wire in the semiconductor chip and the source electrode terminal, it is difficult to increase the number of wires connected to a limited region.
　本願は、限られた領域内において、半導体チップを電極端子に接続する配線の本数を増やすことができる半導体装置を提供することを目的とする。 An object of the present application is to provide a semiconductor device capable of increasing the number of wirings for connecting a semiconductor chip to electrode terminals in a limited region.
　本願の半導体装置は、半導体チップと、前記半導体チップが搭載されるチップ搭載面を有するチップ搭載基板と、第１及び第２の配線を介して前記半導体チップに電気的に接続される電極端子と、を備え、前記半導体チップ及び前記電極端子の少なくとも一方の上では、前記第２の配線が前記第１の配線上に重ねて接続される。 A semiconductor device of the present application includes a semiconductor chip, a chip mounting substrate having a chip mounting surface on which the semiconductor chip is mounted, and electrode terminals electrically connected to the semiconductor chip via first and second wirings. The second wiring is overlapped with and connected to the first wiring on at least one of the semiconductor chip and the electrode terminal.
　上記によれば、限られた領域内において、半導体チップを電極端子に接続する配線の本数を増やすことができる半導体装置が提供され得る。 According to the above, it is possible to provide a semiconductor device capable of increasing the number of wirings that connect the semiconductor chip to the electrode terminals in a limited region.
第１実施形態に係る半導体装置を模式的に示す平面図である。1 is a plan view schematically showing a semiconductor device according to a first embodiment. 図１のＸ方向から見た半導体装置の一部を模式的に示す図である。It is a figure which shows typically a part of semiconductor device seen from the X direction of FIG. 第２実施形態に係る半導体装置の一部を模式的に示す図である。It is a figure which shows typically a part of semiconductor device which concerns on 2nd Embodiment. 第３実施形態に係る半導体装置を模式的に示す図である。It is a figure which shows typically the semiconductor device which concerns on 3rd Embodiment. 第４実施形態に係る半導体装置を模式的に示す図である。It is a figure which shows typically the semiconductor device which concerns on 4th Embodiment.
　最初に本願発明の実施形態を列記して説明する。 First, embodiments of the present invention will be listed and described.
　本願の半導体装置は、半導体チップと、前記半導体チップが搭載されるチップ搭載面を有するチップ搭載基板と、第１及び第２の配線を介して前記半導体チップに電気的に接続される電極端子と、を備え、前記半導体チップ及び前記電極端子の少なくとも一方の上では、前記第２の配線が前記第１の配線上に重ねて接続される。 A semiconductor device of the present application includes a semiconductor chip, a chip mounting substrate having a chip mounting surface on which the semiconductor chip is mounted, and electrode terminals electrically connected to the semiconductor chip via first and second wirings. The second wiring is overlapped with and connected to the first wiring on at least one of the semiconductor chip and the electrode terminal.
　この半導体装置では、半導体チップ及び電極端子の少なくとも一方の上において、第２の配線が第１の配線上に重ねて接続されるので、第２の配線を接続するための領域が不要になる。そのため、限られた領域内において、半導体チップと電極端子との間の配線の本数を増やすことができる。 In this semiconductor device, since the second wiring is connected over the first wiring on at least one of the semiconductor chip and the electrode terminal, a region for connecting the second wiring becomes unnecessary. Therefore, the number of wirings between the semiconductor chip and the electrode terminals can be increased in a limited region.
　一実施形態において、前記電極端子が、ソース電極端子、エミッタ電極端子、又はアノード電極端子であってもよい。 In one embodiment, the electrode terminal may be a source electrode terminal, an emitter electrode terminal, or an anode electrode terminal.
　この場合、半導体チップと電極端子との間に大電流が流れる。そのような場合であっても、半導体チップと電極端子との間の配線の本数を増やすことによって、配線に流れる電流を分散させることができる。 In this case, a large current flows between the semiconductor chip and the electrode terminal. Even in such a case, the current flowing through the wiring can be dispersed by increasing the number of wirings between the semiconductor chip and the electrode terminals.
　一実施形態において、前記半導体チップの材料が、ワイドバンドギャップ半導体を含んでもよい。 In one embodiment, the material of the semiconductor chip may include a wide band gap semiconductor.
　シリコン（Ｓｉ）では、半導体チップに小さい電流しか流れないので、多数の配線を使用する必要性は低い。しかし、ワイドバンドギャップ半導体では、半導体チップに流れる電流がシリコンよりも大きいので、電流の集中を抑制するために配線の本数を増やす必要性が高い。また、ワイドバンドギャップ半導体では、シリコンよりも低い製造歩留まりに起因して半導体チップの大型化が難しい。このため、ワイドバンドギャップ半導体では、小型の半導体チップに多数の配線が接続される。よって、ワイドバンドギャップ半導体では、配線の本数を増やすことが特に重要である。 Since silicon (Si) allows only a small current to flow through a semiconductor chip, it is not necessary to use a large number of wires. However, in a wide bandgap semiconductor, the current flowing through the semiconductor chip is larger than that in silicon, so that there is a high need to increase the number of wirings in order to suppress current concentration. Further, in the wide band gap semiconductor, it is difficult to increase the size of the semiconductor chip due to the manufacturing yield lower than that of silicon. For this reason, in the wide band gap semiconductor, a large number of wirings are connected to a small semiconductor chip. Therefore, it is particularly important to increase the number of wirings in the wide band gap semiconductor.
　一実施形態において、前記第１の配線及び前記第２の配線の少なくとも一方がボンディングリボンであってもよい。 In one embodiment, at least one of the first wiring and the second wiring may be a bonding ribbon.
　これにより、第１の配線と第２の配線との間の接続安定性を向上させることができる。 Thereby, the connection stability between the first wiring and the second wiring can be improved.
　一実施形態において、前記第１の配線がボンディングリボンであってもよい。 In one embodiment, the first wiring may be a bonding ribbon.
　これにより、半導体チップ及び電極端子の少なくとも一方、第１の配線、及び第２の配線の間の接続安定性を向上させることができる。 Thereby, the connection stability between at least one of the semiconductor chip and the electrode terminal, the first wiring, and the second wiring can be improved.
　一実施形態において、前記第１の配線及び前記第２の配線の材料が、アルミニウム又は銅を含んでもよい。 In one embodiment, the material of the first wiring and the second wiring may include aluminum or copper.
　以下、添付図面を参照しながら本発明の実施形態が詳細に説明される。図面の説明において、同一又は同等の要素には同一符号が用いられ、重複する説明は省略される。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are used for the same or equivalent elements, and redundant descriptions are omitted.
（第１実施形態）
　図１は、第１実施形態に係る半導体装置を模式的に示す平面図である。図１には、ＸＹＺ直交座標系が示されている。図２は、図１のＸ方向から見た半導体装置の一部を模式的に示す図である。図１及び図２に示される半導体装置１０は、樹脂封止型の半導体装置である。半導体装置１０は、チップ搭載基板としてのダイパッド１２と、半導体チップ（又は半導体素子）１４と、電極端子としてのリード２０とを備える。 (First embodiment)
FIG. 1 is a plan view schematically showing the semiconductor device according to the first embodiment. FIG. 1 shows an XYZ orthogonal coordinate system. FIG. 2 is a diagram schematically showing a part of the semiconductor device viewed from the X direction of FIG. A semiconductor device 10 shown in FIGS. 1 and 2 is a resin-encapsulated semiconductor device. The semiconductor device 10 includes a die pad 12 as a chip mounting substrate, a semiconductor chip (or semiconductor element) 14, and leads 20 as electrode terminals.
　半導体装置１０は、別の電極端子としてのリード１６及び１８を備えてもよい。リード１６，１８，２０はＸ方向に沿って配列される。リード１６は、リード１８，２０の間に位置する。リード１６，１８、２０及びダイパッド１２は、リードフレームを構成し得る。半導体装置１０は、例えば電源等に使用される電力用半導体装置である。半導体装置１０のパッケージ形態の例は一般的なＴＯシリーズである。ＴＯシリーズの例はＴＯ－２４７、ＴＯ－２２０、ＴＯ－２６３（Ｄ２―ＰＡＫ）、ＴＯ－２５２（Ｄ－ＰＡＫ）を含む。 The semiconductor device 10 may include leads 16 and 18 as other electrode terminals. The leads 16, 18, and 20 are arranged along the X direction. The lead 16 is located between the leads 18 and 20. The leads 16, 18, 20 and the die pad 12 may constitute a lead frame. The semiconductor device 10 is a power semiconductor device used for a power source or the like, for example. An example of the package form of the semiconductor device 10 is a general TO series. Examples of TO series include TO-247, TO-220, TO-263 (D2-PAK), and TO-252 (D-PAK).
　ダイパッド１２は、半導体チップ１４が搭載されるチップ搭載面１２ａを有する。ダイパッド１２は、半導体チップ１４と電気的に接続され得る。ダイパッド１２は例えば板状を呈している。チップ搭載面１２ａは、例えば長方形である。ダイパッド１２の材料の例は、銅（Ｃｕ）及び銅合金等の金属を含む。ダイパッド１２には、板厚方向にダイパッド１２を貫通する貫通孔２６が形成され得る。貫通孔２６は、例えば螺子によって半導体装置１０を他の部材に固定する際に、螺子を通すための孔である。 The die pad 12 has a chip mounting surface 12a on which the semiconductor chip 14 is mounted. The die pad 12 can be electrically connected to the semiconductor chip 14. The die pad 12 has a plate shape, for example. The chip mounting surface 12a is, for example, a rectangle. Examples of the material of the die pad 12 include metals such as copper (Cu) and a copper alloy. A through-hole 26 that penetrates the die pad 12 in the thickness direction can be formed in the die pad 12. The through hole 26 is a hole through which a screw is passed when the semiconductor device 10 is fixed to another member by, for example, a screw.
　半導体チップ１４は、チップ搭載面１２ａの所定位置に搭載される。半導体チップ１４の例は、バイポーラトランジスタ、ＭＯＳ－ＦＥＴ、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）等のトランジスタ、ダイオードを含む。半導体チップ１４は、鉛入り金属半田、鉛を含まない金属半田又は導電性樹脂等を含む材料から構成される接着層３２を介してチップ搭載面１２ａに実装され得る。半導体チップ１４の材料の例は、ワイドバンドギャップ半導体、シリコンその他の半導体を含む。ワイドバンドギャップ半導体は、シリコンのバンドギャップよりも大きいバンドギャップを有する。ワイドバンドギャップ半導体の例は、シリコンカーバイド（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンドを含む。 The semiconductor chip 14 is mounted at a predetermined position on the chip mounting surface 12a. Examples of the semiconductor chip 14 include transistors such as bipolar transistors, MOS-FETs, insulated gate bipolar transistors (IGBTs), and diodes. The semiconductor chip 14 can be mounted on the chip mounting surface 12a via an adhesive layer 32 made of a material containing lead-containing metal solder, lead-free metal solder, conductive resin, or the like. Examples of the material of the semiconductor chip 14 include a wide band gap semiconductor, silicon and other semiconductors. A wide band gap semiconductor has a band gap larger than that of silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and diamond.
　リード１６の内側端部は、ダイパッド１２に機械的に一体的に連結されている。ダイパッド１２は導電性を有するので、リード１６とダイパッド１２とは電気的に接続されている。リード１６の材料の例はダイパッド１２の材料と同じ材料を含む。 The inner end of the lead 16 is mechanically and integrally connected to the die pad 12. Since the die pad 12 has conductivity, the lead 16 and the die pad 12 are electrically connected. Examples of the material of the lead 16 include the same material as that of the die pad 12.
　リード１８は、配線３０を介して半導体チップ１４に接続される。配線３０の一端は半導体チップ１４の電極パッドＧＰに接続される。配線３０の他端はリード１８の内側端部に接続される。 The lead 18 is connected to the semiconductor chip 14 via the wiring 30. One end of the wiring 30 is connected to the electrode pad GP of the semiconductor chip 14. The other end of the wiring 30 is connected to the inner end of the lead 18.
　リード２０は、第１～第４の配線２２ａ～２２ｄを介して半導体チップ１４に電気的に接続される。配線２２ａ～２２ｄは、半導体チップ１４の電極パッドＳＰに電気的に接続される第１の端部Ｅ１ａ～Ｅ１ｄと、リード２０の内側端部に電気的に接続される第２の端部Ｅ２ａ～Ｅ２ｄとをそれぞれ有してもよい。リード２０上では、第２の配線２２ｂが第１の配線２２ａ上に重ねて接続され、第４の配線２２ｄが第３の配線２２ｃ上に重ねて接続される。 The lead 20 is electrically connected to the semiconductor chip 14 via the first to fourth wirings 22a to 22d. The wirings 22a to 22d include first end portions E1a to E1d that are electrically connected to the electrode pads SP of the semiconductor chip 14, and second end portions E2a to E2a that are electrically connected to the inner end portions of the leads 20. And E2d. On the lead 20, the second wiring 22b is overlaid on the first wiring 22a and connected, and the fourth wiring 22d is overlaid on the third wiring 22c.
　配線２２ａ～２２ｄの端部Ｅ１ａ～Ｅ１ｄは、電極パッドＳＰの表面において分散配置される。配線２２ａの端部Ｅ１ａは、配線２２ｂの端部Ｅ１ｂよりもリード２０に近い位置に配置され得る。配線２２ｃの端部Ｅ１ｃは、配線２２ｄの端部Ｅ１ｄよりもリード２０に近い位置に配置され得る。端部Ｅ１ａ及びＥ１ｃは、Ｘ方向においてこの順に配列される。端部Ｅ１ｂ及びＥ１ｄは、Ｘ方向においてこの順に配列される。 The ends E1a to E1d of the wirings 22a to 22d are distributed on the surface of the electrode pad SP. The end E1a of the wiring 22a can be disposed at a position closer to the lead 20 than the end E1b of the wiring 22b. The end E1c of the wiring 22c can be disposed at a position closer to the lead 20 than the end E1d of the wiring 22d. The ends E1a and E1c are arranged in this order in the X direction. The ends E1b and E1d are arranged in this order in the X direction.
　配線２２ａの端部Ｅ２ａは、配線２２ｂの端部Ｅ２ｂとリード２０との間に配置される。配線２２ｃの端部Ｅ２ｃは、配線２２ｄの端部Ｅ２ｄとリード２０との間に配置される。配線２２ａの端部Ｅ２ａは、配線２２ｃの端部Ｅ２ｃよりも半導体チップ１４に近い位置に配置され得る。端部Ｅ２ａ及びＥ２ｃは、Ｘ方向においてこの順に配列される。 The end E2a of the wiring 22a is disposed between the end E2b of the wiring 22b and the lead 20. The end E2c of the wiring 22c is disposed between the end E2d of the wiring 22d and the lead 20. The end E2a of the wiring 22a can be disposed at a position closer to the semiconductor chip 14 than the end E2c of the wiring 22c. The ends E2a and E2c are arranged in this order in the X direction.
　半導体チップ１４がＭＯＳ－ＦＥＴを含む場合、リード１６はドレイン電極端子に対応し、リード１８はゲート電極端子に対応し、リード２０はソース電極端子に対応し、電極パッドＧＰはゲート電極パッドに対応し、電極パッドＳＰはソース電極パッドに対応する。半導体チップ１４がＩＧＢＴを含む場合、リード１６はコレクタ電極端子に対応し、リード１８はゲート電極端子に対応し、リード２０はエミッタ電極端子に対応し、電極パッドＧＰはゲート電極パッドに対応し、電極パッドＳＰはエミッタ電極パッドに対応する。半導体チップ１４がダイオードを含む場合、リード１６はカソード電極端子に対応し、リード２０はアノード電極端子に対応し、電極パッドＳＰはアノード電極パッドに対応する。この場合、半導体装置１０はリード１８及び電極パッドＧＰを備えていない。 When the semiconductor chip 14 includes a MOS-FET, the lead 16 corresponds to the drain electrode terminal, the lead 18 corresponds to the gate electrode terminal, the lead 20 corresponds to the source electrode terminal, and the electrode pad GP corresponds to the gate electrode pad. The electrode pad SP corresponds to the source electrode pad. When the semiconductor chip 14 includes an IGBT, the lead 16 corresponds to the collector electrode terminal, the lead 18 corresponds to the gate electrode terminal, the lead 20 corresponds to the emitter electrode terminal, the electrode pad GP corresponds to the gate electrode pad, The electrode pad SP corresponds to the emitter electrode pad. When the semiconductor chip 14 includes a diode, the lead 16 corresponds to the cathode electrode terminal, the lead 20 corresponds to the anode electrode terminal, and the electrode pad SP corresponds to the anode electrode pad. In this case, the semiconductor device 10 does not include the lead 18 and the electrode pad GP.
　リード１８，２０の材料の例は、銅及び銅合金等の金属を含む。配線２２ａ～２２ｄ，３０は、ワイヤ又はボンディングリボンであってもよい。配線２２ａ～２２ｄ，３０の断面形状は例えば円形である。配線２２ａ～２２ｄ，３０の径は、例えば１００～５００μｍである。配線２２ａの径は、配線２２ｂの径より大きくてもよい。これにより、配線２２ｂを配線２２ａ上にワイヤボンディングし易くなる。配線２２ａとリード２０との接触面積は、例えば５００００～２５０００００μｍ２である。配線２２ａ～２２ｄ，３０の材料の例は、アルミニウム、金、銅等の金属を含む。配線２２ａ～２２ｄ，３０は、例えば超音波又は加圧等を用いたワイヤボンディングによりリード１８，２０及び半導体チップ１４に電気的に接続される。 Examples of the material of the leads 18 and 20 include metals such as copper and copper alloys. The wirings 22a to 22d and 30 may be wires or bonding ribbons. The cross-sectional shapes of the wirings 22a to 22d and 30 are, for example, circular. The diameters of the wirings 22a to 22d and 30 are, for example, 100 to 500 μm. The diameter of the wiring 22a may be larger than the diameter of the wiring 22b. This facilitates wire bonding of the wiring 22b on the wiring 22a. The contact area between the wiring 22a and the lead 20 is, for example, 50,000 to 2500,000 μm 2 . Examples of the material of the wirings 22a to 22d and 30 include metals such as aluminum, gold, and copper. The wirings 22a to 22d and 30 are electrically connected to the leads 18 and 20 and the semiconductor chip 14 by wire bonding using, for example, ultrasonic waves or pressure.
　ダイパッド１２及び半導体チップ１４は、樹脂部２４によって封止され得る。リード１６，１８，２０の内側端部は、樹脂部２４に固定される。リード１６，１８，２０のうち樹脂部２４の内側の部分は、いわゆるインナーリード部である。リード１６，１８，２０のうち樹脂部２４の外側の部分は、アウターリード部である。樹脂部２４の外形形状の一例は、略直方体である。樹脂部２４の材料の例は、ポリフェニレンサルファイド樹脂（ＰＰＳ樹脂）、液晶ポリマー等の熱可塑性樹脂を含む。樹脂部２４は、ダイパッド１２及び半導体チップ１４を熱可塑性樹脂でモールドすることによって形成され得る。樹脂部２４には、ダイパッド１２の貫通孔２６の中心軸線を中心軸線とする貫通孔２８が形成されている。貫通孔２８は、貫通孔２６と同様に螺子止めなどの際などに螺子が通される孔である。貫通孔２８の直径は、貫通孔２６の直径より小さい。 The die pad 12 and the semiconductor chip 14 can be sealed by the resin portion 24. Inner ends of the leads 16, 18, and 20 are fixed to the resin portion 24. Of the leads 16, 18, and 20, the portion inside the resin portion 24 is a so-called inner lead portion. Of the leads 16, 18, and 20, the portion outside the resin portion 24 is an outer lead portion. An example of the outer shape of the resin portion 24 is a substantially rectangular parallelepiped. Examples of the material of the resin portion 24 include thermoplastic resins such as polyphenylene sulfide resin (PPS resin) and liquid crystal polymer. The resin portion 24 can be formed by molding the die pad 12 and the semiconductor chip 14 with a thermoplastic resin. A through hole 28 is formed in the resin portion 24 with the central axis of the through hole 26 of the die pad 12 as the central axis. The through hole 28 is a hole through which a screw is passed in the case of screwing or the like, like the through hole 26. The diameter of the through hole 28 is smaller than the diameter of the through hole 26.
　一実施形態において、ダイパッド１２のチップ搭載面１２ａと反対側の面である底面１２ｆは開放され得る。換言すれば、底面１２ｆは樹脂部２４によって覆われていない面であり得る。この場合、底面１２ｆは放熱面として機能し得る。 In one embodiment, the bottom surface 12f of the die pad 12 opposite to the chip mounting surface 12a can be opened. In other words, the bottom surface 12 f may be a surface that is not covered by the resin portion 24. In this case, the bottom surface 12f can function as a heat dissipation surface.
　半導体装置１０では、リード２０上において、第２の配線２２ｂが第１の配線２２ａ上に重ねて接続されるので、第２の配線２２ｂを接続するための領域が不要になる。第４の配線２２ｄが第３の配線２２ｃ上に重ねて接続されるので、第４の配線２２ｄを接続するための領域が不要になる。そのため、リード２０の限られた領域内において、半導体チップ１４とリード２０との間の配線２２ａ～２２ｄの本数を増やすことができる。その結果、リード２０から半導体チップ１４に大電流を流すことができる。さらに、リード２０を小型化できる。 In the semiconductor device 10, since the second wiring 22b is overlapped and connected to the first wiring 22a on the lead 20, an area for connecting the second wiring 22b is not necessary. Since the fourth wiring 22d is overlapped and connected to the third wiring 22c, an area for connecting the fourth wiring 22d is not necessary. Therefore, the number of wirings 22a to 22d between the semiconductor chip 14 and the lead 20 can be increased in a limited region of the lead 20. As a result, a large current can flow from the lead 20 to the semiconductor chip 14. Furthermore, the lead 20 can be reduced in size.
　リード２０が、ソース電極端子、エミッタ電極端子、又はアノード電極端子である場合、半導体チップ１４とリード２０との間に大電流が流れる。そのような場合であっても、半導体チップ１４とリード２０との間の配線２２ａ～２２ｄの本数を増やすことによって、配線２２ａ～２２ｄに流れる電流を分散させることができる。 When the lead 20 is a source electrode terminal, an emitter electrode terminal, or an anode electrode terminal, a large current flows between the semiconductor chip 14 and the lead 20. Even in such a case, the current flowing through the wirings 22a to 22d can be dispersed by increasing the number of wirings 22a to 22d between the semiconductor chip 14 and the leads 20.
　シリコンでは、半導体チップ１４に小さい電流しか流れないので、多数の配線２２ａ～２２ｄを使用する必要性は低い。しかし、ワイドバンドギャップ半導体では、半導体チップ１４に流れる電流がシリコンよりも大きいので、電流の集中を抑制するために配線２２ａ～２２ｄの本数を増やす必要性が高い。また、ワイドバンドギャップ半導体では、シリコンよりも低い製造歩留まりに起因して半導体チップ１４の大型化が難しい。このため、ワイドバンドギャップ半導体では、小型の半導体チップ１４に多数の配線２２ａ～２２ｄが接続される。よって、ワイドバンドギャップ半導体では、配線２２ａ～２２ｄの本数を増やすことが特に重要である。 In silicon, only a small current flows through the semiconductor chip 14, so that it is not necessary to use a large number of wirings 22a to 22d. However, in the wide band gap semiconductor, the current flowing through the semiconductor chip 14 is larger than that in silicon, so that it is highly necessary to increase the number of wirings 22a to 22d in order to suppress current concentration. Further, in the wide band gap semiconductor, it is difficult to increase the size of the semiconductor chip 14 due to the manufacturing yield lower than that of silicon. Therefore, in the wide band gap semiconductor, a large number of wirings 22a to 22d are connected to the small semiconductor chip 14. Therefore, in a wide band gap semiconductor, it is particularly important to increase the number of wirings 22a to 22d.
（第２実施形態）
　図３は、第２実施形態に係る半導体装置の一部を模式的に示す図である。図３は、図２に対応する。第２実施形態に係る半導体装置は、配線２２ａ～２２ｄの配置が異なること以外は半導体装置１０と同様の構成を備える。第２実施形態に係る半導体装置では、半導体チップ１４上において、第２の配線２２ｂが第１の配線２２ａ上に重ねて接続され、第４の配線２２ｄが第３の配線２２ｃ上に重ねて接続される。配線２２ａの端部Ｅ１ａは、配線２２ｂの端部Ｅ１ｂと半導体チップ１４との間に配置される。配線２２ｃの端部Ｅ１ｃは、配線２２ｄの端部Ｅ１ｄと半導体チップ１４との間に配置される。配線２２ａ～２２ｄの端部Ｅ２ａ～Ｅ２ｄは、Ｘ方向においてこの順に配列される。 (Second Embodiment)
FIG. 3 is a diagram schematically showing a part of the semiconductor device according to the second embodiment. FIG. 3 corresponds to FIG. The semiconductor device according to the second embodiment has the same configuration as that of the semiconductor device 10 except that the arrangement of the wirings 22a to 22d is different. In the semiconductor device according to the second embodiment, on the semiconductor chip 14, the second wiring 22b is overlaid on the first wiring 22a and the fourth wiring 22d is overlaid on the third wiring 22c. Is done. The end E1a of the wiring 22a is disposed between the end E1b of the wiring 22b and the semiconductor chip 14. The end E1c of the wiring 22c is disposed between the end E1d of the wiring 22d and the semiconductor chip 14. The ends E2a to E2d of the wirings 22a to 22d are arranged in this order in the X direction.
　第２実施形態に係る半導体装置では、半導体チップ１４上において、第２の配線２２ｂが第１の配線２２ａ上に重ねて接続されるので、第２の配線２２ｂを接続するための領域が不要になる。第４の配線２２ｄが第３の配線２２ｃ上に重ねて接続されるので、第４の配線２２ｄを接続するための領域が不要になる。そのため、半導体チップ１４の限られた領域内において、半導体チップ１４とリード２０との間の配線２２ａ～２２ｄの本数を増やすことができる。その結果、リード２０から半導体チップ１４に大電流を流すことができる。さらに、半導体チップ１４を小型化できる。 In the semiconductor device according to the second embodiment, since the second wiring 22b is connected to the first wiring 22a in an overlapping manner on the semiconductor chip 14, an area for connecting the second wiring 22b is unnecessary. Become. Since the fourth wiring 22d is overlapped and connected to the third wiring 22c, an area for connecting the fourth wiring 22d is not necessary. Therefore, the number of wirings 22a to 22d between the semiconductor chip 14 and the leads 20 can be increased in a limited region of the semiconductor chip 14. As a result, a large current can flow from the lead 20 to the semiconductor chip 14. Furthermore, the semiconductor chip 14 can be reduced in size.
（第３実施形態）
　図４は、第３実施形態に係る半導体装置を模式的に示す図である。図４は、図１に対応する。第３実施形態に係る半導体装置は、第１の配線２２ａ及び第３の配線２２ｃに代えてボンディングリボン２２ｅを備えること以外は半導体装置１０と同様の構成を備える。ボンディングリボン２２ｅは、半導体チップ１４の電極パッドＳＰに電気的に接続される第１の端部Ｅ１ｅと、リード２０の内側端部に電気的に接続される第２の端部Ｅ２ｅとを有してもよい。リード２０上では、第２の配線２２ｂ及び第４の配線２２ｄは、ボンディングリボン２２ｅ上に重ねて接続される。ボンディングリボン２２ｅの端部Ｅ２ｅは、配線２２ｂの端部Ｅ２ｂ及び配線２２ｄの端部Ｅ２ｄとリード２０との間に配置される。 (Third embodiment)
FIG. 4 is a diagram schematically showing a semiconductor device according to the third embodiment. FIG. 4 corresponds to FIG. The semiconductor device according to the third embodiment has the same configuration as that of the semiconductor device 10 except that a bonding ribbon 22e is provided instead of the first wiring 22a and the third wiring 22c. The bonding ribbon 22e has a first end E1e electrically connected to the electrode pad SP of the semiconductor chip 14 and a second end E2e electrically connected to the inner end of the lead 20. May be. On the lead 20, the second wiring 22b and the fourth wiring 22d are overlapped and connected to the bonding ribbon 22e. The end E2e of the bonding ribbon 22e is disposed between the end 20E2b of the wiring 22b and the end E2d of the wiring 22d and the lead 20.
　第３実施形態に係る半導体装置では、少なくとも半導体装置１０と同様の作用効果が得られる。さらに、リード２０とボンディングリボン２２ｅと配線２２ｂ及び２２ｄとの間の接続安定性を向上させることができる。配線２２ｂ及び２２ｄをボンディングリボン２２ｅ上にワイヤボンディングし易い。 The semiconductor device according to the third embodiment can obtain at least the same effects as the semiconductor device 10. Furthermore, connection stability among the lead 20, the bonding ribbon 22e, and the wirings 22b and 22d can be improved. It is easy to wire-bond the wirings 22b and 22d on the bonding ribbon 22e.
（第４実施形態）
　図５は、第４実施形態に係る半導体装置を模式的に示す図である。図５に示される半導体装置１１０は、ケース型の半導体装置である。半導体装置１１０は、チップ搭載基板としての配線基板４０と、半導体チップ１４と、電極端子４２０と、ケース５２とを備える。 (Fourth embodiment)
FIG. 5 is a diagram schematically showing a semiconductor device according to the fourth embodiment. A semiconductor device 110 shown in FIG. 5 is a case-type semiconductor device. The semiconductor device 110 includes a wiring substrate 40 as a chip mounting substrate, a semiconductor chip 14, electrode terminals 420, and a case 52.
　配線基板４０は、半導体チップ１４が搭載されるチップ搭載面４６ａを有する。半導体チップ１４は、接着層３２を介してチップ搭載面４６ａに搭載される。電極端子４２０は、第１及び第２の配線２２ａ，２２ｂを介して半導体チップ１４に接続される。電極端子４２０上では、図１及び図２に示される半導体装置１０のリード２０と同様に、第２の配線２２ｂが第１の配線２２ａ上に重ねて接続される。 The wiring board 40 has a chip mounting surface 46a on which the semiconductor chip 14 is mounted. The semiconductor chip 14 is mounted on the chip mounting surface 46 a via the adhesive layer 32. The electrode terminal 420 is connected to the semiconductor chip 14 via the first and second wirings 22a and 22b. On the electrode terminal 420, like the lead 20 of the semiconductor device 10 shown in FIGS. 1 and 2, the second wiring 22b is overlapped with and connected to the first wiring 22a.
　配線基板４０は、絶縁性基板４２と、絶縁性基板４２の表面に設けられた配線層４６と、絶縁性基板４２の裏面に設けられた放熱層４４とを備える。配線層４６の材料の例は、銅及び銅合金等の金属を含む。絶縁性基板４２の材料の例は、アルミナ等のセラミックを含む。放熱層４４の材料の例は、銅及び銅合金等の金属を含む。放熱層４４は、例えば半田等を含む接着層４８を介してヒートシンク５０に接着される。ヒートシンク５０の材料の例は、金属を含む。 The wiring substrate 40 includes an insulating substrate 42, a wiring layer 46 provided on the surface of the insulating substrate 42, and a heat dissipation layer 44 provided on the back surface of the insulating substrate 42. Examples of the material of the wiring layer 46 include metals such as copper and copper alloys. An example of the material of the insulating substrate 42 includes ceramic such as alumina. Examples of the material of the heat dissipation layer 44 include metals such as copper and copper alloys. The heat dissipation layer 44 is bonded to the heat sink 50 via an adhesive layer 48 including, for example, solder. An example of the material of the heat sink 50 includes a metal.
　半導体チップ１４及び配線基板４０は、ケース５２に収容される。ケース５２は、例えば筒状である。ケース５２の一方の開口はヒートシンク５０によって封止され得る。ケース５２の他方の開口は蓋５４によって封止され得る。ケース５２の材料の例は、ポリブチレンテレフタレート（ＰＢＴ）又はポリフェニレンサルファイド（ＰＰＳ）樹脂といったエンジニヤリングプラスチック等の樹脂を含む。蓋５４の材料の例は熱可塑性樹脂を含む。ケース５２の内側には、応力緩和のため、例えばシリコーンゲル等のゲル５６が注入され得る。 The semiconductor chip 14 and the wiring board 40 are accommodated in the case 52. The case 52 has a cylindrical shape, for example. One opening of the case 52 can be sealed by the heat sink 50. The other opening of the case 52 can be sealed by a lid 54. Examples of the material of the case 52 include resins such as engineering plastics such as polybutylene terephthalate (PBT) or polyphenylene sulfide (PPS) resin. An example of the material of the lid 54 includes a thermoplastic resin. Inside the case 52, a gel 56 such as a silicone gel may be injected for stress relaxation.
　半導体装置１１０は、電極端子４１８を備え得る。電極端子４１８は、配線３０を介して半導体チップ１４に接続される。電極端子４１８及び電極端子４２０はケース５２の内壁に取り付けられる。電極端子４１８及び電極端子４２０は、ケース５２の内壁に沿って延びており、蓋５４に形成された開口を通って外部に突出する。電極端子４１８及び電極端子４２０は、プレス加工等により作製され得る。 The semiconductor device 110 may include an electrode terminal 418. The electrode terminal 418 is connected to the semiconductor chip 14 via the wiring 30. The electrode terminal 418 and the electrode terminal 420 are attached to the inner wall of the case 52. The electrode terminal 418 and the electrode terminal 420 extend along the inner wall of the case 52 and project outside through an opening formed in the lid 54. The electrode terminal 418 and the electrode terminal 420 can be manufactured by press working or the like.
　半導体チップ１４がＭＯＳ－ＦＥＴを含む場合、電極端子４１８はゲート電極端子に対応し、電極端子４２０はソース電極端子に対応する。ドレイン電極端子は図示されていない。半導体チップ１４がＩＧＢＴを含む場合、電極端子４１８はゲート電極端子に対応し、電極端子４２０はエミッタ電極端子に対応する。コレクタ電極端子は図示されていない。半導体チップ１４がダイオードを含む場合、電極端子４２０はアノード電極端子に対応する。カソード電極端子は図示されていない。この場合、半導体装置１１０は電極端子４１８を備えていない。 When the semiconductor chip 14 includes a MOS-FET, the electrode terminal 418 corresponds to the gate electrode terminal, and the electrode terminal 420 corresponds to the source electrode terminal. The drain electrode terminal is not shown. When the semiconductor chip 14 includes an IGBT, the electrode terminal 418 corresponds to a gate electrode terminal, and the electrode terminal 420 corresponds to an emitter electrode terminal. The collector electrode terminal is not shown. When the semiconductor chip 14 includes a diode, the electrode terminal 420 corresponds to the anode electrode terminal. The cathode electrode terminal is not shown. In this case, the semiconductor device 110 does not include the electrode terminal 418.
　第４実施形態に係る半導体装置では、少なくとも半導体装置１０と同様の作用効果が得られる。 In the semiconductor device according to the fourth embodiment, at least the same effects as the semiconductor device 10 can be obtained.
　以上、本発明の好適な実施形態について詳細に説明されたが、本発明は上記実施形態に限定されない。各実施形態の構成要素は任意に組み合わされ得る。 The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the above embodiments. The components of each embodiment can be arbitrarily combined.
　例えば、図１及び図２の半導体装置１０は、配線２２ｃ及び２２ｄを備えなくてもよいし、半導体チップ１４とリード２０との間に設けられた更なる配線を備えてもよい。リード２０上において、第２の配線２２ｂ及び第４の配線２２ｄ上に更なる配線が重ねて接続されてもよい。 For example, the semiconductor device 10 of FIGS. 1 and 2 may not include the wirings 22c and 22d, or may include a further wiring provided between the semiconductor chip 14 and the lead 20. On the lead 20, a further wiring may be overlapped and connected on the second wiring 22b and the fourth wiring 22d.
　電極パッドＧＰとリード１８との間に複数の配線３０が設けられてもよい。この場合、半導体チップ１４上において、配線３０上に更なる配線３０が重ねて接続されてもよいし、リード１８上において、配線３０上に更なる配線３０が重ねて接続されてもよい。 A plurality of wirings 30 may be provided between the electrode pad GP and the lead 18. In this case, on the semiconductor chip 14, a further wiring 30 may be overlaid on the wiring 30, or on the lead 18, the further wiring 30 may be overlaid on the wiring 30.
　図３に示される第２実施形態に係る半導体装置では、第１実施形態と同様に、リード２０上においても、第２の配線２２ｂが第１の配線２２ａ上に重ねて接続され、第４の配線２２ｄが第３の配線２２ｃ上に重ねて接続されてもよい。 In the semiconductor device according to the second embodiment shown in FIG. 3, as in the first embodiment, the second wiring 22 b is also connected to the first wiring 22 a so as to overlap the lead 20 on the lead 20. The wiring 22d may be overlapped with and connected to the third wiring 22c.
　図４に示される第３実施形態に係る半導体装置では、第２の配線２２ｂ及び第４の配線２２ｄがボンディングリボンに置き換えられてもよい。この場合、ボンディングリボン２２ｅが第１の配線２２ａ及び第３の配線２２ｃに置き換えられてもよい。その結果、リード２０上において、ボンディングリボンが第１の配線２２ａ及び第３の配線２２ｃ上に重ねて接続される。このような場合でも、ボンディングリボンと第１の配線２２ａ及び第３の配線２２ｃとの間の接続安定性を向上させることができる。第２実施形態と同様に、半導体チップ１４上において、配線２２ｂ及び２２ｄがボンディングリボン２２ｅ上に重ねて接続されてもよい。 In the semiconductor device according to the third embodiment shown in FIG. 4, the second wiring 22b and the fourth wiring 22d may be replaced with a bonding ribbon. In this case, the bonding ribbon 22e may be replaced with the first wiring 22a and the third wiring 22c. As a result, on the lead 20, the bonding ribbon is overlapped and connected on the first wiring 22a and the third wiring 22c. Even in such a case, the connection stability between the bonding ribbon and the first wiring 22a and the third wiring 22c can be improved. Similarly to the second embodiment, on the semiconductor chip 14, the wirings 22b and 22d may be overlapped on and connected to the bonding ribbon 22e.
　図５に示される第４実施形態に係る半導体装置では、第２実施形態と同様に、半導体チップ１４上において、配線２２ｂが配線２２ａ上に重ねて接続されてもよい。第３実施形態と同様に、配線２２ａ及び２２ｂの少なくとも一方がボンディングリボンに置き換えられてもよい。 In the semiconductor device according to the fourth embodiment shown in FIG. 5, the wiring 22b may be overlapped and connected on the wiring 22a on the semiconductor chip 14 as in the second embodiment. Similar to the third embodiment, at least one of the wirings 22a and 22b may be replaced with a bonding ribbon.
　１０，１１０…半導体装置、１２…ダイパッド（チップ搭載基板）、１２ａ，４６ａ…チップ搭載面、１４…半導体チップ、２０…リード（電極端子）、２２ａ…第１の配線、２２ｂ…第２の配線、２２ｅ…ボンディングリボン、４０…配線基板（チップ搭載基板）、４２０…電極端子。 DESCRIPTION OF SYMBOLS 10,110 ... Semiconductor device, 12 ... Die pad (chip mounting substrate), 12a, 46a ... Chip mounting surface, 14 ... Semiconductor chip, 20 ... Lead (electrode terminal), 22a ... First wiring, 22b ... Second wiring , 22e ... bonding ribbon, 40 ... wiring board (chip mounting board), 420 ... electrode terminal.

Claims (6)

  1. 　半導体チップと、
    　前記半導体チップが搭載されるチップ搭載面を有するチップ搭載基板と、
    　第１及び第２の配線を介して前記半導体チップに電気的に接続される電極端子と、
    を備え、
    　前記半導体チップ及び前記電極端子の少なくとも一方の上では、前記第２の配線が前記第１の配線上に重ねて接続される、半導体装置。     A semiconductor chip;
    A chip mounting substrate having a chip mounting surface on which the semiconductor chip is mounted;
    Electrode terminals electrically connected to the semiconductor chip via first and second wirings;
    With
    The semiconductor device, wherein the second wiring is overlapped with and connected to the first wiring on at least one of the semiconductor chip and the electrode terminal.
  2. 　前記電極端子が、ソース電極端子、エミッタ電極端子、又はアノード電極端子である、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the electrode terminal is a source electrode terminal, an emitter electrode terminal, or an anode electrode terminal.
  3. 　前記半導体チップの材料が、ワイドバンドギャップ半導体を含む、請求項１又は２に記載の半導体装置。 The semiconductor device according to claim 1 or 2, wherein a material of the semiconductor chip includes a wide band gap semiconductor.
  4. 　前記第１の配線及び前記第２の配線の少なくとも一方がボンディングリボンである、請求項１～３のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3, wherein at least one of the first wiring and the second wiring is a bonding ribbon.
  5. 　前記第１の配線がボンディングリボンである、請求項４に記載の半導体装置。 The semiconductor device according to claim 4, wherein the first wiring is a bonding ribbon.
  6. 　前記第１の配線及び前記第２の配線の材料が、アルミニウム又は銅を含む、請求項１～５のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 5, wherein a material of the first wiring and the second wiring includes aluminum or copper.
PCT/JP2014/053649 2013-03-01 2014-02-17 Semiconductor device WO2014132826A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-040914 2013-03-01
JP2013040914A JP2014170801A (en) 2013-03-01 2013-03-01 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2014132826A1 true WO2014132826A1 (en) 2014-09-04

Family

ID=51428098

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/053649 WO2014132826A1 (en) 2013-03-01 2014-02-17 Semiconductor device

Country Status (2)

Country Link
JP (1) JP2014170801A (en)
WO (1) WO2014132826A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110400668A (en) * 2018-04-24 2019-11-01 莫列斯有限公司 Electronic component

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2018235330A1 (en) 2017-06-20 2020-04-16 住友電気工業株式会社 Semiconductor device
JP7380071B2 (en) 2019-10-21 2023-11-15 富士電機株式会社 semiconductor equipment
FR3105575B1 (en) * 2019-12-20 2021-12-03 Valeo Systemes De Controle Moteur Electrical connection

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008277751A (en) * 2007-04-04 2008-11-13 Panasonic Corp Method of manufacturing semiconductor device, and semiconductor device
JP2010283053A (en) * 2009-06-03 2010-12-16 Renesas Electronics Corp Semiconductor device and method for manufacturing the same
WO2011087485A2 (en) * 2009-12-22 2011-07-21 Tessera Research Llc Microelectronic assembly with joined bond elements having lowered inductance
JP2013175609A (en) * 2012-02-27 2013-09-05 Mitsubishi Electric Corp Semiconductor device and method for manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008277751A (en) * 2007-04-04 2008-11-13 Panasonic Corp Method of manufacturing semiconductor device, and semiconductor device
JP2010283053A (en) * 2009-06-03 2010-12-16 Renesas Electronics Corp Semiconductor device and method for manufacturing the same
WO2011087485A2 (en) * 2009-12-22 2011-07-21 Tessera Research Llc Microelectronic assembly with joined bond elements having lowered inductance
JP2013175609A (en) * 2012-02-27 2013-09-05 Mitsubishi Electric Corp Semiconductor device and method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110400668A (en) * 2018-04-24 2019-11-01 莫列斯有限公司 Electronic component
US11037895B2 (en) 2018-04-24 2021-06-15 Molex, Llc Electronic component
CN110400668B (en) * 2018-04-24 2022-02-08 莫列斯有限公司 Electronic component

Also Published As

Publication number Publication date
JP2014170801A (en) 2014-09-18

Similar Documents

Publication Publication Date Title
JP5272191B2 (en) Semiconductor device and manufacturing method of semiconductor device
JPH09260550A (en) Semiconductor device
JP2019040971A (en) Semiconductor device
JP2015076562A (en) Power module
WO2013140928A1 (en) Semiconductor device
JP5387715B2 (en) Semiconductor device
WO2014132826A1 (en) Semiconductor device
US20130112993A1 (en) Semiconductor device and wiring substrate
JP7286582B2 (en) semiconductor equipment
JP2021068783A (en) Semiconductor device
JP2013219268A (en) Semiconductor device
WO2013150890A1 (en) Semiconductor device
WO2013172139A1 (en) Semiconductor device
JP5172290B2 (en) Semiconductor device
US10699994B2 (en) Semiconductor device having bonding regions exposed through protective films provided on circuit patterns onto which components are soldered
US9123710B2 (en) Semiconductor device having a semiconductor chip and wiring
JP5083294B2 (en) Power semiconductor device
WO2018012281A1 (en) Semiconductor device
WO2014132897A1 (en) Semiconductor device
WO2014181638A1 (en) Method for manufacturing semiconductor device
JP2017069351A (en) Semiconductor device
JP6887476B2 (en) Semiconductor power module
JP7334655B2 (en) semiconductor equipment
JP2017135310A (en) Semiconductor device
JP2019169512A (en) Semiconductor package

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14756326

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14756326

Country of ref document: EP

Kind code of ref document: A1