WO2014181638A1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
WO2014181638A1
WO2014181638A1 PCT/JP2014/060528 JP2014060528W WO2014181638A1 WO 2014181638 A1 WO2014181638 A1 WO 2014181638A1 JP 2014060528 W JP2014060528 W JP 2014060528W WO 2014181638 A1 WO2014181638 A1 WO 2014181638A1
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WO
WIPO (PCT)
Prior art keywords
adherend
semiconductor device
wiring
electrode terminal
bonding surface
Prior art date
Application number
PCT/JP2014/060528
Other languages
French (fr)
Japanese (ja)
Inventor
貴弘 杉村
浩史 野津
Original Assignee
住友電気工業株式会社
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Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Publication of WO2014181638A1 publication Critical patent/WO2014181638A1/en

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    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/049—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • a case-type semiconductor device is known as an example of a semiconductor device (see Non-Patent Document 1).
  • Such a semiconductor device is manufactured by connecting a semiconductor chip accommodated in a case and an electrode terminal attached to the case with a wire by wire bonding.
  • a wire is connected to a semiconductor chip by placing the wire on the semiconductor chip and applying pressure and ultrasonic waves.
  • the wire is connected to the electrode terminal by placing the wire on the electrode terminal and applying pressure and ultrasonic waves.
  • the relative positions of the electrode terminals with respect to the semiconductor chip are fixed and cannot be changed after wire bonding. Therefore, the degree of freedom in designing the semiconductor device is not high.
  • This application aims at providing the manufacturing method of a semiconductor device with high design freedom.
  • a method of manufacturing a semiconductor device includes a connection step of connecting a first adherend and a second adherend by wiring, and after the connection step, the first adherend and the second adherend.
  • FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II in FIG. It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows typically the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment.
  • a method of manufacturing a semiconductor device includes a connection step of connecting a first adherend and a second adherend by wiring, and after the connection step, the first adherend and the second adherend.
  • the relative position of the first adherend to the second adherend can be arbitrarily changed after the connecting step. Therefore, the degree of freedom in designing the semiconductor device is increased.
  • a first plane including a bonding surface between the first adherend and the wiring is disposed so as to face a second plane including a bonding surface between the second adherend and the wiring.
  • At least one of the first adherend and the second adherend may be moved.
  • the semiconductor device can be reduced in size as viewed from the normal direction of the joint surface between the second adherend and the wiring.
  • a first plane including a bonding surface between the first adherend and the wiring is substantially orthogonal to a second plane including a bonding surface between the second adherend and the wiring. At least one of the first adherend and the second adherend may be moved.
  • the semiconductor device can be reduced in size as viewed from the normal direction of the joint surface between the second adherend and the wiring.
  • the first adherend may be fixed to the thermosetting resin portion.
  • the heat resistance of the semiconductor device can be improved compared to gel or the like.
  • the first adherend may be fixed to a case.
  • the first adherend may be fixed to a support member attached to the case.
  • the wire may be a wire or a bonding ribbon.
  • FIG. 1 is a perspective view schematically showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II in FIG.
  • a semiconductor device 10 shown in FIGS. 1 and 2 is a power semiconductor device used for a power source or the like, for example.
  • the semiconductor device 10 includes an electrode terminal 12A, a semiconductor chip 14A, and a wiring 16A.
  • the wiring 16A connects the electrode terminal 12A and the semiconductor chip 14A.
  • a bonding surface 11A is formed between the electrode terminal 12A and the wiring 16A.
  • a bonding surface 13A is formed between the semiconductor chip 14A and the wiring 16A.
  • the electrode terminal 12A is electrically connected to the surface electrode of the semiconductor chip 14A.
  • the first plane PA1 including the bonding surface 11A is disposed to face the second plane PA2 including the bonding surface 13A.
  • the semiconductor device 10 may include an electrode terminal 12B, a wiring board 20, and a wiring 16B.
  • the wiring 16B connects between the electrode terminal 12B and the wiring board 20.
  • a bonding surface 11B is formed between the electrode terminal 12B and the wiring 16B.
  • a bonding surface 13B is formed between the wiring board 20 and the wiring 16B.
  • the first plane PB1 including the bonding surface 11B is disposed to face the second plane PB2 including the bonding surface 13B.
  • Semiconductor chips 14A and 14B can be arranged on the wiring board 20.
  • the semiconductor chips 14A and 14B may have the same structure.
  • the semiconductor chips 14A and 14B can be mounted on the wiring board 20 via adhesive layers 42 made of a material containing lead-containing metal solder, lead-free metal solder, conductive resin, or the like.
  • the wiring substrate 20 includes an insulating substrate 22, a wiring pattern layer 24 provided on the surface of the insulating substrate 22, and a heat dissipation layer 26 provided on the back surface of the insulating substrate 22.
  • the heat dissipation layer 26 may be provided on the entire back surface of the insulating substrate 22.
  • the semiconductor chips 14A and 14B are connected to the wiring pattern layer 24 through the adhesive layer 42, respectively. Thereby, the electrode terminal 12B is electrically connected to the back electrode of the semiconductor chip 14A.
  • the electrode terminal 12A may include a first portion 18A extending along the bonding surface 11A and a second portion 19A orthogonal to the bonding surface 11A.
  • the electrode terminal 12B can include a first portion 18B extending along the bonding surface 11B and a second portion 19B orthogonal to the bonding surface 11B.
  • the electrode terminals 12A and 12B are, for example, bent metal plates.
  • Examples of the semiconductor chips 14A and 14B include bipolar transistors, MOS-FETs, transistors such as insulated gate bipolar transistors (IGBT), and diodes.
  • Examples of the material of the semiconductor chips 14A and 14B include a wide band gap semiconductor, silicon and other semiconductors.
  • a wide band gap semiconductor has a band gap larger than that of silicon.
  • Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and diamond.
  • the wirings 16A and 16B have flexibility, for example.
  • the wirings 16A and 16B may be wires or bonding ribbons.
  • the cross-sectional shapes of the wirings 16A and 16B are, for example, circular.
  • the diameters of the wirings 16A and 16B are, for example, 100 to 500 ⁇ m.
  • Examples of the material of the wirings 16A and 16B include metals such as aluminum, gold, and copper.
  • Examples of the material of the wiring pattern layer 24 include metals such as copper and copper alloys.
  • An example of the material of the insulating substrate 22 includes ceramic such as alumina.
  • Examples of the material of the heat dissipation layer 26 include metals such as copper and copper alloys.
  • the heat dissipation layer 26 is bonded to the heat sink 32 via an adhesive layer 44 including, for example, solder.
  • An example of the material of the heat sink 32 includes a metal.
  • the semiconductor chips 14A and 14B and the wiring board 20 can be accommodated in the case 30.
  • the case 30 is, for example, a box-shaped electrically insulating case that accommodates the semiconductor chips 14A and 14B.
  • the case 30 has a cylindrical shape, for example.
  • One opening of the case 30 can be sealed by a heat sink 32.
  • the other opening of the case 30 can be sealed with a lid.
  • the material of the case 30 include resins such as engineering plastics such as polybutylene terephthalate (PBT) or polyphenylene sulfide (PPS) resin.
  • the lid material include a thermoplastic resin.
  • the case 30 can be filled with a thermosetting resin portion 50.
  • thermosetting resin portion 50 fixes the electrode terminals 12A and 12B and the wirings 16A and 16B.
  • the second portions 19A and 19B of the electrode terminals 12A and 12B protrude outward from the thermosetting resin portion 50.
  • FIG 3 and 4 are cross-sectional views schematically showing one process of the method for manufacturing a semiconductor device according to the present embodiment.
  • the semiconductor device 10 is manufactured as follows, for example.
  • the electrode terminal 12A as the first adherend and the semiconductor chip 14A as the second adherend are connected by the wiring 16A.
  • the bonding surface 11A is formed between the electrode terminal 12A and the wiring 16A.
  • a bonding surface 13A is formed between the semiconductor chip 14A and the wiring 16A.
  • the bonding surface 11A is substantially parallel to the bonding surface 13A. “Substantially parallel” means that the angle formed between the bonding surface 11A and the bonding surface 13A is ⁇ 5 degrees or less. Normally, in wire bonding, the two bonding surfaces 11A and 13A are parallel to each other.
  • the wiring 16A is connected to the electrode terminal 12A and the semiconductor chip 14A, for example, by wire bonding.
  • the electrode terminal 12A and the semiconductor chip 14A are held by the jig 60.
  • the second portion 19 ⁇ / b> A of the electrode terminal 12 ⁇ / b> A is inserted into a hole 62 ⁇ / b> A formed in the jig 60.
  • the wiring 16A is bonded to the electrode terminal 12A by placing the wiring 16A on the electrode terminal 12A and applying pressure and ultrasonic waves.
  • the wiring 16A is bonded to the semiconductor chip 14A by placing the wiring 16A on the semiconductor chip 14A and applying pressure and ultrasonic waves.
  • the electrode terminal 12B as the first adherend and the wiring board 20 as the second adherend are connected by the wiring 16B.
  • the joint surface 11B is formed between the electrode terminal 12B and the wiring 16B.
  • a bonding surface 13B is formed between the wiring board 20 and the wiring 16B.
  • the bonding surface 11B is substantially parallel to the bonding surface 13B. “Substantially parallel” means that the angle formed between the joint surface 11B and the joint surface 13B is ⁇ 5 degrees or less. Normally, in wire bonding, the two bonding surfaces 11B and 13B are parallel to each other.
  • the wiring 16B is connected to the electrode terminal 12B and the wiring board 20 by wire bonding, for example.
  • the electrode terminal 12 ⁇ / b> B and the wiring substrate 20 are held by the jig 60.
  • the second portion 19B of the electrode terminal 12B is inserted into a hole 62B formed in the jig 60.
  • the wiring 16B is bonded to the electrode terminal 12B by placing the wiring 16B on the electrode terminal 12B and applying pressure and ultrasonic waves.
  • the wiring 16B is bonded to the wiring board 20 by placing the wiring 16B on the wiring board 20 and applying pressure and ultrasonic waves.
  • the electrode terminal 12A is moved relative to the semiconductor chip 14A by moving at least one of the electrode terminal 12A and the semiconductor chip 14A.
  • the electrode terminal 12A is moved from the first position to the second position.
  • the electrodes are arranged such that the first plane PA1 including the bonding surface 11A between the electrode terminal 12A and the wiring 16A is opposed to the second plane PA2 including the bonding surface 13A between the semiconductor chip 14A and the wiring 16A. At least one of the terminal 12A and the semiconductor chip 14A is moved.
  • the electrode terminal 12B is moved relative to the wiring board 20 by moving at least one of the electrode terminal 12B and the wiring board 20.
  • the electrode terminal 12B is moved from the first position to the second position.
  • the first plane PB1 including the bonding surface 11B between the electrode terminal 12B and the wiring 16B is disposed to face the second plane PB2 including the bonding surface 13B between the wiring board 20 and the wiring 16B. At least one of the terminal 12B and the wiring board 20 is moved.
  • the relative position of the electrode terminal 12A with respect to the semiconductor chip 14A is fixed.
  • the relative position of the electrode terminal 12B with respect to the wiring board 20 is fixed.
  • the electrode terminals 12 ⁇ / b> A and 12 ⁇ / b> B are fixed to the thermosetting resin portion 50.
  • the wirings 16 ⁇ / b> A and 16 ⁇ / b> B can also be fixed to the thermosetting resin part 50.
  • the thermosetting resin portion 50 can be formed by pouring an uncured thermosetting resin material into the case 30 and heating.
  • the wiring board 20 is bonded to the heat sink 32 through the adhesive layer 44 as necessary.
  • the relative position of the electrode terminal 12A with respect to the semiconductor chip 14A can be arbitrarily changed after the connecting step.
  • the relative position of the electrode terminal 12B with respect to the wiring board 20 can be arbitrarily changed after the connecting step. Therefore, the degree of freedom in designing the semiconductor device 10 is increased.
  • the normal lines of the bonding surfaces 11A and 13A are moved.
  • the semiconductor device 10 can be reduced in size when viewed from the direction.
  • the electrode terminal 12B and the wiring board 20 is moved so that the first plane PB1 including the bonding surface 11B is opposed to the second plane PB2 including the bonding surface 13B, the normal lines of the bonding surfaces 11B and 13B are moved.
  • the semiconductor device 10 can be reduced in size when viewed from the direction.
  • thermosetting resin portion 50 fixes the electrode terminals 12A and 12B
  • the heat resistance of the semiconductor device 10 can be improved compared to gel or the like.
  • the material of the semiconductor chips 14A and 14B includes a wide band gap semiconductor, a large current flows through the semiconductor device 10, and thus the semiconductor device 10 tends to become high temperature. Even in such a case, the reliability of the semiconductor device 10 can be improved.
  • FIG. 5 is a cross-sectional view schematically showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment.
  • the semiconductor device 110 shown in FIG. 5 has the same configuration as the semiconductor device 10 except that the electrode terminals 112A and 112B are provided instead of the electrode terminals 12A and 12B, respectively.
  • the electrode terminals 112A and 112B are metal plates that are not bent, for example.
  • the electrode terminal 112A is arranged so that the first plane PA1 including the bonding surface 11A between the electrode terminal 112A and the wiring 16A is substantially orthogonal to the second plane PA2 including the bonding surface 13A between the semiconductor chip 14A and the wiring 16A.
  • substantially orthogonal means that the angle formed by the first plane PA1 and the second plane PA2 is 90 ⁇ 5 degrees or less.
  • the electrode terminal 112B is disposed so that the first plane PB1 including the bonding surface 11B between the electrode terminal 112B and the wiring 16B is substantially orthogonal to the second plane PB2 including the bonding surface 13B between the wiring board 20 and the wiring 16B.
  • substantially orthogonal means that the angle formed by the first plane PB1 and the second plane PB2 is 90 ⁇ 5 degrees or less.
  • FIG. 6 and 7 are cross-sectional views schematically showing one step of the method of manufacturing a semiconductor device according to the second embodiment.
  • the semiconductor device 110 is manufactured as follows, for example.
  • the electrode terminal 112A as the first adherend and the semiconductor chip 14A as the second adherend are connected by the wiring 16A.
  • the electrode terminal 112B as the first adherend and the wiring board 20 as the second adherend are connected by the wiring 16B.
  • the connection process of the present embodiment is performed in the same manner as the connection process of the first embodiment except that the electrode terminals 112A and 112B are used instead of the electrode terminals 12A and 12B, respectively.
  • the electrode terminals 112A and 112B are metal plates that are not bent, for example. Therefore, it is not necessary to form the holes 62A and 62B in the jig 60.
  • the electrode terminal 112A is moved relative to the semiconductor chip 14A by moving at least one of the electrode terminal 112A and the semiconductor chip 14A.
  • the electrode terminals are arranged such that the first plane PA1 including the bonding surface 11A between the electrode terminal 112A and the wiring 16A is substantially orthogonal to the second plane PA2 including the bonding surface 13A between the semiconductor chip 14A and the wiring 16A. At least one of 112A and semiconductor chip 14A is moved.
  • substantially orthogonal means that the angle formed by the first plane PA1 and the second plane PA2 is 90 ⁇ 5 degrees or less.
  • the electrode terminal 112B is moved relative to the wiring board 20 by moving at least one of the electrode terminal 112B and the wiring board 20.
  • the electrode terminal 112B and the wiring 16B are connected so that the first plane PB1 including the bonding surface 11B is substantially orthogonal to the second plane PB2 including the bonding surface 13B of the wiring board 20 and the wiring 16B. At least one of 112B and wiring board 20 is moved.
  • substantially orthogonal means that the angle formed by the first plane PB1 and the second plane PB2 is 90 ⁇ 5 degrees or less.
  • thermosetting resin portion 50 fixes the electrode terminals 112A and 112B.
  • the same effect as that of the first embodiment can be obtained. Furthermore, even if a metal plate that is not bent is used as the electrode terminals 112A and 112B, the electrode terminals 112A and 112B can be projected in a direction along the bonding surfaces 11A and 11B.
  • FIG. 8 is a perspective view schematically showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the third embodiment.
  • the semiconductor device 210 shown in FIG. 8 includes electrode terminals 212A and 212B (first adherend) instead of the electrode terminals 12A and 12B, respectively, and includes an insulating material 250 instead of the thermosetting resin portion 50.
  • the insulating material 250 is a gel such as a silicone gel.
  • the electrode terminals 212A and 212B are fixed to the case 30.
  • the electrode terminal 212 ⁇ / b> A may include a first portion 219 ⁇ / b> A fixed to the case 30 and a second portion 218 ⁇ / b> A connected to the first portion 219 ⁇ / b> A and protruding outward from the case 30.
  • a wiring 16A is connected to the first portion 219A.
  • the first portion 219A is, for example, a metal plate that crosses one opening of the case 30.
  • the second portion 218A is, for example, a metal plate that is connected to the edge of the first portion 219A and is orthogonal to the first portion 219A.
  • the electrode terminal 212B may include a first portion 219B fixed to the case 30 and a second portion 218B connected to the first portion 219B and protruding outward from the case 30.
  • a wiring 16B is connected to the first portion 219B.
  • the first portion 219B is, for example, a metal plate that crosses one opening of the case 30.
  • the second portion 218B is, for example, a metal plate that is connected to the edge of the first portion 219B and is orthogonal to the first portion 219B.
  • the semiconductor device 210 can be manufactured through a connection process (see FIG. 3), a movement process (see FIG. 4), and a fixing process.
  • the connecting process and the moving process are performed in the same manner as in the first embodiment.
  • the fixing process as shown in FIG. 8, the electrode terminals 212 ⁇ / b> A and 212 ⁇ / b> B are fixed to the case 30. Both ends of the first portion 219A of the electrode terminal 212A can be fixed to the case 30. Both ends of the first portion 219B of the electrode terminal 212B can be fixed to the case 30. Thereafter, the insulating material 250 is filled in the case 30 as necessary.
  • the same effect as that of the first embodiment can be obtained. Furthermore, the electrode terminals 212A and 212B can be fixed to the case 30 with high positional accuracy.
  • FIG. 9 is a perspective view schematically showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the fourth embodiment.
  • a semiconductor device 310 shown in FIG. 9 has the same configuration as the semiconductor device 10 except that it includes an insulating material 250 instead of the thermosetting resin portion 50 and further includes support members 319A and 319B.
  • the electrode terminals 12A and 12B are fixed to support members 319A and 319B attached to the case 30.
  • the electrode terminals 12A and 12B may be fixed to the case 30.
  • the support members 319A and 319B are, for example, insulating plates that cross one opening of the case 30.
  • An opening 318A for fitting the electrode terminal 12A is formed in the support member 319A.
  • An opening 318B for fitting the electrode terminal 12B is formed in the support member 319B.
  • the semiconductor device 310 can be manufactured through a connection process (see FIG. 3), a movement process (see FIG. 4), and a fixing process.
  • the connecting process and the moving process are performed in the same manner as in the first embodiment.
  • the fixing step as shown in FIG. 9, the electrode terminals 12 ⁇ / b> A and 12 ⁇ / b> B are fixed to support members 319 ⁇ / b> A and 319 ⁇ / b> B attached to the case 30. Thereafter, the insulating material 250 is filled in the case 30 as necessary.
  • the same effect as that of the first embodiment can be obtained. Furthermore, the electrode terminals 12A and 12B can be fixed to the support members 319A and 319B with high positional accuracy. Moreover, the electrode terminals 12A and 12B can be electrically insulated from the case 30 by using the insulating support members 319A and 319B.
  • the semiconductor devices 210 and 310 may include the thermosetting resin portion 50 instead of the insulating material 250.
  • the semiconductor device 210 may include electrode terminals 112A and 112B instead of the electrode terminals 212A and 212B.
  • the electrode terminals 112 ⁇ / b> A and 112 ⁇ / b> B have a portion fixed to the case 30.
  • the semiconductor device 310 may include electrode terminals 112A and 112B instead of the electrode terminals 12A and 12B. In this case, the electrode terminals 112A and 112B are fixed to the support members 319A and 319B.
  • Each of the first adherend and the second adherend may be an electrode terminal, a semiconductor chip, a wiring board, or the like.

Abstract

In the present invention, a method for manufacturing a semiconductor device comprises: a connecting step for connecting a first adherend and a second adherend to each other by means of wiring; a movement step, subsequent to the connecting step, for moving at least one of the first adherend and the second adherend, thereby moving the first adherend relative to the second adherend; and a fixing step for fixing the relative position of the first adherend in relation to the second adherend.

Description

半導体装置の製造方法Manufacturing method of semiconductor device
　本発明は、半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device.
　半導体装置の例として、ケース型の半導体装置が知られている（非特許文献１参照）。このような半導体装置は、ワイヤボンディングにより、ケース内に収容された半導体チップと、ケースに取り付けられた電極端子とをワイヤにより接続することによって製造される。 A case-type semiconductor device is known as an example of a semiconductor device (see Non-Patent Document 1). Such a semiconductor device is manufactured by connecting a semiconductor chip accommodated in a case and an electrode terminal attached to the case with a wire by wire bonding.
　ワイヤボンディングでは、ワイヤを半導体チップ上に載せて圧力及び超音波を印加することによって、ワイヤを半導体チップに接続する。同様に、ワイヤを電極端子上に載せて圧力及び超音波を印加することによって、ワイヤを電極端子に接続する。半導体チップに対する電極端子の相対的な位置は固定されており、ワイヤボンディング後に変えることができない。よって、半導体装置の設計自由度は高くない。 In wire bonding, a wire is connected to a semiconductor chip by placing the wire on the semiconductor chip and applying pressure and ultrasonic waves. Similarly, the wire is connected to the electrode terminal by placing the wire on the electrode terminal and applying pressure and ultrasonic waves. The relative positions of the electrode terminals with respect to the semiconductor chip are fixed and cannot be changed after wire bonding. Therefore, the degree of freedom in designing the semiconductor device is not high.
　本願は、設計自由度の高い半導体装置の製造方法を提供することを目的とする。 This application aims at providing the manufacturing method of a semiconductor device with high design freedom.
　本願の半導体装置の製造方法は、第１被着体と第２被着体との間を配線により接続する接続工程と、前記接続工程の後、前記第１被着体及び前記第２被着体の少なくとも１つを移動することによって、前記第１被着体を前記第２被着体に対して相対的に移動する移動工程と、前記第２被着体に対する前記第１被着体の相対的な位置を固定する固定工程と、を含む。 A method of manufacturing a semiconductor device according to the present application includes a connection step of connecting a first adherend and a second adherend by wiring, and after the connection step, the first adherend and the second adherend. A moving step of moving the first adherend relative to the second adherend by moving at least one of the bodies; and a step of moving the first adherend relative to the second adherend. A fixing step of fixing a relative position.
　上記によれば、設計自由度の高い半導体装置の製造方法が提供され得る。 According to the above, a method for manufacturing a semiconductor device with a high degree of design freedom can be provided.
第１実施形態に係る半導体装置の製造方法により製造される半導体装置を模式的に示す斜視図である。It is a perspective view showing typically the semiconductor device manufactured by the manufacturing method of the semiconductor device concerning a 1st embodiment. 図１のＩＩ－ＩＩ線に沿った半導体装置の断面図である。FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II in FIG. 第１実施形態に係る半導体装置の製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第２実施形態に係る半導体装置の製造方法により製造される半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第３実施形態に係る半導体装置の製造方法により製造される半導体装置を模式的に示す斜視図である。It is a perspective view which shows typically the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. 第４実施形態に係る半導体装置の製造方法により製造される半導体装置を模式的に示す斜視図である。It is a perspective view which shows typically the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on 4th Embodiment.
　最初に本願発明の実施形態を列記して説明する。 First, embodiments of the present invention will be listed and described.
　本願の半導体装置の製造方法は、第１被着体と第２被着体との間を配線により接続する接続工程と、前記接続工程の後、前記第１被着体及び前記第２被着体の少なくとも１つを移動することによって、前記第１被着体を前記第２被着体に対して相対的に移動する移動工程と、前記第２被着体に対する前記第１被着体の相対的な位置を固定する固定工程と、を含む。 A method of manufacturing a semiconductor device according to the present application includes a connection step of connecting a first adherend and a second adherend by wiring, and after the connection step, the first adherend and the second adherend. A moving step of moving the first adherend relative to the second adherend by moving at least one of the bodies; and a step of moving the first adherend relative to the second adherend. A fixing step of fixing a relative position.
　この方法では、接続工程後に第２被着体に対する第１被着体の相対的な位置を任意に変えることができる。よって、半導体装置の設計自由度が高くなる。 In this method, the relative position of the first adherend to the second adherend can be arbitrarily changed after the connecting step. Therefore, the degree of freedom in designing the semiconductor device is increased.
　前記移動工程では、前記第１被着体と前記配線との接合面を含む第１平面が、前記第２被着体と前記配線との接合面を含む第２平面に対向配置されるように、前記第１被着体及び前記第２被着体の少なくとも１つを移動してもよい。 In the moving step, a first plane including a bonding surface between the first adherend and the wiring is disposed so as to face a second plane including a bonding surface between the second adherend and the wiring. , At least one of the first adherend and the second adherend may be moved.
　この場合、第２被着体と配線との接合面の法線方向から見て、半導体装置を小型化することができる。 In this case, the semiconductor device can be reduced in size as viewed from the normal direction of the joint surface between the second adherend and the wiring.
　前記移動工程では、前記第１被着体と前記配線との接合面を含む第１平面が、前記第２被着体と前記配線との接合面を含む第２平面と略直交するように、前記第１被着体及び前記第２被着体の少なくとも１つを移動してもよい。 In the moving step, a first plane including a bonding surface between the first adherend and the wiring is substantially orthogonal to a second plane including a bonding surface between the second adherend and the wiring. At least one of the first adherend and the second adherend may be moved.
　この場合、第２被着体と配線との接合面の法線方向から見て、半導体装置を小型化することができる。 In this case, the semiconductor device can be reduced in size as viewed from the normal direction of the joint surface between the second adherend and the wiring.
　前記固定工程では、前記第１被着体を熱硬化性樹脂部に固定してもよい。 In the fixing step, the first adherend may be fixed to the thermosetting resin portion.
　この場合、ゲル等に比べて半導体装置の耐熱性を向上させることができる。 In this case, the heat resistance of the semiconductor device can be improved compared to gel or the like.
　前記固定工程では、前記第１被着体をケースに固定してもよい。 In the fixing step, the first adherend may be fixed to a case.
　前記固定工程では、前記第１被着体を、ケースに取り付けられた支持部材に固定してもよい。 In the fixing step, the first adherend may be fixed to a support member attached to the case.
　前記配線が、ワイヤ又はボンディングリボンであってもよい。 The wire may be a wire or a bonding ribbon.
　以下、添付図面を参照しながら本発明の実施形態が詳細に説明される。図面の説明において、同一又は同等の要素には同一符号が用いられ、重複する説明は省略される。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are used for the same or equivalent elements, and redundant descriptions are omitted.
（第１実施形態）
　図１は、第１実施形態に係る半導体装置の製造方法により製造される半導体装置を模式的に示す斜視図である。図２は、図１のＩＩ－ＩＩ線に沿った半導体装置の断面図である。図１及び図２に示される半導体装置１０は、例えば電源等に使用される電力用半導体装置である。 (First embodiment)
FIG. 1 is a perspective view schematically showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II in FIG. A semiconductor device 10 shown in FIGS. 1 and 2 is a power semiconductor device used for a power source or the like, for example.
　半導体装置１０は、電極端子１２Ａ、半導体チップ１４Ａ、及び配線１６Ａを備える。配線１６Ａは、電極端子１２Ａと半導体チップ１４Ａとの間を接続する。電極端子１２Ａと配線１６Ａとの間には接合面１１Ａが形成される。半導体チップ１４Ａと配線１６Ａとの間には接合面１３Ａが形成される。これにより、電極端子１２Ａが半導体チップ１４Ａの表面電極に電気的に接続される。本実施形態では、接合面１１Ａを含む第１平面ＰＡ１が接合面１３Ａを含む第２平面ＰＡ２に対向配置される。 The semiconductor device 10 includes an electrode terminal 12A, a semiconductor chip 14A, and a wiring 16A. The wiring 16A connects the electrode terminal 12A and the semiconductor chip 14A. A bonding surface 11A is formed between the electrode terminal 12A and the wiring 16A. A bonding surface 13A is formed between the semiconductor chip 14A and the wiring 16A. Thereby, the electrode terminal 12A is electrically connected to the surface electrode of the semiconductor chip 14A. In the present embodiment, the first plane PA1 including the bonding surface 11A is disposed to face the second plane PA2 including the bonding surface 13A.
　半導体装置１０は、電極端子１２Ｂ、配線基板２０、及び配線１６Ｂを備え得る。配線１６Ｂは、電極端子１２Ｂと配線基板２０との間を接続する。電極端子１２Ｂと配線１６Ｂとの間には接合面１１Ｂが形成される。配線基板２０と配線１６Ｂとの間には接合面１３Ｂが形成される。本実施形態では、接合面１１Ｂを含む第１平面ＰＢ１が接合面１３Ｂを含む第２平面ＰＢ２に対向配置される。 The semiconductor device 10 may include an electrode terminal 12B, a wiring board 20, and a wiring 16B. The wiring 16B connects between the electrode terminal 12B and the wiring board 20. A bonding surface 11B is formed between the electrode terminal 12B and the wiring 16B. A bonding surface 13B is formed between the wiring board 20 and the wiring 16B. In the present embodiment, the first plane PB1 including the bonding surface 11B is disposed to face the second plane PB2 including the bonding surface 13B.
　配線基板２０上には、半導体チップ１４Ａ，１４Ｂが配置され得る。半導体チップ１４Ａ，１４Ｂは、同じ構造を有してもよい。半導体チップ１４Ａ，１４Ｂは、鉛入り金属半田、鉛を含まない金属半田又は導電性樹脂等を含む材料から構成される接着層４２をそれぞれ介して配線基板２０に実装され得る。配線基板２０は、絶縁性基板２２と、絶縁性基板２２の表面に設けられた配線パターン層２４と、絶縁性基板２２の裏面に設けられた放熱層２６とを備える。放熱層２６は絶縁性基板２２の裏面全体に設けられ得る。半導体チップ１４Ａ，１４Ｂは、接着層４２をそれぞれ介して配線パターン層２４に接続される。これにより、電極端子１２Ｂが半導体チップ１４Ａの裏面電極に電気的に接続される。 Semiconductor chips 14A and 14B can be arranged on the wiring board 20. The semiconductor chips 14A and 14B may have the same structure. The semiconductor chips 14A and 14B can be mounted on the wiring board 20 via adhesive layers 42 made of a material containing lead-containing metal solder, lead-free metal solder, conductive resin, or the like. The wiring substrate 20 includes an insulating substrate 22, a wiring pattern layer 24 provided on the surface of the insulating substrate 22, and a heat dissipation layer 26 provided on the back surface of the insulating substrate 22. The heat dissipation layer 26 may be provided on the entire back surface of the insulating substrate 22. The semiconductor chips 14A and 14B are connected to the wiring pattern layer 24 through the adhesive layer 42, respectively. Thereby, the electrode terminal 12B is electrically connected to the back electrode of the semiconductor chip 14A.
　電極端子１２Ａは、接合面１１Ａに沿って延びる第１部分１８Ａと、接合面１１Ａに直交する第２部分１９Ａとを備え得る。電極端子１２Ｂは、接合面１１Ｂに沿って延びる第１部分１８Ｂと、接合面１１Ｂに直交する第２部分１９Ｂとを備え得る。電極端子１２Ａ，１２Ｂは、例えば折り曲げられた金属板である。 The electrode terminal 12A may include a first portion 18A extending along the bonding surface 11A and a second portion 19A orthogonal to the bonding surface 11A. The electrode terminal 12B can include a first portion 18B extending along the bonding surface 11B and a second portion 19B orthogonal to the bonding surface 11B. The electrode terminals 12A and 12B are, for example, bent metal plates.
　半導体チップ１４Ａ，１４Ｂの例は、バイポーラトランジスタ、ＭＯＳ－ＦＥＴ、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）等のトランジスタ、ダイオードを含む。半導体チップ１４Ａ，１４Ｂの材料の例は、ワイドバンドギャップ半導体、シリコンその他の半導体を含む。ワイドバンドギャップ半導体は、シリコンのバンドギャップよりも大きいバンドギャップを有する。ワイドバンドギャップ半導体の例は、シリコンカーバイド（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンドを含む。 Examples of the semiconductor chips 14A and 14B include bipolar transistors, MOS-FETs, transistors such as insulated gate bipolar transistors (IGBT), and diodes. Examples of the material of the semiconductor chips 14A and 14B include a wide band gap semiconductor, silicon and other semiconductors. A wide band gap semiconductor has a band gap larger than that of silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and diamond.
　配線１６Ａ，１６Ｂは、例えば可撓性を有する。配線１６Ａ，１６Ｂは、ワイヤ又はボンディングリボンであってもよい。配線１６Ａ，１６Ｂの断面形状は例えば円形である。配線１６Ａ，１６Ｂの径は、例えば１００～５００μｍである。配線１６Ａ，１６Ｂの材料の例は、アルミニウム、金、銅等の金属を含む。 The wirings 16A and 16B have flexibility, for example. The wirings 16A and 16B may be wires or bonding ribbons. The cross-sectional shapes of the wirings 16A and 16B are, for example, circular. The diameters of the wirings 16A and 16B are, for example, 100 to 500 μm. Examples of the material of the wirings 16A and 16B include metals such as aluminum, gold, and copper.
　配線パターン層２４の材料の例は、銅及び銅合金等の金属を含む。絶縁性基板２２の材料の例は、アルミナ等のセラミックを含む。放熱層２６の材料の例は、銅及び銅合金等の金属を含む。放熱層２６は、例えば半田等を含む接着層４４を介してヒートシンク３２に接着される。ヒートシンク３２の材料の例は、金属を含む。 Examples of the material of the wiring pattern layer 24 include metals such as copper and copper alloys. An example of the material of the insulating substrate 22 includes ceramic such as alumina. Examples of the material of the heat dissipation layer 26 include metals such as copper and copper alloys. The heat dissipation layer 26 is bonded to the heat sink 32 via an adhesive layer 44 including, for example, solder. An example of the material of the heat sink 32 includes a metal.
　半導体チップ１４Ａ，１４Ｂ及び配線基板２０は、ケース３０内に収容され得る。ケース３０は、例えば、半導体チップ１４Ａ，１４Ｂを収容する箱状の電気絶縁性のケースである。ケース３０は、例えば筒状である。ケース３０の一方の開口はヒートシンク３２によって封止され得る。ケース３０の他方の開口は蓋によって封止され得る。ケース３０の材料の例は、ポリブチレンテレフタレート（ＰＢＴ）又はポリフェニレンサルファイド（ＰＰＳ）樹脂といったエンジニヤリングプラスチック等の樹脂を含む。蓋の材料の例は熱可塑性樹脂を含む。ケース３０内には熱硬化性樹脂部５０が充填され得る。 The semiconductor chips 14A and 14B and the wiring board 20 can be accommodated in the case 30. The case 30 is, for example, a box-shaped electrically insulating case that accommodates the semiconductor chips 14A and 14B. The case 30 has a cylindrical shape, for example. One opening of the case 30 can be sealed by a heat sink 32. The other opening of the case 30 can be sealed with a lid. Examples of the material of the case 30 include resins such as engineering plastics such as polybutylene terephthalate (PBT) or polyphenylene sulfide (PPS) resin. Examples of the lid material include a thermoplastic resin. The case 30 can be filled with a thermosetting resin portion 50.
　熱硬化性樹脂部５０は、電極端子１２Ａ，１２Ｂ及び配線１６Ａ，１６Ｂを固定する。電極端子１２Ａ，１２Ｂの第２部分１９Ａ，１９Ｂは、熱硬化性樹脂部５０から外側に突出する。 The thermosetting resin portion 50 fixes the electrode terminals 12A and 12B and the wirings 16A and 16B. The second portions 19A and 19B of the electrode terminals 12A and 12B protrude outward from the thermosetting resin portion 50.
　図３及び図４は、本実施形態に係る半導体装置の製造方法の一工程を模式的に示す断面図である。半導体装置１０は、例えば以下のように製造される。 3 and 4 are cross-sectional views schematically showing one process of the method for manufacturing a semiconductor device according to the present embodiment. The semiconductor device 10 is manufactured as follows, for example.
（接続工程）
　まず、図３（ａ）に示されるように、第１被着体としての電極端子１２Ａと第２被着体としての半導体チップ１４Ａとの間を配線１６Ａにより接続する。これにより、電極端子１２Ａと配線１６Ａとの間に接合面１１Ａが形成される。半導体チップ１４Ａと配線１６Ａとの間に接合面１３Ａが形成される。接続工程において、接合面１１Ａは接合面１３Ａと略平行である。略平行とは、接合面１１Ａと接合面１３Ａとのなす角度が±５度以下であることを意味する。通常、ワイヤボンディングでは、２つの接合面１１Ａ，１３Ａが互いに平行になる。 (Connection process)
First, as shown in FIG. 3A, the electrode terminal 12A as the first adherend and the semiconductor chip 14A as the second adherend are connected by the wiring 16A. Thereby, the bonding surface 11A is formed between the electrode terminal 12A and the wiring 16A. A bonding surface 13A is formed between the semiconductor chip 14A and the wiring 16A. In the connecting step, the bonding surface 11A is substantially parallel to the bonding surface 13A. “Substantially parallel” means that the angle formed between the bonding surface 11A and the bonding surface 13A is ± 5 degrees or less. Normally, in wire bonding, the two bonding surfaces 11A and 13A are parallel to each other.
　配線１６Ａは、例えばワイヤボンディングにより、電極端子１２Ａ及び半導体チップ１４Ａに接続される。ワイヤボンディングを行う際に、電極端子１２Ａ及び半導体チップ１４Ａは、治具６０によって保持される。電極端子１２Ａの第２部分１９Ａは、治具６０に形成された孔６２Ａ内に挿入される。配線１６Ａを電極端子１２Ａ上に載せて圧力及び超音波を印加することによって、配線１６Ａが電極端子１２Ａに接合される。同様に、配線１６Ａを半導体チップ１４Ａ上に載せて圧力及び超音波を印加することによって、配線１６Ａが半導体チップ１４Ａに接合される。 The wiring 16A is connected to the electrode terminal 12A and the semiconductor chip 14A, for example, by wire bonding. When wire bonding is performed, the electrode terminal 12A and the semiconductor chip 14A are held by the jig 60. The second portion 19 </ b> A of the electrode terminal 12 </ b> A is inserted into a hole 62 </ b> A formed in the jig 60. The wiring 16A is bonded to the electrode terminal 12A by placing the wiring 16A on the electrode terminal 12A and applying pressure and ultrasonic waves. Similarly, the wiring 16A is bonded to the semiconductor chip 14A by placing the wiring 16A on the semiconductor chip 14A and applying pressure and ultrasonic waves.
　また、図３（ｂ）に示されるように、第１被着体としての電極端子１２Ｂと第２被着体としての配線基板２０との間を配線１６Ｂにより接続する。これにより、電極端子１２Ｂと配線１６Ｂとの間に接合面１１Ｂが形成される。配線基板２０と配線１６Ｂとの間に接合面１３Ｂが形成される。接続工程において、接合面１１Ｂは接合面１３Ｂと略平行である。略平行とは、接合面１１Ｂと接合面１３Ｂとのなす角度が±５度以下であることを意味する。通常、ワイヤボンディングでは、２つの接合面１１Ｂ，１３Ｂが互いに平行になる。 Further, as shown in FIG. 3B, the electrode terminal 12B as the first adherend and the wiring board 20 as the second adherend are connected by the wiring 16B. Thereby, the joint surface 11B is formed between the electrode terminal 12B and the wiring 16B. A bonding surface 13B is formed between the wiring board 20 and the wiring 16B. In the connecting step, the bonding surface 11B is substantially parallel to the bonding surface 13B. “Substantially parallel” means that the angle formed between the joint surface 11B and the joint surface 13B is ± 5 degrees or less. Normally, in wire bonding, the two bonding surfaces 11B and 13B are parallel to each other.
　配線１６Ｂは、例えばワイヤボンディングにより電極端子１２Ｂ及び配線基板２０に接続される。ワイヤボンディングを行う際に、電極端子１２Ｂ及び配線基板２０は、治具６０によって保持される。電極端子１２Ｂの第２部分１９Ｂは、治具６０に形成された孔６２Ｂ内に挿入される。配線１６Ｂを電極端子１２Ｂ上に載せて圧力及び超音波を印加することによって、配線１６Ｂが電極端子１２Ｂに接合される。同様に、配線１６Ｂを配線基板２０上に載せて圧力及び超音波を印加することによって、配線１６Ｂが配線基板２０に接合される。 The wiring 16B is connected to the electrode terminal 12B and the wiring board 20 by wire bonding, for example. When performing wire bonding, the electrode terminal 12 </ b> B and the wiring substrate 20 are held by the jig 60. The second portion 19B of the electrode terminal 12B is inserted into a hole 62B formed in the jig 60. The wiring 16B is bonded to the electrode terminal 12B by placing the wiring 16B on the electrode terminal 12B and applying pressure and ultrasonic waves. Similarly, the wiring 16B is bonded to the wiring board 20 by placing the wiring 16B on the wiring board 20 and applying pressure and ultrasonic waves.
（移動工程）
　次に、図４に示されるように、電極端子１２Ａ及び半導体チップ１４Ａの少なくとも１つを移動することによって、電極端子１２Ａを半導体チップ１４Ａに対して相対的に移動する。例えば、電極端子１２Ａを第１位置から第２位置まで移動する。本実施形態では、電極端子１２Ａと配線１６Ａとの接合面１１Ａを含む第１平面ＰＡ１が、半導体チップ１４Ａと配線１６Ａとの接合面１３Ａを含む第２平面ＰＡ２に対向配置されるように、電極端子１２Ａ及び半導体チップ１４Ａの少なくとも１つを移動する。 (Transfer process)
Next, as shown in FIG. 4, the electrode terminal 12A is moved relative to the semiconductor chip 14A by moving at least one of the electrode terminal 12A and the semiconductor chip 14A. For example, the electrode terminal 12A is moved from the first position to the second position. In the present embodiment, the electrodes are arranged such that the first plane PA1 including the bonding surface 11A between the electrode terminal 12A and the wiring 16A is opposed to the second plane PA2 including the bonding surface 13A between the semiconductor chip 14A and the wiring 16A. At least one of the terminal 12A and the semiconductor chip 14A is moved.
　また、電極端子１２Ｂ及び配線基板２０の少なくとも１つを移動することによって、電極端子１２Ｂを配線基板２０に対して相対的に移動する。例えば、電極端子１２Ｂを第１位置から第２位置まで移動する。本実施形態では、電極端子１２Ｂと配線１６Ｂとの接合面１１Ｂを含む第１平面ＰＢ１が、配線基板２０と配線１６Ｂとの接合面１３Ｂを含む第２平面ＰＢ２に対向配置されるように、電極端子１２Ｂ及び配線基板２０の少なくとも１つを移動する。 Also, the electrode terminal 12B is moved relative to the wiring board 20 by moving at least one of the electrode terminal 12B and the wiring board 20. For example, the electrode terminal 12B is moved from the first position to the second position. In the present embodiment, the first plane PB1 including the bonding surface 11B between the electrode terminal 12B and the wiring 16B is disposed to face the second plane PB2 including the bonding surface 13B between the wiring board 20 and the wiring 16B. At least one of the terminal 12B and the wiring board 20 is moved.
（固定工程）
　次に、図２に示されるように、半導体チップ１４Ａに対する電極端子１２Ａの相対的な位置を固定する。配線基板２０に対する電極端子１２Ｂの相対的な位置を固定する。本実施形態では、電極端子１２Ａ，１２Ｂを熱硬化性樹脂部５０に固定する。配線１６Ａ，１６Ｂも熱硬化性樹脂部５０に固定され得る。未硬化の熱硬化性樹脂材料をケース３０内に流し込んで加熱することによって、熱硬化性樹脂部５０を形成することができる。 (Fixing process)
Next, as shown in FIG. 2, the relative position of the electrode terminal 12A with respect to the semiconductor chip 14A is fixed. The relative position of the electrode terminal 12B with respect to the wiring board 20 is fixed. In the present embodiment, the electrode terminals 12 </ b> A and 12 </ b> B are fixed to the thermosetting resin portion 50. The wirings 16 </ b> A and 16 </ b> B can also be fixed to the thermosetting resin part 50. The thermosetting resin portion 50 can be formed by pouring an uncured thermosetting resin material into the case 30 and heating.
　固定工程の前に、必要に応じて、接着層４４を介して配線基板２０をヒートシンク３２に接着する。 Before the fixing step, the wiring board 20 is bonded to the heat sink 32 through the adhesive layer 44 as necessary.
　本実施形態では、接続工程後に半導体チップ１４Ａに対する電極端子１２Ａの相対的な位置を任意に変えることができる。接続工程後に配線基板２０に対する電極端子１２Ｂの相対的な位置を任意に変えることができる。そのため、半導体装置１０の設計自由度が高くなる。 In this embodiment, the relative position of the electrode terminal 12A with respect to the semiconductor chip 14A can be arbitrarily changed after the connecting step. The relative position of the electrode terminal 12B with respect to the wiring board 20 can be arbitrarily changed after the connecting step. Therefore, the degree of freedom in designing the semiconductor device 10 is increased.
　接合面１１Ａを含む第１平面ＰＡ１が接合面１３Ａを含む第２平面ＰＡ２に対向配置されるように、電極端子１２Ａ及び半導体チップ１４Ａの少なくとも１つを移動すると、接合面１１Ａ，１３Ａの法線方向から見て、半導体装置１０を小型化することができる。接合面１１Ｂを含む第１平面ＰＢ１が接合面１３Ｂを含む第２平面ＰＢ２に対向配置されるように、電極端子１２Ｂ及び配線基板２０の少なくとも１つを移動すると、接合面１１Ｂ，１３Ｂの法線方向から見て、半導体装置１０を小型化することができる。 When at least one of the electrode terminal 12A and the semiconductor chip 14A is moved so that the first plane PA1 including the bonding surface 11A is opposed to the second plane PA2 including the bonding surface 13A, the normal lines of the bonding surfaces 11A and 13A are moved. The semiconductor device 10 can be reduced in size when viewed from the direction. When at least one of the electrode terminal 12B and the wiring board 20 is moved so that the first plane PB1 including the bonding surface 11B is opposed to the second plane PB2 including the bonding surface 13B, the normal lines of the bonding surfaces 11B and 13B are moved. The semiconductor device 10 can be reduced in size when viewed from the direction.
　熱硬化性樹脂部５０が電極端子１２Ａ，１２Ｂを固定すると、ゲル等に比べて半導体装置１０の耐熱性を向上させることができる。半導体チップ１４Ａ，１４Ｂの材料がワイドバンドギャップ半導体を含む場合、半導体装置１０に大電流が流れるので、半導体装置１０が高温になる傾向がある。そのような場合であっても、半導体装置１０の信頼性を向上させることができる。 When the thermosetting resin portion 50 fixes the electrode terminals 12A and 12B, the heat resistance of the semiconductor device 10 can be improved compared to gel or the like. When the material of the semiconductor chips 14A and 14B includes a wide band gap semiconductor, a large current flows through the semiconductor device 10, and thus the semiconductor device 10 tends to become high temperature. Even in such a case, the reliability of the semiconductor device 10 can be improved.
（第２実施形態）
　図５は、第２実施形態に係る半導体装置の製造方法により製造される半導体装置を模式的に示す断面図である。図５に示される半導体装置１１０は、電極端子１２Ａ，１２Ｂに代えて電極端子１１２Ａ，１１２Ｂをそれぞれ備えること以外は、半導体装置１０と同じ構成を備える。電極端子１１２Ａ，１１２Ｂは、例えば折り曲げられていない金属板である。 (Second Embodiment)
FIG. 5 is a cross-sectional view schematically showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment. The semiconductor device 110 shown in FIG. 5 has the same configuration as the semiconductor device 10 except that the electrode terminals 112A and 112B are provided instead of the electrode terminals 12A and 12B, respectively. The electrode terminals 112A and 112B are metal plates that are not bent, for example.
　電極端子１１２Ａは、電極端子１１２Ａと配線１６Ａとの接合面１１Ａを含む第１平面ＰＡ１が、半導体チップ１４Ａと配線１６Ａとの接合面１３Ａを含む第２平面ＰＡ２と略直交するように、配置される。略直交とは、第１平面ＰＡ１と第２平面ＰＡ２とのなす角度が９０±５度以下であることを意味する。 The electrode terminal 112A is arranged so that the first plane PA1 including the bonding surface 11A between the electrode terminal 112A and the wiring 16A is substantially orthogonal to the second plane PA2 including the bonding surface 13A between the semiconductor chip 14A and the wiring 16A. The The term “substantially orthogonal” means that the angle formed by the first plane PA1 and the second plane PA2 is 90 ± 5 degrees or less.
　電極端子１１２Ｂは、電極端子１１２Ｂと配線１６Ｂとの接合面１１Ｂを含む第１平面ＰＢ１が、配線基板２０と配線１６Ｂとの接合面１３Ｂを含む第２平面ＰＢ２と略直交するように、配置される。略直交とは、第１平面ＰＢ１と第２平面ＰＢ２とのなす角度が９０±５度以下であることを意味する。 The electrode terminal 112B is disposed so that the first plane PB1 including the bonding surface 11B between the electrode terminal 112B and the wiring 16B is substantially orthogonal to the second plane PB2 including the bonding surface 13B between the wiring board 20 and the wiring 16B. The The term “substantially orthogonal” means that the angle formed by the first plane PB1 and the second plane PB2 is 90 ± 5 degrees or less.
　図６及び図７は、第２実施形態に係る半導体装置の製造方法の一工程を模式的に示す断面図である。半導体装置１１０は、例えば以下のように製造される。 6 and 7 are cross-sectional views schematically showing one step of the method of manufacturing a semiconductor device according to the second embodiment. The semiconductor device 110 is manufactured as follows, for example.
（接続工程）
　まず、図６（ａ）に示されるように、第１被着体としての電極端子１１２Ａと第２被着体としての半導体チップ１４Ａとの間を配線１６Ａにより接続する。図６（ｂ）に示されるように、第１被着体としての電極端子１１２Ｂと第２被着体としての配線基板２０との間を配線１６Ｂにより接続する。本実施形態の接続工程は、電極端子１２Ａ，１２Ｂに代えて電極端子１１２Ａ，１１２Ｂをそれぞれ用いたこと以外は、第１実施形態の接続工程と同様に実施される。電極端子１１２Ａ，１１２Ｂは、例えば折り曲げられていない金属板である。そのため、治具６０には、孔６２Ａ，６２Ｂを形成する必要がない。 (Connection process)
First, as shown in FIG. 6A, the electrode terminal 112A as the first adherend and the semiconductor chip 14A as the second adherend are connected by the wiring 16A. As shown in FIG. 6B, the electrode terminal 112B as the first adherend and the wiring board 20 as the second adherend are connected by the wiring 16B. The connection process of the present embodiment is performed in the same manner as the connection process of the first embodiment except that the electrode terminals 112A and 112B are used instead of the electrode terminals 12A and 12B, respectively. The electrode terminals 112A and 112B are metal plates that are not bent, for example. Therefore, it is not necessary to form the holes 62A and 62B in the jig 60.
（移動工程）
　次に、図７に示されるように、電極端子１１２Ａ及び半導体チップ１４Ａの少なくとも１つを移動することによって、電極端子１１２Ａを半導体チップ１４Ａに対して相対的に移動する。本実施形態では、電極端子１１２Ａと配線１６Ａとの接合面１１Ａを含む第１平面ＰＡ１が、半導体チップ１４Ａと配線１６Ａとの接合面１３Ａを含む第２平面ＰＡ２と略直交するように、電極端子１１２Ａ及び半導体チップ１４Ａの少なくとも１つを移動する。略直交とは、第１平面ＰＡ１と第２平面ＰＡ２とのなす角度が９０±５度以下であることを意味する。 (Transfer process)
Next, as shown in FIG. 7, the electrode terminal 112A is moved relative to the semiconductor chip 14A by moving at least one of the electrode terminal 112A and the semiconductor chip 14A. In the present embodiment, the electrode terminals are arranged such that the first plane PA1 including the bonding surface 11A between the electrode terminal 112A and the wiring 16A is substantially orthogonal to the second plane PA2 including the bonding surface 13A between the semiconductor chip 14A and the wiring 16A. At least one of 112A and semiconductor chip 14A is moved. The term “substantially orthogonal” means that the angle formed by the first plane PA1 and the second plane PA2 is 90 ± 5 degrees or less.
　また、電極端子１１２Ｂ及び配線基板２０の少なくとも１つを移動することによって、電極端子１１２Ｂを配線基板２０に対して相対的に移動する。本実施形態では、電極端子１１２Ｂと配線１６Ｂとの接合面１１Ｂを含む第１平面ＰＢ１が、配線基板２０と配線１６Ｂとの接合面１３Ｂを含む第２平面ＰＢ２と略直交するように、電極端子１１２Ｂ及び配線基板２０の少なくとも１つを移動する。略直交とは、第１平面ＰＢ１と第２平面ＰＢ２とのなす角度が９０±５度以下であることを意味する。 Also, the electrode terminal 112B is moved relative to the wiring board 20 by moving at least one of the electrode terminal 112B and the wiring board 20. In the present embodiment, the electrode terminal 112B and the wiring 16B are connected so that the first plane PB1 including the bonding surface 11B is substantially orthogonal to the second plane PB2 including the bonding surface 13B of the wiring board 20 and the wiring 16B. At least one of 112B and wiring board 20 is moved. The term “substantially orthogonal” means that the angle formed by the first plane PB1 and the second plane PB2 is 90 ± 5 degrees or less.
（固定工程）
　次に、図５に示されるように、半導体チップ１４Ａに対する電極端子１１２Ａの相対的な位置を固定する。配線基板２０に対する電極端子１１２Ｂの相対的な位置を固定する。本実施形態では、熱硬化性樹脂部５０が電極端子１１２Ａ，１１２Ｂを固定する。 (Fixing process)
Next, as shown in FIG. 5, the relative position of the electrode terminal 112A with respect to the semiconductor chip 14A is fixed. The relative position of the electrode terminal 112B with respect to the wiring board 20 is fixed. In the present embodiment, the thermosetting resin portion 50 fixes the electrode terminals 112A and 112B.
　本実施形態では、第１実施形態と同様の作用効果が得られる。さらに、折り曲げられていない金属板を電極端子１１２Ａ，１１２Ｂとして用いても、電極端子１１２Ａ，１１２Ｂを接合面１１Ａ，１１Ｂに沿う方向に突出させることができる。 In this embodiment, the same effect as that of the first embodiment can be obtained. Furthermore, even if a metal plate that is not bent is used as the electrode terminals 112A and 112B, the electrode terminals 112A and 112B can be projected in a direction along the bonding surfaces 11A and 11B.
（第３実施形態）
　図８は、第３実施形態に係る半導体装置の製造方法により製造される半導体装置を模式的に示す斜視図である。図８に示される半導体装置２１０は、電極端子１２Ａ，１２Ｂに代えて電極端子２１２Ａ，２１２Ｂ（第１被着体）をそれぞれ備え、熱硬化性樹脂部５０に代えて絶縁材２５０を備えること以外は、半導体装置１０と同じ構成を備える。絶縁材２５０は、例えばシリコーンゲル等のゲルである。電極端子２１２Ａ，２１２Ｂは、ケース３０に固定される。 (Third embodiment)
FIG. 8 is a perspective view schematically showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the third embodiment. The semiconductor device 210 shown in FIG. 8 includes electrode terminals 212A and 212B (first adherend) instead of the electrode terminals 12A and 12B, respectively, and includes an insulating material 250 instead of the thermosetting resin portion 50. Has the same configuration as the semiconductor device 10. The insulating material 250 is a gel such as a silicone gel. The electrode terminals 212A and 212B are fixed to the case 30.
　電極端子２１２Ａは、ケース３０に固定される第１部分２１９Ａと、第１部分２１９Ａに接続され、ケース３０から外側に突出する第２部分２１８Ａとを備え得る。第１部分２１９Ａには配線１６Ａが接続される。第１部分２１９Ａは、例えば、ケース３０の一方の開口を横切る金属板である。第２部分２１８Ａは、例えば、第１部分２１９Ａの縁に接続され、第１部分２１９Ａに直交する金属板である。 The electrode terminal 212 </ b> A may include a first portion 219 </ b> A fixed to the case 30 and a second portion 218 </ b> A connected to the first portion 219 </ b> A and protruding outward from the case 30. A wiring 16A is connected to the first portion 219A. The first portion 219A is, for example, a metal plate that crosses one opening of the case 30. The second portion 218A is, for example, a metal plate that is connected to the edge of the first portion 219A and is orthogonal to the first portion 219A.
　電極端子２１２Ｂは、ケース３０に固定される第１部分２１９Ｂと、第１部分２１９Ｂに接続され、ケース３０から外側に突出する第２部分２１８Ｂとを備え得る。第１部分２１９Ｂには配線１６Ｂが接続される。第１部分２１９Ｂは、例えば、ケース３０の一方の開口を横切る金属板である。第２部分２１８Ｂは、例えば、第１部分２１９Ｂの縁に接続され、第１部分２１９Ｂに直交する金属板である。 The electrode terminal 212B may include a first portion 219B fixed to the case 30 and a second portion 218B connected to the first portion 219B and protruding outward from the case 30. A wiring 16B is connected to the first portion 219B. The first portion 219B is, for example, a metal plate that crosses one opening of the case 30. The second portion 218B is, for example, a metal plate that is connected to the edge of the first portion 219B and is orthogonal to the first portion 219B.
　半導体装置２１０は、接続工程（図３参照）、移動工程（図４参照）及び固定工程を経ることによって製造され得る。接続工程及び移動工程は、第１実施形態と同様に実施される。固定工程では、図８に示されるように、電極端子２１２Ａ，２１２Ｂを、ケース３０に固定する。電極端子２１２Ａの第１部分２１９Ａの両端がケース３０に固定され得る。電極端子２１２Ｂの第１部分２１９Ｂの両端がケース３０に固定され得る。その後、必要に応じて絶縁材２５０がケース３０内に充填される。 The semiconductor device 210 can be manufactured through a connection process (see FIG. 3), a movement process (see FIG. 4), and a fixing process. The connecting process and the moving process are performed in the same manner as in the first embodiment. In the fixing process, as shown in FIG. 8, the electrode terminals 212 </ b> A and 212 </ b> B are fixed to the case 30. Both ends of the first portion 219A of the electrode terminal 212A can be fixed to the case 30. Both ends of the first portion 219B of the electrode terminal 212B can be fixed to the case 30. Thereafter, the insulating material 250 is filled in the case 30 as necessary.
　本実施形態では、第１実施形態と同様の作用効果が得られる。さらに、高い位置精度で電極端子２１２Ａ，２１２Ｂをケース３０に固定することができる。 In this embodiment, the same effect as that of the first embodiment can be obtained. Furthermore, the electrode terminals 212A and 212B can be fixed to the case 30 with high positional accuracy.
（第４実施形態）
　図９は、第４実施形態に係る半導体装置の製造方法により製造される半導体装置を模式的に示す斜視図である。図９に示される半導体装置３１０は、熱硬化性樹脂部５０に代えて絶縁材２５０を備え、支持部材３１９Ａ，３１９Ｂを更に備えること以外は、半導体装置１０と同じ構成を備える。 (Fourth embodiment)
FIG. 9 is a perspective view schematically showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the fourth embodiment. A semiconductor device 310 shown in FIG. 9 has the same configuration as the semiconductor device 10 except that it includes an insulating material 250 instead of the thermosetting resin portion 50 and further includes support members 319A and 319B.
　電極端子１２Ａ，１２Ｂは、ケース３０に取り付けられた支持部材３１９Ａ，３１９Ｂに固定される。電極端子１２Ａ，１２Ｂはケース３０に固定されてもよい。支持部材３１９Ａ，３１９Ｂは、例えば、ケース３０の一方の開口を横切る絶縁板である。支持部材３１９Ａには、電極端子１２Ａを嵌め込むための開口３１８Ａが形成されている。支持部材３１９Ｂには、電極端子１２Ｂを嵌め込むための開口３１８Ｂが形成されている。 The electrode terminals 12A and 12B are fixed to support members 319A and 319B attached to the case 30. The electrode terminals 12A and 12B may be fixed to the case 30. The support members 319A and 319B are, for example, insulating plates that cross one opening of the case 30. An opening 318A for fitting the electrode terminal 12A is formed in the support member 319A. An opening 318B for fitting the electrode terminal 12B is formed in the support member 319B.
　半導体装置３１０は、接続工程（図３参照）、移動工程（図４参照）及び固定工程を経ることによって製造され得る。接続工程及び移動工程は、第１実施形態と同様に実施される。固定工程では、図９に示されるように、電極端子１２Ａ，１２Ｂを、ケース３０に取り付けられた支持部材３１９Ａ，３１９Ｂに固定する。その後、必要に応じて絶縁材２５０がケース３０内に充填される。 The semiconductor device 310 can be manufactured through a connection process (see FIG. 3), a movement process (see FIG. 4), and a fixing process. The connecting process and the moving process are performed in the same manner as in the first embodiment. In the fixing step, as shown in FIG. 9, the electrode terminals 12 </ b> A and 12 </ b> B are fixed to support members 319 </ b> A and 319 </ b> B attached to the case 30. Thereafter, the insulating material 250 is filled in the case 30 as necessary.
　本実施形態では、第１実施形態と同様の作用効果が得られる。さらに、高い位置精度で電極端子１２Ａ，１２Ｂを支持部材３１９Ａ，３１９Ｂに固定することができる。また、絶縁性の支持部材３１９Ａ，３１９Ｂを用いることにより、電極端子１２Ａ，１２Ｂをケース３０から電気的に絶縁することができる。 In this embodiment, the same effect as that of the first embodiment can be obtained. Furthermore, the electrode terminals 12A and 12B can be fixed to the support members 319A and 319B with high positional accuracy. Moreover, the electrode terminals 12A and 12B can be electrically insulated from the case 30 by using the insulating support members 319A and 319B.
　以上、本発明の好適な実施形態について詳細に説明されたが、本発明は上記実施形態に限定されない。各実施形態の構成は任意に組み合わせ得る。例えば、半導体装置２１０，３１０は、絶縁材２５０に代えて熱硬化性樹脂部５０を備えてもよい。半導体装置２１０は、電極端子２１２Ａ，２１２Ｂに代えて電極端子１１２Ａ，１１２Ｂを備えてもよい。この場合、電極端子１１２Ａ，１１２Ｂは、ケース３０に固定される部分を有する。半導体装置３１０は、電極端子１２Ａ，１２Ｂに代えて電極端子１１２Ａ，１１２Ｂを備えてもよい。この場合、電極端子１１２Ａ，１１２Ｂは、支持部材３１９Ａ，３１９Ｂに固定される。 The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the above embodiments. The configurations of the embodiments can be arbitrarily combined. For example, the semiconductor devices 210 and 310 may include the thermosetting resin portion 50 instead of the insulating material 250. The semiconductor device 210 may include electrode terminals 112A and 112B instead of the electrode terminals 212A and 212B. In this case, the electrode terminals 112 </ b> A and 112 </ b> B have a portion fixed to the case 30. The semiconductor device 310 may include electrode terminals 112A and 112B instead of the electrode terminals 12A and 12B. In this case, the electrode terminals 112A and 112B are fixed to the support members 319A and 319B.
　第１被着体及び第２被着体のそれぞれは、電極端子、半導体チップ、又は配線基板等であってもよい。 Each of the first adherend and the second adherend may be an electrode terminal, a semiconductor chip, a wiring board, or the like.
　１０，１１０，２１０，３１０…半導体装置、１１Ａ，１３Ａ，１１Ｂ，１３Ｂ…接合面、１２Ａ，１２Ｂ，１１２Ａ，１１２Ｂ，２１２Ａ，２１２Ｂ…電極端子（第１被着体）、１４Ａ…半導体チップ（第２被着体）、１６Ａ，１６Ｂ…配線、２０…配線基板（第２被着体）、５０…熱硬化性樹脂部、３０…ケース、３１９Ａ，３１９Ｂ…支持部材、ＰＡ１，ＰＢ１…第１平面、ＰＡ２，ＰＢ２…第２平面。 10, 110, 210, 310 ... Semiconductor device, 11A, 13A, 11B, 13B ... Bonding surface, 12A, 12B, 112A, 112B, 212A, 212B ... Electrode terminal (first adherend), 14A ... Semiconductor chip (first) 2 adherends), 16A, 16B ... wiring, 20 ... wiring board (second adherend), 50 ... thermosetting resin part, 30 ... case, 319A, 319B ... support member, PA1, PB1 ... first plane , PA2, PB2 ... second plane.

Claims (7)

  1. 　第１被着体と第２被着体との間を配線により接続する接続工程と、
    　前記接続工程の後、前記第１被着体及び前記第２被着体の少なくとも１つを移動することによって、前記第１被着体を前記第２被着体に対して相対的に移動する移動工程と、
    　前記第２被着体に対する前記第１被着体の相対的な位置を固定する固定工程と、
    を含む、半導体装置の製造方法。     A connecting step of connecting the first adherend and the second adherend by wiring;
    After the connecting step, the first adherend is moved relative to the second adherend by moving at least one of the first adherend and the second adherend. Moving process;
    A fixing step of fixing a relative position of the first adherend to the second adherend;
    A method for manufacturing a semiconductor device, comprising:
  2. 　前記移動工程では、前記第１被着体と前記配線との接合面を含む第１平面が、前記第２被着体と前記配線との接合面を含む第２平面に対向配置されるように、前記第１被着体及び前記第２被着体の少なくとも１つを移動する、請求項１に記載の半導体装置の製造方法。 In the moving step, a first plane including a bonding surface between the first adherend and the wiring is disposed so as to face a second plane including a bonding surface between the second adherend and the wiring. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the first adherend and the second adherend is moved.
  3. 　前記移動工程では、前記第１被着体と前記配線との接合面を含む第１平面が、前記第２被着体と前記配線との接合面を含む第２平面と略直交するように、前記第１被着体及び前記第２被着体の少なくとも１つを移動する、請求項１に記載の半導体装置の製造方法。 In the moving step, a first plane including a bonding surface between the first adherend and the wiring is substantially orthogonal to a second plane including a bonding surface between the second adherend and the wiring. The method for manufacturing a semiconductor device according to claim 1, wherein at least one of the first adherend and the second adherend is moved.
  4. 　前記固定工程では、前記第１被着体を熱硬化性樹脂部に固定する、請求項１～３のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein, in the fixing step, the first adherend is fixed to a thermosetting resin portion.
  5. 　前記固定工程では、前記第１被着体をケースに固定する、請求項１～４のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein, in the fixing step, the first adherend is fixed to a case.
  6. 　前記固定工程では、前記第１被着体を、ケースに取り付けられた支持部材に固定する、請求項１～５のいずれか一項に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 1, wherein, in the fixing step, the first adherend is fixed to a support member attached to a case.
  7. 　前記配線が、ワイヤ又はボンディングリボンである、請求項１～６のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the wiring is a wire or a bonding ribbon.
PCT/JP2014/060528 2013-05-07 2014-04-11 Method for manufacturing semiconductor device WO2014181638A1 (en)

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Publication number Priority date Publication date Assignee Title
JPH0855881A (en) * 1994-07-07 1996-02-27 Tessera Inc Packaging structure of microelectronics device and manufacture thereof
JP2003224243A (en) * 2002-01-30 2003-08-08 Toyota Industries Corp Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3058565A1 (en) * 2016-11-08 2018-05-11 Valeo Systemes De Controle Moteur ELECTRONIC POWER MODULE, ELECTRICAL EQUIPMENT AND ELECTRICAL POWER COMPRESSOR COMPRISING SUCH AN ELECTRONIC POWER MODULE

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