JP5266371B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP5266371B2
JP5266371B2 JP2011170871A JP2011170871A JP5266371B2 JP 5266371 B2 JP5266371 B2 JP 5266371B2 JP 2011170871 A JP2011170871 A JP 2011170871A JP 2011170871 A JP2011170871 A JP 2011170871A JP 5266371 B2 JP5266371 B2 JP 5266371B2
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semiconductor chip
wire
main surface
wires
wiring board
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JP2011249838A (en
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好彦 嶋貫
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Renesas Electronics Corp
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Renesas Electronics Corp
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Description

本発明は、半導体製造技術に関し、特に、ワイヤボンディングにおける接続不良の抑制化に適用して有効な技術に関する。   The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique effective when applied to suppression of connection failure in wire bonding.

第１ボンディング点にネック部分を形成後、第１所定量の長さのワイヤを繰り出しながらキャピラリを上昇させ、第２ボンディング点に向かう方向に移動させて第１癖付け部分を形成する。キャピラリを下降させ、第２ボンディング点と反対側に向かう方向に移動させて第２癖付け部分を形成する。キャピラリを上昇させて第１癖付け部分がキャピラリ先端に位置するまでワイヤを繰り出し、その状態でキャピラリを第２ボンディング点まで移動させワイヤループを形成する技術がある（例えば、特許文献１参照）。   After forming the neck portion at the first bonding point, the capillary is raised while feeding the first predetermined length of wire, and moved in the direction toward the second bonding point to form the first brazed portion. The capillary is lowered and moved in the direction opposite to the second bonding point to form the second brazed portion. There is a technique in which the capillary is raised and the wire is fed out until the first brazing portion is located at the tip of the capillary, and in that state, the capillary is moved to the second bonding point to form a wire loop (see, for example, Patent Document 1).

第１ボンディング点にワイヤを接続する工程と、キャピラリを少し上昇させ、第１のリバース動作を行う工程と、キャピラリを上昇させ、第２のリバース動作を行う工程と、キャピラリを上昇させ、第３のリバース動作を行う工程とを行う。さらに、クランパが閉じ、キャピラリを第２ボンディング点の反対の方向に水平移動させる工程と、クランパが開き、キャピラリを第２ボンディング点の方向に水平移動させる工程と、キャピラリを第１ボンディング点の上方まで上昇させてワイヤを繰り出し、第２ボンディング点に接続する工程とを行う技術がある（例えば、特許文献２参照）。   A step of connecting a wire to the first bonding point, a step of slightly raising the capillary to perform a first reverse operation, a step of raising the capillary and performing a second reverse operation, a step of raising the capillary, The reverse operation is performed. Further, the clamper is closed and the capillary is moved horizontally in the direction opposite to the second bonding point, the clamper is opened and the capillary is moved horizontally in the direction of the second bonding point, and the capillary is moved above the first bonding point. There is a technique of performing a process of raising the wire up to a wire and feeding it to a second bonding point (see, for example, Patent Document 2).

特開２００４−８７７４７号公報（図２）JP 2004-87747 A (FIG. 2) 特開２００４−３１９９２１号公報（図１）JP 2004-319921 A (FIG. 1)

小型化の要求に応えた半導体装置の一例として、チップサイズと半導体パッケージ（配線基板）のサイズがほぼ同じであるＣＳＰ（Chip Size Package)と呼ばれる半導体装置が知られている。   As an example of a semiconductor device that meets the demand for miniaturization, a semiconductor device called a CSP (Chip Size Package) in which the chip size and the size of a semiconductor package (wiring substrate) are almost the same is known.

前記ＣＳＰは、半導体チップの端部（端辺）と配線基板の端部（端辺）との距離が約0.２〜0.３ｍｍと狭い（短い）ため、配線基板の主面に形成されたワイヤ接続するためのボンディングリード（端子）と半導体チップの端部（端辺）との距離も約0.１ｍｍと非常に狭い（短い）。そのため、ワイヤボンディング工程において、半導体チップの電極と接続する点を１ｓｔ側、配線基板の主面に形成されたボンディングリードと接続する点を２ｎｄ側とする所謂正ボンディング方式によりワイヤ接続を行うと、ワイヤがキャピラリとチップ端の間に入らないという現象が起こる。   The CSP is formed on the main surface of the wiring board because the distance between the edge (edge) of the semiconductor chip and the edge (edge) of the wiring board is as narrow (short) as about 0.2 to 0.3 mm. The distance between the bonding lead (terminal) for connecting the wire and the end portion (end side) of the semiconductor chip is also very narrow (short) of about 0.1 mm. Therefore, in the wire bonding step, when the wire connection is performed by a so-called positive bonding method in which the point connected to the electrode of the semiconductor chip is the 1st side and the point connected to the bonding lead formed on the main surface of the wiring board is the 2nd side, A phenomenon occurs in which the wire does not enter between the capillary and the tip end.

これを詳細に説明すると、図２７の比較例に示すように、１ｓｔ側から２ｎｄ側に打ち下ろしたワイヤ４にキャピラリ１８の一部が接触する。そこで、キャピラリ１８の根元から先端まで補足加工した部分（Ｌ）を長くすれば、ワイヤ４との干渉は抑制できるが、ワイヤボンディング工程では超音波を併用したネイルヘッドボンディング方式により行うため、細いＬ寸法分が長すぎると、細い部分でキャピラリ１８が撓むため、超音波がキャピラリ１８の先端に伝わり難くなる。   This will be described in detail. As shown in the comparative example of FIG. 27, a part of the capillary 18 comes into contact with the wire 4 that is downed from the 1st side to the 2nd side. Therefore, if the part (L) supplementarily processed from the base to the tip of the capillary 18 is lengthened, interference with the wire 4 can be suppressed. However, since the wire bonding process is performed by a nail head bonding method using ultrasonic waves, the thin L If the dimension is too long, the capillary 18 bends at a narrow portion, so that it is difficult to transmit ultrasonic waves to the tip of the capillary 18.

また、正ボンディングの場合、２ｎｄ側のワイヤ４を圧着する際、ワイヤ４が２ｎｄ側よりも高い位置から引き出されているために、図２７に示すようにＡ部において、キャピラリ１８の一部とワイヤ４との間で摩擦が生じ易く、キャピラリ１８の一部が磨耗し易い。   Further, in the case of positive bonding, when the wire 4 on the 2nd side is crimped, the wire 4 is drawn from a position higher than the 2nd side. Therefore, as shown in FIG. Friction is likely to occur between the wire 4 and part of the capillary 18 is easily worn.

そこで、前記特許文献１（特開２００４−８７７４７号公報）や前記特許文献２（特開２００４−３１９９２１号公報）に記載されているように、配線基板の主面に形成されたボンディングリードと接続する点を１ｓｔ（第１ボンド）側、半導体チップの電極と接続する点を２ｎｄ（第２ボンド）側とする所謂逆ボンディング方式によりワイヤ接続を行えば、ワイヤ断線不良を抑制することができる。すなわち、ワイヤは低い位置にある１ｓｔ側から高い位置にある２ｎｄ側へとほぼ同じ高さまで垂直方向に引き上げられ、その後、水平方向にキャピラリを移動させて高い位置にある２ｎｄ側に接続するため、１ｓｔ側におけるワイヤの根元が折れ曲がることはなく、その結果、ワイヤ断線不良を抑制することができる。   Therefore, as described in Patent Document 1 (Japanese Patent Laid-Open No. 2004-87747) and Patent Document 2 (Japanese Patent Laid-Open No. 2004-319921), connection with bonding leads formed on the main surface of the wiring board is possible. If wire connection is performed by a so-called reverse bonding method in which the point to be connected is the 1st (first bond) side and the point to be connected to the electrode of the semiconductor chip is the 2nd (second bond) side, wire disconnection defects can be suppressed. That is, the wire is pulled up to the same height from the 1st side at the lower position to the 2nd side at the higher position in the vertical direction, and then the capillary is moved in the horizontal direction to connect to the 2nd side at the higher position. The base of the wire on the 1st side is not bent, and as a result, wire disconnection failure can be suppressed.

しかしながら、上記したように半導体装置の小型化に伴い、配線基板の主面に形成されたボンディングリードと半導体チップの端部（端辺）との距離も約0.１ｍｍと非常に狭いため、逆ボンディング方式によりワイヤ接続を行うと、最終的にワイヤを２ｎｄ側に倒したときに、ワイヤの引き回しのマージンが足りないため、図２８の比較例の小型パッケージ３０に示すように、ワイヤ４がチップ端部に接触するという現象が起こる。   However, as described above, with the miniaturization of the semiconductor device, the distance between the bonding lead formed on the main surface of the wiring board and the end portion (end side) of the semiconductor chip is also very narrow, about 0.1 mm. When wire connection is performed by the bonding method, when the wire is finally tilted to the 2nd side, there is not enough wire routing margin. Therefore, as shown in the small package 30 of the comparative example in FIG. The phenomenon of touching the edge occurs.

言い換えると、スプールからのワイヤ送り速度とキャピラリ１８の動く速度が対応しておらず、ワイヤ４の送り速度よりもキャピラリ１８の動きの方が速いため、ワイヤ供給力が少なくなり、形成されたワイヤ４が短く安定しないことから、チップ端部にショートしてワイヤ接続不良を引き起こすという問題が発生する。特に、半導体チップ１の主面１ａの端部にテストパターンが形成されている場合があり、この場合、テストパターンとワイヤ４とがショートすることも問題となる。   In other words, the wire feed speed from the spool and the moving speed of the capillary 18 do not correspond, and the movement of the capillary 18 is faster than the feeding speed of the wire 4, so the wire supply force is reduced and the formed wire Since 4 is short and unstable, there is a problem that a short circuit occurs at the end of the chip to cause a poor wire connection. In particular, a test pattern may be formed at the end of the main surface 1a of the semiconductor chip 1. In this case, a short circuit between the test pattern and the wire 4 is also a problem.

本発明の目的は、ワイヤ接続不良の抑制化を図ることができる技術を提供することにある。   The objective of this invention is providing the technique which can aim at suppression of the wire connection defect.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

すなわち、本発明は、主面の周縁部に沿って配置された複数の端子を有する配線基板と、配線基板の主面の端子列の内側に搭載された半導体チップと、半導体チップの電極と配線基板の端子とを接続し、配線基板側の端子が第１ボンドとして接続され、半導体チップの電極が第２ボンドとして接続された複数のワイヤとを有し、前記ワイヤの一部が、前記端子におけるワイヤ接続部より前記周縁部側に配置されているものである。   That is, the present invention relates to a wiring board having a plurality of terminals arranged along the peripheral edge of the main surface, a semiconductor chip mounted inside a terminal row on the main surface of the wiring board, and electrodes and wiring of the semiconductor chip A plurality of wires connected to a terminal of the substrate, a terminal on the wiring substrate side as a first bond, and an electrode of a semiconductor chip as a second bond, and a part of the wire includes the terminal It is arrange | positioned in the said peripheral part side from the wire connection part.

また、本発明は、配線基板に半導体チップを接続した後、ワイヤの先端部を配線基板の端子に接続し、その後キャピラリを半導体チップから離れる方向に移動させてワイヤを前記端子から引き出し、さらにキャピラリを半導体チップの電極上に配置した後、前記ワイヤの一部を半導体チップの電極に接続する工程を有し、ワイヤの一部が、配線基板の端子におけるワイヤ接続部より周縁部側に配置されるようにワイヤを接続するものである。   The present invention also provides a method for connecting a semiconductor chip to a wiring board, connecting a tip portion of the wire to a terminal of the wiring board, and then moving the capillary away from the semiconductor chip to draw the wire from the terminal. Is disposed on the electrode of the semiconductor chip, and then a part of the wire is connected to the electrode of the semiconductor chip, and the part of the wire is disposed on the peripheral edge side of the wire connection part in the terminal of the wiring board. In this way, wires are connected.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

ワイヤの一部が、配線基板の端子における第１ボンドのワイヤ接続部より外側に配置されていることにより、ワイヤが外側に遠回りして引き回されるため、配線基板の端子と半導体チップの電極との接続においてワイヤ長を長くすることができる。これにより、ワイヤの引き回しのマージンが増えてキャピラリの動く速度にワイヤ送り速度が追従することが可能になり、ワイヤのループ形状の安定化を図ることができる。その結果、チップ端部とワイヤのショートを低減してワイヤ接続不良の発生を低減することができ、ワイヤ接続不良の抑制化を図ることができる。   Since a part of the wire is arranged outside the wire connection portion of the first bond in the terminal of the wiring board, the wire is routed around to the outside, so that the terminal of the wiring board and the electrode of the semiconductor chip The wire length can be increased in connection with. As a result, the wire routing margin increases and the wire feed speed can follow the capillary moving speed, so that the wire loop shape can be stabilized. As a result, it is possible to reduce the occurrence of wire connection failure by reducing short-circuit between the chip end and the wire, and to suppress the wire connection failure.

本発明の実施の形態１の半導体装置の構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. 図１に示す半導体装置の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device shown in FIG. 図２に示すＡ部の構造を示す拡大部分断面図である。FIG. 3 is an enlarged partial cross-sectional view showing a structure of a portion A shown in FIG. 2. 図３に示すワイヤ接合部の構造の一例を示す拡大部分断面図である。FIG. 4 is an enlarged partial cross-sectional view illustrating an example of a structure of a wire joint portion illustrated in FIG. 3. 図４に示すワイヤリング時のキャピラリの移動軌跡の一例を示す断面図である。It is sectional drawing which shows an example of the movement locus | trajectory of the capillary at the time of wiring shown in FIG. 図４に示すワイヤリング時のキャピラリの移動軌跡の一例を示す断面図である。It is sectional drawing which shows an example of the movement locus | trajectory of the capillary at the time of wiring shown in FIG. 図４に示すワイヤリング時のキャピラリの移動軌跡の一例を示す断面図である。It is sectional drawing which shows an example of the movement locus | trajectory of the capillary at the time of wiring shown in FIG. 図４に示すワイヤリング時のキャピラリの移動軌跡の一例を示す断面図である。It is sectional drawing which shows an example of the movement locus | trajectory of the capillary at the time of wiring shown in FIG. 図１に示す半導体装置に組み込まれる配線基板の主面側の配線パターンの一例を示す平面図である。FIG. 2 is a plan view showing an example of a wiring pattern on the main surface side of a wiring board incorporated in the semiconductor device shown in FIG. 1. 図９に示す配線基板の裏面側の配線パターンの一例を示す裏面図である。FIG. 10 is a back view showing an example of a wiring pattern on the back side of the wiring board shown in FIG. 9. 図９に示す配線基板の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the wiring board shown in FIG. 図１１に示すＡ部の構造を示す拡大部分断面図である。It is an expanded partial sectional view which shows the structure of the A section shown in FIG. 図１に示す半導体装置の組み立てにおける樹脂モールドまでの組み立ての一例を示す製造プロセスフロー図である。It is a manufacturing process flowchart which shows an example of the assembly to the resin mold in the assembly of the semiconductor device shown in FIG. 図１に示す半導体装置の組み立てにおける樹脂モールド後の組み立ての一例を示す製造プロセスフロー図である。FIG. 2 is a manufacturing process flow diagram illustrating an example of assembly after resin molding in the assembly of the semiconductor device illustrated in FIG. 1. 図１に示す半導体装置の組み立てにおける樹脂モールド後の組み立ての変形例を示す製造プロセスフロー図である。FIG. 8 is a manufacturing process flow diagram illustrating a modification example of assembly after resin molding in the assembly of the semiconductor device illustrated in FIG. 1. 本発明の実施の形態１の変形例の配線基板の主面側の配線パターンを示す平面図である。It is a top view which shows the wiring pattern by the side of the main surface of the wiring board of the modification of Embodiment 1 of this invention. 図１６に示す配線基板の裏面側の配線パターンを示す裏面図である。It is a back view which shows the wiring pattern of the back surface side of the wiring board shown in FIG. 図１６に示す配線基板の構造を示す断面図である。It is sectional drawing which shows the structure of the wiring board shown in FIG. 図１８に示すＡ部の構造を示す拡大部分断面図である。It is an expanded partial sectional view which shows the structure of the A section shown in FIG. 本発明の実施の形態１の他の変形例の配線基板の主面側の配線パターンを示す平面図である。It is a top view which shows the wiring pattern by the side of the main surface of the wiring board of the other modification of Embodiment 1 of this invention. 図２０に示す配線基板の構造を示す断面図である。It is sectional drawing which shows the structure of the wiring board shown in FIG. 図２１に示すＡ部の構造を示す拡大部分断面図である。It is an expanded partial sectional view which shows the structure of the A section shown in FIG. 本発明の実施の形態２の半導体装置の構造の一例を封止体を透過して示す平面図である。It is a top view which permeate | transmits and shows an example of the structure of the semiconductor device of Embodiment 2 of this invention. 図２３に示す半導体装置の構造の一例を示す断面図である。FIG. 24 is a cross-sectional view illustrating an example of the structure of the semiconductor device illustrated in FIG. 23. 図２４に示すＡ部の構造を示す拡大部分断面図である。FIG. 25 is an enlarged partial sectional view showing a structure of a portion A shown in FIG. 24. 図２４に示すＢ部の構造を示す拡大部分断面図である。FIG. 25 is an enlarged partial sectional view showing a structure of a B part shown in FIG. 24. 比較例のワイヤボンディング時のキャピラリ押し付け状態の一例を示す拡大部分断面図である。It is an expanded partial sectional view which shows an example of the capillary pressing state at the time of the wire bonding of a comparative example. 比較例のワイヤボンディング後の接続不良の状態を示す断面図である。It is sectional drawing which shows the state of the connection failure after the wire bonding of a comparative example.

以下の実施の形態では特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。   In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

さらに、以下の実施の形態では便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明などの関係にある。   Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

また、以下の実施の形態において、要素の数など（個数、数値、量、範囲などを含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合などを除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良いものとする。   Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

（実施の形態１）
図１は本発明の実施の形態１の半導体装置の構造の一例を封止体を透過して示す平面図、図２は図１に示す半導体装置の構造の一例を示す断面図、図３は図２に示すＡ部の構造を示す拡大部分断面図、図４は図３に示すワイヤ接合部の構造の一例を示す拡大部分断面図、図５〜図８は図４に示すワイヤリング時のキャピラリの移動軌跡の一例を示す断面図である。また、図９は図１に示す半導体装置に組み込まれる配線基板の主面側の配線パターンの一例を示す平面図、図１０は図９に示す配線基板の裏面側の配線パターンの一例を示す裏面図、図１１は図９に示す配線基板の構造の一例を示す断面図、図１２は図１１に示すＡ部の構造を示す拡大部分断面図である。さらに、図１３は図１に示す半導体装置の組み立てにおける樹脂モールドまでの組み立ての一例を示す製造プロセスフロー図、図１４は図１に示す半導体装置の組み立てにおける樹脂モールド後の組み立ての一例を示す製造プロセスフロー図、図１５は図１に示す半導体装置の組み立てにおける樹脂モールド後の組み立ての変形例を示す製造プロセスフロー図である。 (Embodiment 1)
1 is a plan view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention through a sealing body, FIG. 2 is a cross-sectional view showing an example of the structure of the semiconductor device shown in FIG. 1, and FIG. 2 is an enlarged partial sectional view showing the structure of part A shown in FIG. 2, FIG. 4 is an enlarged partial sectional view showing an example of the structure of the wire joint part shown in FIG. 3, and FIGS. 5 to 8 are capillaries during wiring shown in FIG. It is sectional drawing which shows an example of this movement locus | trajectory. 9 is a plan view showing an example of a wiring pattern on the main surface side of the wiring board incorporated in the semiconductor device shown in FIG. 1, and FIG. 10 is a back surface showing an example of the wiring pattern on the back side of the wiring board shown in FIG. 11 is a cross-sectional view showing an example of the structure of the wiring board shown in FIG. 9, and FIG. 12 is an enlarged partial cross-sectional view showing the structure of part A shown in FIG. Further, FIG. 13 is a manufacturing process flow chart showing an example of assembly up to the resin mold in the assembly of the semiconductor device shown in FIG. 1, and FIG. 14 is a manufacturing process showing an example of the assembly after the resin mold in the assembly of the semiconductor device shown in FIG. FIG. 15 is a process flow diagram showing a modification of assembly after resin molding in the assembly of the semiconductor device shown in FIG.

また、図１６は本発明の実施の形態１の変形例の配線基板の主面側の配線パターンを示す平面図、図１７は図１６に示す配線基板の裏面側の配線パターンを示す裏面図、図１８は図１６に示す配線基板の構造を示す断面図、図１９は図１８に示すＡ部の構造を示す拡大部分断面図である。さらに、図２０は本発明の実施の形態１の他の変形例の配線基板の主面側の配線パターンを示す平面図、図２１は図２０に示す配線基板の構造を示す断面図、図２２は図２１に示すＡ部の構造を示す拡大部分断面図である。   16 is a plan view showing a wiring pattern on the main surface side of the wiring board according to the modification of the first embodiment of the present invention, and FIG. 17 is a back view showing the wiring pattern on the back surface side of the wiring board shown in FIG. 18 is a cross-sectional view showing the structure of the wiring board shown in FIG. 16, and FIG. 19 is an enlarged partial cross-sectional view showing the structure of part A shown in FIG. 20 is a plan view showing a wiring pattern on the main surface side of the wiring board of another modification of the first embodiment of the present invention, FIG. 21 is a cross-sectional view showing the structure of the wiring board shown in FIG. FIG. 22 is an enlarged partial cross-sectional view showing the structure of part A shown in FIG. 21.

本実施の形態１の半導体装置は、配線基板上に半導体チップ１が搭載された樹脂封止型の小型の半導体パッケージであり、本実施の形態１ではその一例として、図１〜図３に示すようなＣＳＰ７を取り上げて説明する。   The semiconductor device according to the first embodiment is a resin-sealed small semiconductor package in which a semiconductor chip 1 is mounted on a wiring board. In the first embodiment, an example thereof is shown in FIGS. Such a CSP 7 will be described.

なお、ＣＳＰ７は、配線基板の裏面３ｂに複数の外部端子である半田バンプ８が格子状に配置されて取り付けられており、したがって、ＣＳＰ７はＢＧＡ（Ball Grid Array)型の半導体パッケージである。   Note that the CSP 7 has a plurality of external terminals of solder bumps 8 arranged in a grid on the back surface 3b of the wiring board, and therefore the CSP 7 is a BGA (Ball Grid Array) type semiconductor package.

図１〜図３を用いてＣＳＰ７の構造について説明すると、主面３ａと、主面３ａに対向する裏面３ｂと、主面３ａの外周部に並んで配置された複数のボンディングリード（端子）３ｈとを有する配線基板であるパッケージ基板３と、パッケージ基板３の主面３ａのボンディングリード列の内側（複数のボンディングリード３ｈの内側の領域）に搭載され、かつ集積回路を有する半導体チップ１とを備えている。また、半導体チップ１の電極であるパッド１ｃとパッケージ基板３のボンディングリード３ｈとを電気的に接続する導電性のワイヤ４と、パッケージ基板３の主面３ａと半導体チップ１との間に配置された（予め半導体チップ１の裏面側に貼り付けられた）ダイボンド材であるダイボンド用フィルム２と、パッケージ基板３の裏面３ｂの複数のランド３ｄに設けられた複数の外部端子（外部接続用端子）である半田バンプ８とを備えている。さらに、半導体チップ１及び複数のワイヤ４を樹脂封止する封止体６を備えており、パッケージ基板３の主面３ａの保護膜であるソルダレジスト膜３ｆ上に、半導体チップ１がダイボンド用フィルム２を介して固定されている。   The structure of the CSP 7 will be described with reference to FIGS. 1 to 3. The main surface 3a, the back surface 3b opposite to the main surface 3a, and a plurality of bonding leads (terminals) 3h arranged side by side on the outer periphery of the main surface 3a. And a semiconductor chip 1 mounted on the inner side of the bonding lead row of the main surface 3a of the package substrate 3 (the region inside the plurality of bonding leads 3h) and having an integrated circuit. I have. In addition, the conductive wire 4 that electrically connects the pad 1 c that is an electrode of the semiconductor chip 1 and the bonding lead 3 h of the package substrate 3, and the main surface 3 a of the package substrate 3 and the semiconductor chip 1 are disposed. A die-bonding film 2 that is a die-bonding material (preliminarily attached to the back side of the semiconductor chip 1) and a plurality of external terminals (external connection terminals) provided on a plurality of lands 3d on the back surface 3b of the package substrate 3 The solder bumps 8 are provided. Further, the semiconductor chip 1 and a sealing body 6 for sealing the plurality of wires 4 are provided. The semiconductor chip 1 is a die-bonding film on the solder resist film 3f that is a protective film of the main surface 3a of the package substrate 3. 2 is fixed.

なお、ＣＳＰ７は、小型の半導体パッケージであるが、半導体チップ１の大きさとパッケージ基板３の大きさがほぼ同じであり、パッケージ基板３の方が僅かに大きい程度である。例えば、図４に示すように、半導体チップ１の端部からパッケージ基板３の端部までの距離（Ｔ１）は、約0.２〜0.３ｍｍと非常に狭い（短い）。   The CSP 7 is a small semiconductor package, but the size of the semiconductor chip 1 and the size of the package substrate 3 are substantially the same, and the package substrate 3 is slightly larger. For example, as shown in FIG. 4, the distance (T1) from the end of the semiconductor chip 1 to the end of the package substrate 3 is very narrow (short) of about 0.2 to 0.3 mm.

したがって、パッケージ基板３の主面３ａの外周部（周縁部）に形成されたワイヤ接続するためのボンディングリード３ｈと半導体チップ１の端部（端辺）との距離（Ｔ２）も約0.１ｍｍ程度と非常に狭い（短い）。   Therefore, the distance (T2) between the bonding lead 3h formed on the outer peripheral portion (peripheral portion) of the main surface 3a of the package substrate 3 and the end portion (end side) of the semiconductor chip 1 is also about 0.1 mm. The degree and very narrow (short).

そこで、ＣＳＰ７では、図１及び図３に示すように、パッケージ基板３においてチップ外側の領域で、かつ基板の外周部に複数のボンディングリード３ｈが並んで配置されており、半導体チップ１の主面１ａに設けられた電極であるパッド１ｃと、これに対応するパッケージ基板３のボンディングリード３ｈとが金線等の導電性のワイヤ４によって電気的に接続されている。   Therefore, in the CSP 7, as shown in FIGS. 1 and 3, a plurality of bonding leads 3 h are arranged in a region outside the chip in the package substrate 3 and on the outer periphery of the substrate, and the main surface of the semiconductor chip 1. A pad 1c, which is an electrode provided on 1a, and a corresponding bonding lead 3h of the package substrate 3 are electrically connected by a conductive wire 4 such as a gold wire.

その際、本実施の形態１のＣＳＰ７では、図１に示すように、複数のワイヤ４それぞれが、半導体チップ１のパッド１ｃと、これに対応するパッケージ基板３のボンディングリード３ｈとを電気的に接続するとともに、基板側のボンディングリード３ｈが第１ボンドとして接続され、一方、チップ側のパッド１ｃが第２ボンドとして接続されたものである。   At this time, in the CSP 7 of the first embodiment, as shown in FIG. 1, each of the plurality of wires 4 electrically connects the pad 1c of the semiconductor chip 1 and the bonding lead 3h of the package substrate 3 corresponding thereto. In addition to the connection, the bonding lead 3h on the substrate side is connected as the first bond, while the pad 1c on the chip side is connected as the second bond.

ここで、前記第１ボンドは、電気トーチによりワイヤ先端に形成されたボールをキャピラリ１８で端子に押し付けて接続するものであり、一方、前記第２ボンドは、第１ボンド後、ワイヤ４を前記端子から引き出してキャピラリ１８を他方の端子上に配置し、その後、ワイヤ４の一部を前記他方の端子に対してキャピラリ１８で押し潰してこの他方の端子に接続するものである。   Here, the first bond is to connect a ball formed at the tip of the wire by an electric torch against a terminal with a capillary 18, while the second bond connects the wire 4 after the first bond. The capillary 18 is pulled out from the terminal and placed on the other terminal, and then a part of the wire 4 is crushed against the other terminal by the capillary 18 and connected to the other terminal.

本実施の形態１のＣＳＰ７では、前記第１ボンドがパッケージ基板３のボンディングリード３ｈに対して行われ、前記第２ボンドが半導体チップ１のパッド１ｃに対して行われたものである。すなわち、ＣＳＰ７は、半導体チップ１のパッド１ｃとパッケージ基板３のボンディングリード３ｈとの接続において、逆ボンディングによるワイヤボンディングが行われて組み立てられたものである。   In the CSP 7 of the first embodiment, the first bond is made to the bonding lead 3 h of the package substrate 3, and the second bond is made to the pad 1 c of the semiconductor chip 1. That is, the CSP 7 is assembled by performing wire bonding by reverse bonding at the connection between the pad 1c of the semiconductor chip 1 and the bonding lead 3h of the package substrate 3.

これは、ＣＳＰ７は、半導体チップ１とパッケージ基板３の大きさがほぼ同じ小型の半導体パッケージであり、チップの端部から基板の端部までの距離が、約0.２〜0.３ｍｍと非常に狭い構造となっており、さらにボンディングリード３ｈとチップの端部との距離も約0.１ｍｍ程度と非常に狭いため、基板上の半導体チップ１の外側の領域において第２ボンドとしてキャピラリ１８を滑らしながら配置することが困難なためである。   This is because the CSP 7 is a small semiconductor package in which the size of the semiconductor chip 1 and the package substrate 3 are substantially the same, and the distance from the end of the chip to the end of the substrate is about 0.2 to 0.3 mm. In addition, since the distance between the bonding lead 3h and the end of the chip is very narrow, about 0.1 mm, the capillary 18 is formed as a second bond in the region outside the semiconductor chip 1 on the substrate. This is because it is difficult to arrange while sliding.

すなわち、ワイヤ接続時にキャピラリ１８をボンディングリード３ｈから上方に移動させることでワイヤボンディング用に狭い領域しか確保できない基板側を第１ボンドとし、チップ側を第２ボンドとするものである。   That is, by moving the capillary 18 upward from the bonding lead 3h at the time of wire connection, the substrate side where only a narrow region for wire bonding can be secured is defined as the first bond, and the chip side is defined as the second bond.

さらに、本実施の形態１のＣＳＰ７では、図1に示すように、パッケージ基板３の主面３ａ上において、逆ボンディングによって接続されたそれぞれのワイヤ４の一部が、ボンディングリード３ｈにおける第１ボンドのワイヤ接続部４ａより外側に（パッケージ基板３の外周部に向かって）配置（形成）されている。   Furthermore, in the CSP 7 of the first embodiment, as shown in FIG. 1, a part of each wire 4 connected by reverse bonding on the main surface 3a of the package substrate 3 is connected to the first bond in the bonding lead 3h. Is arranged (formed) outside the wire connection portion 4a (toward the outer peripheral portion of the package substrate 3).

具体的には、図４に示すように、ワイヤ４の一部であるループの頂点４ｂが第１ボンドのワイヤ接続部４ａより外側に配置されている。すなわち、各ワイヤ４のループの最上位地点（ここでは４ｂ）がワイヤ接続部４ａのワイヤ引き出し方向の中心線１３より外側（半導体チップ１から離れる方向）に配置されているものである。   Specifically, as shown in FIG. 4, the apex 4b of the loop, which is a part of the wire 4, is disposed outside the wire connection portion 4a of the first bond. That is, the uppermost point (here, 4b) of the loop of each wire 4 is arranged outside (in the direction away from the semiconductor chip 1) from the center line 13 in the wire drawing direction of the wire connection portion 4a.

ここで、図５〜図８を用いて、図４に示すワイヤ４のループ形状の形成方法について説明すると、まず、パッケージ基板３のボンディングリード３ｈに第１ボンドを行う。すなわち、ワイヤ４のボール状に形成された先端部を、図４、図５に示すように、キャピラリ１８でパッケージ基板３の図４に示すボンディングリード３ｈに押し付けて接続する。   Here, a method for forming the loop shape of the wire 4 shown in FIG. 4 will be described with reference to FIGS. 5 to 8. First, a first bond is made to the bonding lead 3 h of the package substrate 3. That is, the tip of the wire 4 formed in a ball shape is pressed and connected to the bonding lead 3h shown in FIG. 4 of the package substrate 3 by the capillary 18, as shown in FIGS.

その後、図６に示すように、キャピラリ１８を半導体チップ１から離れる方向に移動させてワイヤ４を前記ボンディングリード３ｈから引き出す。すなわち、キャピラリ１８を半導体チップ１から離れる方向で（パッケージ基板３の外周部に向かって）、かつ斜め上方に移動させてワイヤ４を前記ボンディングリード３ｈから斜め上方に引き出す。   Thereafter, as shown in FIG. 6, the capillary 18 is moved away from the semiconductor chip 1 and the wire 4 is pulled out from the bonding lead 3h. That is, the capillary 18 is moved obliquely upward in a direction away from the semiconductor chip 1 (toward the outer peripheral portion of the package substrate 3), and the wire 4 is drawn obliquely upward from the bonding lead 3h.

その後、キャピラリ１８の移動を所定箇所で一旦停止し、続いて図７に示すように、キャピラリ１８を真上（垂直上）に移動させてワイヤ４を上方に引き出す。   Thereafter, the movement of the capillary 18 is temporarily stopped at a predetermined position, and then, as shown in FIG. 7, the capillary 18 is moved right above (vertically upward), and the wire 4 is drawn upward.

その後、ワイヤ４がチップ高さを超えたところでキャピラリ１８の上方への移動を停止し、その後、図８に示すように、キャピラリ１８を半導体チップ１のパッド１ｃ上にほぼ水平に移動させて、半導体チップ１のパッド１ｃ上にワイヤ４を配置する。   Thereafter, when the wire 4 exceeds the chip height, the upward movement of the capillary 18 is stopped, and then, as shown in FIG. 8, the capillary 18 is moved almost horizontally onto the pad 1c of the semiconductor chip 1, A wire 4 is disposed on the pad 1 c of the semiconductor chip 1.

その後、パッド１ｃにおいてキャピラリ１８によりワイヤ４の一部を押し潰して半導体チップ１のパッド１ｃにワイヤ４を接続する。これにより、ワイヤ４と半導体チップ１のパッド１ｃとの接続である第２ボンドを完了するとともに、各ワイヤ４のループの頂点４ｂがワイヤ接続部４ａより外側に配置された状態となる。   Thereafter, a part of the wire 4 is crushed by the capillary 18 at the pad 1 c to connect the wire 4 to the pad 1 c of the semiconductor chip 1. As a result, the second bond, which is the connection between the wire 4 and the pad 1c of the semiconductor chip 1, is completed, and the apex 4b of the loop of each wire 4 is placed outside the wire connection portion 4a.

なお、半導体チップ１のパッド１ｃ上には、予め金バンプ（スタッドバンプ）１９が形成されており、第２ボンドの際には、ワイヤ４をパッド１ｃ上の金バンプ１９に接続する。これは、ワイヤボンディング工程において、第２ボンドの際には、キャピラリ１８を擦り付ける様にワイヤ４をパッド１ｃ（又は、ボンディングリード３ｈ）に圧着するため、キャピラリ１８を滑走させる距離だけパッド１ｃの形状を相対的に大きく形成しておく必要がある。しかしながら、本実施の形態１のように、逆ボンディング方式の場合、半導体チップ１の主面上に形成されたパッド１ｃを相対的に大きく形成しようとすると、その分半導体チップ１を小型化することが困難となる。更には、半導体チップ１の主面上において上記圧着動作を行うと、圧着圧力により、半導体チップ１に応力が伝わり、特に半導体チップ１の厚さが薄ければチップの抗折強度も低いため、チップクラックを起こす原因となる。そこで、第２ボンドする前に、金バンプ１９を形成しておく。金バンプ１９はパッド１ｃに比べ硬度が低いため、微小な圧着圧力でもワイヤ４の一部を容易に圧着することが可能である。更には、第１ボンドする前に金バンプ１９を形成しておくことで、第２ボンドする際のボンディングポイントを事前に認識しておくことが可能であるため、ワイヤボンディングの座標が変わらず、安定したワイヤボンディング工程が可能となる。ただし、半導体チップ１の面積が相対的に大きく、半導体チップ１の厚さも厚ければチップの抗折強度も高いため、パッド１ｃ上に金バンプ１９は形成されていなくてもよく、その場合は、ワイヤ４を直接パッド１ｃに接続する。   A gold bump (stud bump) 19 is formed in advance on the pad 1c of the semiconductor chip 1, and the wire 4 is connected to the gold bump 19 on the pad 1c at the time of the second bond. This is because the wire 4 is pressed against the pad 1c (or the bonding lead 3h) so that the capillary 18 is rubbed during the second bonding in the wire bonding step. Must be formed relatively large. However, in the case of the reverse bonding method as in the first embodiment, if the pad 1c formed on the main surface of the semiconductor chip 1 is to be formed relatively large, the semiconductor chip 1 is reduced in size accordingly. It becomes difficult. Furthermore, when the above crimping operation is performed on the main surface of the semiconductor chip 1, stress is transmitted to the semiconductor chip 1 due to the crimping pressure, and particularly when the thickness of the semiconductor chip 1 is thin, the bending strength of the chip is low. Causes chip cracking. Therefore, the gold bump 19 is formed before the second bonding. Since the gold bump 19 has a lower hardness than the pad 1c, it is possible to easily crimp a part of the wire 4 even with a very small pressure. Furthermore, by forming the gold bump 19 before the first bonding, it is possible to recognize in advance the bonding point at the time of the second bonding, so the coordinates of the wire bonding do not change, A stable wire bonding process is possible. However, if the area of the semiconductor chip 1 is relatively large and the thickness of the semiconductor chip 1 is large, the die bending strength of the chip is high. Therefore, the gold bump 19 may not be formed on the pad 1c. The wire 4 is directly connected to the pad 1c.

次に、図９〜図１２に示すＣＳＰ７に組み込まれるパッケージ基板３の構造について説明する。   Next, the structure of the package substrate 3 incorporated in the CSP 7 shown in FIGS. 9 to 12 will be described.

パッケージ基板３は、コア材３ｃと、その主面３ａ及び裏面３ｂに形成された複数の導体部と、主面３ａと裏面３ｂの前記導体部を接続するスルーホール３ｅと、前記導体部の少なくとも一部を覆うソルダレジスト膜３ｆとを有している。パッケージ基板３の表面である主面３ａには、図９に示すように基板の外周部（周縁部）に複数のボンディングリード３ｈが各辺に沿って一列に並んで設けられている。   The package substrate 3 includes a core material 3c, a plurality of conductor portions formed on the main surface 3a and the back surface 3b, a through hole 3e connecting the conductor portions on the main surface 3a and the back surface 3b, and at least of the conductor portions. And a solder resist film 3f covering a part thereof. On the main surface 3a which is the surface of the package substrate 3, as shown in FIG. 9, a plurality of bonding leads 3h are provided in a line along each side on the outer peripheral portion (peripheral portion) of the substrate.

なお、ボンディングリード３ｈは、それぞれスルーホール３ｅと銅配線３ｇを介して電気的に接続されている。また、各ボンディングリード３ｈにはそれぞれの外側に向かって給電線３ｊが接続されている。   The bonding leads 3h are electrically connected through the through holes 3e and the copper wirings 3g, respectively. A power supply line 3j is connected to each bonding lead 3h toward the outside.

一方、パッケージ基板３の裏面３ｂには、図１０に示すように、複数のランド３ｄが格子状に配置されて設けられており、これらランド３ｄには外部端子である半田バンプ８（図３参照）が接続される。また、複数のランド３ｄは、それぞれスルーホール３ｅと接続されている。   On the other hand, on the back surface 3b of the package substrate 3, as shown in FIG. 10, a plurality of lands 3d are provided in a grid pattern, and solder bumps 8 (see FIG. 3) as external terminals are provided on these lands 3d. ) Is connected. The plurality of lands 3d are connected to the through holes 3e, respectively.

このようにパッケージ基板３の主面３ａ及び裏面３ｂには、ボンディングリード３ｈ、銅配線３ｇ、給電線３ｊ、ランド３ｄ及びスルーホール３ｅ等の導体部が形成されており、これらの導体部は、例えば、銅合金（Ｃｕ）によって形成されている。また、複数のランド３ｄ及びボンディングリード３ｈには、導電性のワイヤ４との接続強度を向上するために、銅合金の上にＮｉ／Ａｕ、あるいはＮｉ／Ｐｄ／Ａｕなどの表面処理を施している。   Thus, conductor parts such as bonding leads 3h, copper wirings 3g, power supply lines 3j, lands 3d, and through holes 3e are formed on the main surface 3a and the back surface 3b of the package substrate 3, and these conductor parts are For example, it is made of a copper alloy (Cu). In addition, in order to improve the connection strength with the conductive wire 4, the plurality of lands 3 d and bonding leads 3 h are subjected to surface treatment such as Ni / Au or Ni / Pd / Au on the copper alloy. Yes.

また、パッケージ基板３の主面３ａ及び裏面３ｂには、図１２に示すように絶縁膜であるソルダレジスト膜３ｆが形成されている。なお、主面３ａにおいては、ソルダレジスト膜３ｆの細長い開口部３ｉ（図９参照）に複数のボンディングリード３ｈが並んだ状態で露出している。一方、裏面３ｂにおいては、ランド３ｄのみが露出している。すなわち、ソルダレジスト膜３ｆは、ボンディングリード３ｈやランド３ｄ以外の導体部である銅配線３ｇ、給電線３ｊ及びスルーホール３ｅ等を覆っている。   Further, a solder resist film 3f, which is an insulating film, is formed on the main surface 3a and the back surface 3b of the package substrate 3, as shown in FIG. The main surface 3a is exposed in a state where a plurality of bonding leads 3h are arranged in the elongated opening 3i (see FIG. 9) of the solder resist film 3f. On the other hand, only the land 3d is exposed on the back surface 3b. That is, the solder resist film 3f covers the copper wiring 3g, the feed line 3j, the through hole 3e, and the like, which are conductor parts other than the bonding lead 3h and the land 3d.

次に、ＣＳＰ７に組み込まれている種々の構成部材の材質等について説明すると、半導体チップ１は、例えば、シリコンなどによって形成され、その主面１ａには集積回路が形成されている。さらに、図１に示すように半導体チップ１の主面１ａの周縁部には複数の電極であるパッド１ｃが形成されている。また、このパッド１ｃと、パッケージ基板３の主面３ａの外周部（周縁部）に配置されたボンディングリード３ｈとを電気的に接続する導電性のワイヤ４は、例えば、金線などである。   Next, materials and the like of various components incorporated in the CSP 7 will be described. The semiconductor chip 1 is formed of, for example, silicon, and an integrated circuit is formed on the main surface 1a. Further, as shown in FIG. 1, pads 1 c that are a plurality of electrodes are formed on the peripheral portion of the main surface 1 a of the semiconductor chip 1. Further, the conductive wire 4 that electrically connects the pad 1c and the bonding lead 3h disposed on the outer peripheral portion (peripheral portion) of the main surface 3a of the package substrate 3 is, for example, a gold wire.

また、半導体チップ１は、図２、図３に示すように、その裏面１ｂが、ダイボンド用フィルム２を介してパッケージ基板３に固着され、主面１ａを上方に向けた状態でパッケージ基板３に搭載されている。   2 and 3, the semiconductor chip 1 is fixed to the package substrate 3 with the back surface 1b fixed to the package substrate 3 via the die bonding film 2, and the main surface 1a is directed upward. It is installed.

さらに、半導体チップ１や複数の導電性のワイヤ４を樹脂封止する封止体６は、例えば、熱硬化性のエポキシ樹脂などによって形成されている。   Furthermore, the sealing body 6 for resin-sealing the semiconductor chip 1 and the plurality of conductive wires 4 is formed of, for example, a thermosetting epoxy resin.

次に、本実施の形態１のＣＳＰ７の製造方法を、図１３及び図１４に示す製造プロセスフロー図を用いて説明する。   Next, a manufacturing method of the CSP 7 according to the first embodiment will be described with reference to manufacturing process flowcharts shown in FIGS.

まず、図１３のステップＳ１に示す基板準備を行う。ここでは、複数のパッケージ基板３を形成する領域が区画配置された多数個取り基板９を準備する。なお、パッケージ基板３を形成する領域には、各領域の外周部（周縁部）に複数のボンディングリード３ｈが並んで配置された基板を準備する。   First, substrate preparation shown in step S1 of FIG. 13 is performed. Here, a multi-chip substrate 9 in which regions for forming a plurality of package substrates 3 are partitioned is prepared. In a region where the package substrate 3 is to be formed, a substrate is prepared in which a plurality of bonding leads 3h are arranged side by side on the outer peripheral portion (peripheral portion) of each region.

その後、ステップＳ２に示すダイボンディングを行って多数個取り基板９上に図３に示すダイボンド用フィルム２を介して半導体チップ１を固着する。その際、ダイボンド用フィルム２は、例えば、半導体ウエハをダイシングによって個片化する際に用いるダイシング用のテープ部材の接着層をウエハ裏面に残留させたものである。   Thereafter, die bonding shown in step S2 is performed, and the semiconductor chip 1 is fixed on the multi-piece substrate 9 via the die bonding film 2 shown in FIG. At that time, the die-bonding film 2 is obtained by, for example, leaving an adhesive layer of a tape member for dicing used for dicing a semiconductor wafer on the back surface of the wafer.

なお、パッケージ基板３に対応した各領域には、各領域の外周部に複数のボンディングリード３ｈが並んで配置されており、したがって、半導体チップ１は、外周部のボンディングリード列の内側に搭載する。   In each region corresponding to the package substrate 3, a plurality of bonding leads 3h are arranged side by side on the outer periphery of each region, and therefore the semiconductor chip 1 is mounted inside the bonding lead row on the outer periphery. .

その後、ステップＳ３に示すワイヤボンディングを行う。ここでは、図３及び図４に示すように、半導体チップ１の主面１ａのパッド１ｃと、これに対応する多数個取り基板９のパッケージ基板３のボンディングリード３ｈとを金線等の導電性のワイヤ４によって電気的に接続する。   Thereafter, wire bonding shown in step S3 is performed. Here, as shown in FIGS. 3 and 4, the pads 1c on the main surface 1a of the semiconductor chip 1 and the bonding leads 3h of the package substrate 3 of the multi-chip substrate 9 corresponding thereto are electrically conductive such as gold wires. The wire 4 is electrically connected.

その際、本実施の形態１では、逆ボンディング方式によって基板のボンディングリード３ｈと半導体チップ１のパッド１ｃとをワイヤ４で接続する。また、各ワイヤ４において、ワイヤ４の一部であるループの頂点４ｂが第１ボンドのワイヤ接続部４ａより外側に配置されるようにワイヤボンディングする。すなわち、各ワイヤ４のループの最上位地点がワイヤ接続部４ａのワイヤ引き出し方向の中心線１３より外側（パッケージ基板３の外周部側）に配置されるようにワイヤボンディングする。   At this time, in the first embodiment, the bonding lead 3h of the substrate and the pad 1c of the semiconductor chip 1 are connected by the wire 4 by the reverse bonding method. Further, in each wire 4, wire bonding is performed so that the apex 4 b of the loop which is a part of the wire 4 is disposed outside the wire connection portion 4 a of the first bond. That is, wire bonding is performed so that the uppermost point of the loop of each wire 4 is arranged outside the center line 13 in the wire drawing direction of the wire connecting portion 4a (outside of the package substrate 3).

ワイヤボンディング工程では、まず、多数個取り基板９のパッケージ基板３の領域のボンディングリード３ｈに第１ボンドを行う。すなわち、図５に示すように、ワイヤ４のボール状に形成された先端部をキャピラリ１８で基板の図４に示すボンディングリード３ｈに押し付けて接続する。   In the wire bonding process, first, a first bond is made to the bonding lead 3 h in the region of the package substrate 3 of the multi-chip substrate 9. That is, as shown in FIG. 5, the tip of the wire 4 formed in a ball shape is pressed and connected to the bonding lead 3h shown in FIG.

その後、図６に示すように、キャピラリ１８を半導体チップ１から離れる方向に移動させてワイヤ４を前記ボンディングリード３ｈから引き出す。すなわち、キャピラリ１８を半導体チップ１から離れる方向で、かつ斜め上方に移動させてワイヤ４を前記ボンディングリード３ｈから斜め上方に引き出す。   Thereafter, as shown in FIG. 6, the capillary 18 is moved away from the semiconductor chip 1 and the wire 4 is pulled out from the bonding lead 3h. That is, the capillary 18 is moved in the direction away from the semiconductor chip 1 and obliquely upward, and the wire 4 is drawn obliquely upward from the bonding lead 3h.

その後、キャピラリ１８の移動を所定箇所で一旦停止し、続いて図７に示すように、キャピラリ１８を真上（垂直上）に移動させてワイヤ４を上方に引き出す。   Thereafter, the movement of the capillary 18 is temporarily stopped at a predetermined position, and then, as shown in FIG. 7, the capillary 18 is moved right above (vertically upward), and the wire 4 is drawn upward.

その後、ワイヤ４がチップ高さを超えたところでキャピラリ１８の上方への移動を停止し、その後、図８に示すように、キャピラリ１８を半導体チップ１のパッド１ｃ上にほぼ水平に移動させて、半導体チップ１のパッド１ｃ上にワイヤ４を配置する。   Thereafter, when the wire 4 exceeds the chip height, the upward movement of the capillary 18 is stopped, and then, as shown in FIG. 8, the capillary 18 is moved almost horizontally onto the pad 1c of the semiconductor chip 1, A wire 4 is disposed on the pad 1 c of the semiconductor chip 1.

その後、パッド１ｃにおいてキャピラリ１８によりワイヤ４の一部を押し潰して半導体チップ１のパッド１ｃにワイヤ４を接続する。これにより、ワイヤ４と半導体チップ１のパッド１ｃとの接続である第２ボンドを完了するとともに、各ワイヤ４のループの頂点４ｂがワイヤ接続部４ａより外側に配置された状態となる。   Thereafter, a part of the wire 4 is crushed by the capillary 18 at the pad 1 c to connect the wire 4 to the pad 1 c of the semiconductor chip 1. As a result, the second bond, which is the connection between the wire 4 and the pad 1c of the semiconductor chip 1, is completed, and the apex 4b of the loop of each wire 4 is placed outside the wire connection portion 4a.

なお、半導体チップ１のパッド１ｃ上には、予め金バンプ１９が形成されており、第２ボンドの際には、ワイヤ４をパッド１ｃ上の金バンプ１９に接続する。ただし、パッド１ｃ上に金バンプ１９は形成されていなくてもよく、その場合は、ワイヤ４を直接パッド１ｃに接続する。   Note that a gold bump 19 is formed in advance on the pad 1c of the semiconductor chip 1, and the wire 4 is connected to the gold bump 19 on the pad 1c in the second bonding. However, the gold bump 19 may not be formed on the pad 1c, and in that case, the wire 4 is directly connected to the pad 1c.

その後、ステップＳ４に示す樹脂モールドを行う。ここでは、多数個取り基板９上において、樹脂成形金型２０の１つのキャビティ２０ａで多数個取り基板９上の複数の領域（複数のパッケージ基板３の領域）を一括して覆った状態で樹脂封止を行い、これにより、一括封止体５を形成する。なお、一括封止体５を形成する封止用樹脂は、例えば、熱硬化性のエポキシ樹脂などである。   Thereafter, resin molding shown in step S4 is performed. Here, on the multi-cavity substrate 9, the resin 20 in a state where a plurality of regions (regions of the plurality of package substrates 3) on the multi-cavity substrate 9 are collectively covered with one cavity 20 a of the resin molding die 20. Sealing is performed, thereby forming the collective sealing body 5. The sealing resin forming the collective sealing body 5 is, for example, a thermosetting epoxy resin.

その後、図１４のステップＳ５に示すボールマウントを行って図３に示すように各ランド３ｄに半田バンプ８を接続する。   Thereafter, ball mounting shown in step S5 of FIG. 14 is performed, and solder bumps 8 are connected to the respective lands 3d as shown in FIG.

その後、ステップＳ６に示すマークを行う。ここではレーザマーキング法などでマーキング１０を行って一括封止体５にマークを付す。なお、マーキング１０は、例えば、インクマーキング法などで行ってもよい。   Then, the mark shown in step S6 is performed. Here, the marking 10 is performed by a laser marking method or the like to mark the collective sealing body 5. The marking 10 may be performed by, for example, an ink marking method.

その後、ステップＳ７に示す個片化を行う。ここでは、一括封止体５の表面にダイシングテープ１２を貼り、ダイシングテープ１２で固定した状態でダイシングブレード１１によって切断して各ＣＳＰ７に個片化する。   Thereafter, individualization shown in step S7 is performed. Here, the dicing tape 12 is attached to the surface of the collective sealing body 5, and the dicing blade 11 cuts the individual CSPs 7 while being fixed with the dicing tape 12.

これにより、ステップＳ８に示すようにＣＳＰ７の組み立てを完了して製品完成となる。   Thereby, as shown in step S8, the assembly of the CSP 7 is completed and the product is completed.

なお、図１５は一括封止による樹脂モールド後の組み立ての変形例を示す製造プロセスフロー図であり、この変形例の製造プロセスは、マークを行った後にボールマウントを行うものである。   FIG. 15 is a manufacturing process flow chart showing a modified example of assembly after resin molding by batch sealing. The manufacturing process of this modified example is to perform ball mounting after marking.

ボールマウントの工程は、パッケージ基板３のランド３ｄに半田を塗布した後、リフロー処理により半田バンプ８を形成する。このため、ボールマウントの工程においても、このリフロー処理によりパッケージ基板３が更に反る問題が生じる。マークの工程では、レーザマーキング法などでマーキングを行うが、パッケージ基板３が反った状態では、一括封止体５の表面に垂直にレーザを照射することが困難となるため、一括封止体５の表面にマークが付されないというマーキング不良が発生する。   In the ball mounting process, solder is applied to the lands 3d of the package substrate 3, and then solder bumps 8 are formed by reflow processing. For this reason, also in the process of ball mounting, the problem that the package substrate 3 is further warped by this reflow process occurs. In the mark process, marking is performed by a laser marking method or the like. However, when the package substrate 3 is warped, it is difficult to irradiate the surface of the batch sealing body 5 with a laser beam vertically. Marking defect that the mark is not attached to the surface of the sheet occurs.

そこで、図１５に示す変形例では、パッケージ基板３が反る要因の一つである半田バンプ８形成時のリフロー処理を行う前に、先にマークの工程を行う。これにより、マーキング不良を抑制することができる。   Therefore, in the modification shown in FIG. 15, the mark process is first performed before the reflow process at the time of forming the solder bump 8, which is one of the factors that cause the package substrate 3 to warp. Thereby, marking failure can be suppressed.

本実施の形態１の半導体装置及びその製造方法によれば、逆ボンディングによって接続された各ワイヤの一部であるループの頂点４ｂが、パッケージ基板３のボンディングリード３ｈにおける第１ボンドのワイヤ接続部４ａより外側（パッケージ基板３の外周部側）に配置されていることにより、ワイヤ４が外側に遠回りして引き回されるため、パッケージ基板３のボンディングリード３ｈと半導体チップ１のパッド１ｃとの接続においてワイヤ長を長くすることができる。   According to the semiconductor device and the manufacturing method thereof in the first embodiment, the apex 4b of the loop, which is a part of each wire connected by reverse bonding, is the wire connection portion of the first bond in the bonding lead 3h of the package substrate 3 Since the wire 4 is routed away from the outside by being arranged outside 4a (outer peripheral side of the package substrate 3), the bonding lead 3h of the package substrate 3 and the pad 1c of the semiconductor chip 1 are connected. The wire length can be increased in connection.

これにより、ワイヤ４の引き回しのマージンが増えてキャピラリ１８の動く速度にワイヤ送り速度が追従することが可能になり、ワイヤ４のループ形状の安定化を図ることができる。   As a result, the margin for routing the wire 4 is increased and the wire feed speed can follow the speed at which the capillary 18 moves, so that the loop shape of the wire 4 can be stabilized.

その結果、チップ端部とワイヤ４のショートを低減してワイヤ接続不良の発生を低減することができ、ワイヤ接続不良の抑制化を図ることができる。   As a result, the short-circuit between the chip end and the wire 4 can be reduced to reduce the occurrence of wire connection failure, and the wire connection failure can be suppressed.

これにより、半導体チップ１の主面１ａの端部にテストパターンが形成されている場合であっても、テストパターンとワイヤ４とがショートすることを低減できる。   Thereby, even when the test pattern is formed at the end of the main surface 1a of the semiconductor chip 1, it is possible to reduce the short-circuit between the test pattern and the wire 4.

また、ワイヤ４を外側に遠回りさせることにより、パッケージ端部からパッケージ基板３の端子（ボンディングリード３ｈ）までの距離を長くしてリークパスを長くできるため、吸湿不良のマージンを確保することが可能になる。   Further, by turning the wire 4 outward, the distance from the package end to the terminal (bonding lead 3h) of the package substrate 3 can be lengthened to increase the leak path, thereby making it possible to secure a margin for poor moisture absorption. Become.

また、ワイヤ４を遠回りさせる方法としては、ループの頂点４ｂを高くしてもワイヤ長を長く形成することは可能であるが、その場合、ワイヤ４の一部が封止体６の表面側から露出しないように、封止体６を厚く形成する必要がある。そのため、半導体装置の薄型化が困難となる。しかしながら、本実施の形態１では、ワイヤ４を外側（半導体チップ１とは反対側の方向）に遠回りさせて横方向に膨らませているため、ワイヤ４の一部が封止体６の表面側から露出することを防止できる。すなわち、低ループを形成しつつワイヤ長を長くすることができるため、ＣＳＰ７の更なる薄型化にも対応することができる。   Further, as a method of rotating the wire 4, it is possible to make the wire length longer even if the apex 4 b of the loop is increased, but in that case, a part of the wire 4 extends from the surface side of the sealing body 6. The sealing body 6 needs to be formed thick so as not to be exposed. This makes it difficult to reduce the thickness of the semiconductor device. However, in the first embodiment, since the wire 4 is turned outward (in the direction opposite to the semiconductor chip 1) and expanded in the lateral direction, a part of the wire 4 is exposed from the surface side of the sealing body 6. Exposure can be prevented. In other words, since the wire length can be increased while forming a low loop, the CSP 7 can be made thinner.

さらに、低ループによってワイヤ長を長くできるため、半導体装置の薄型化の要求が低ければ、ワイヤ４を低ループで形成したことにより、ワイヤ４のループの頂点４ｂから封止体６の表面までの厚さを十分確保できる。これにより、封止体６の表面にレーザマーキングを施したとしても、レーザマーキングにより形成される溝からワイヤ４が露出する恐れや、レーザによりワイヤ４の一部を溶断する恐れを低減することができる。   Furthermore, since the wire length can be increased by the low loop, if the demand for thinning the semiconductor device is low, the wire 4 is formed by the low loop, so that the wire 4 has a loop apex 4b to the surface of the sealing body 6. Thickness can be secured sufficiently. As a result, even if laser marking is performed on the surface of the sealing body 6, the possibility that the wire 4 is exposed from the groove formed by the laser marking or the possibility that a part of the wire 4 is melted by the laser can be reduced. it can.

また、ワイヤボンディングにおいて、逆ボンディング方式を採用することにより、第２ボンド時にキャピラリ１８を極端に低い側に打ち降ろすことを避けることができる。これにより、ワイヤ４がキャピラリ１８と半導体チップ１の端部の間に入らない問題や、１ｓｔ側から２ｎｄ側に打ち下ろしたワイヤ４にキャピラリ１８の一部が接触する問題、更にはキャピラリ１８の先端のワイヤ４との摩耗を低減することができ、キャピラリ１８の長寿命化を図ることができる。   Further, by adopting a reverse bonding method in wire bonding, it is possible to avoid the capillary 18 from being lowered to an extremely low side during the second bonding. As a result, there is a problem that the wire 4 does not enter between the capillary 18 and the end of the semiconductor chip 1, a problem that a part of the capillary 18 comes into contact with the wire 4 dropped from the 1st side to the 2nd side, Wear with the wire 4 at the tip can be reduced, and the life of the capillary 18 can be extended.

次に、本実施の形態１の変形例のパッケージ基板３について説明する。   Next, a description will be given of a package substrate 3 according to a modification of the first embodiment.

図１６〜図１９に示す変形例のパッケージ基板３は、導体部のめっきが、無電解めっき処理によって形成されたものであり、図９に示すパッケージ基板３のようなボンディングリード３ｈの外側の給電線３ｊが形成されていない構造となっている。したがって、主面３ａに形成されたソルダレジスト膜３ｆがボンディングリード３ｈ上のワイヤ接続部４ａより内側に配置されている。   The package substrate 3 of the modified example shown in FIGS. 16 to 19 is one in which the conductor portion is plated by electroless plating, and the supply of the bonding lead 3h like the package substrate 3 shown in FIG. The electric wire 3j is not formed. Therefore, the solder resist film 3f formed on the main surface 3a is disposed on the inner side of the wire connection portion 4a on the bonding lead 3h.

また、図２０〜２２に示す変形例のパッケージ基板３は、各ボンディングリード３ｈの外側に給電線３ｊが形成されており、一方、給電線３ｊを覆うソルダレジスト膜３ｆは形成されずにボンディングリード３ｈとともに給電線３ｊが露出している構造のものである。   Further, in the package substrate 3 of the modified example shown in FIGS. 20 to 22, the power supply line 3j is formed outside each bonding lead 3h, while the solder resist film 3f covering the power supply line 3j is not formed and the bonding lead is formed. The power supply line 3j is exposed together with 3h.

これは、ＣＳＰ７では、半導体チップ１の端部からパッケージ基板３の端部までの距離が約0.２〜0.３ｍｍと非常に狭く、かつソルダレジスト膜３ｆの位置精度は、±0.０５ｍｍと非常に大きいため、給電線３ｊ上にソルダレジスト膜３ｆを形成した場合の位置ずれを考慮して、ソルダレジスト膜３ｆを形成せずに給電線３ｊを露出させるものである。   This is because in CSP7, the distance from the end of the semiconductor chip 1 to the end of the package substrate 3 is very narrow, about 0.2 to 0.3 mm, and the positional accuracy of the solder resist film 3f is ± 0.05 mm. Therefore, considering the positional shift when the solder resist film 3f is formed on the power supply line 3j, the power supply line 3j is exposed without forming the solder resist film 3f.

ただし、給電線３ｊを露出させた場合、ソルダレジスト膜３ｆの位置ずれの問題は回避されるものの、吸湿の影響が出る可能性があり、したがって、各ボンディングリード３ｈの外側に給電線３ｊが形成されている場合、給電線３ｊを覆うソルダレジスト膜３ｆは形成されていても、形成されていなくてもどちらでもよいが、チップ端部から基板端部までの距離との兼ね合いで形成可能であれば形成した方が好ましい。   However, when the power supply line 3j is exposed, the problem of misalignment of the solder resist film 3f can be avoided, but there is a possibility of moisture absorption. Therefore, the power supply line 3j is formed outside each bonding lead 3h. In this case, the solder resist film 3f covering the power supply line 3j may or may not be formed, but can be formed in consideration of the distance from the chip end to the substrate end. It is preferable to form it.

（実施の形態２）
図２３は本発明の実施の形態２の半導体装置の構造の一例を封止体を透過して示す平面図、図２４は図２３に示す半導体装置の構造の一例を示す断面図、図２５は図２４に示すＡ部の構造を示す拡大部分断面図、図２６は図２４に示すＢ部の構造を示す拡大部分断面図である。 (Embodiment 2)
23 is a plan view showing an example of the structure of the semiconductor device according to the second embodiment of the present invention through a sealing body, FIG. 24 is a cross-sectional view showing an example of the structure of the semiconductor device shown in FIG. 23, and FIG. FIG. 26 is an enlarged partial sectional view showing the structure of the A part shown in FIG. 24, and FIG. 26 is an enlarged partial sectional view showing the structure of the B part shown in FIG.

図２３〜図２６に示す本実施の形態２の半導体装置は、半導体チップ１の上に他の半導体チップである第２の半導体チップ１７がダイボンド用フィルム２を介して固定されているものであり、実施の形態１のＣＳＰ７と同様に樹脂封止型で、かつ小型のチップスタック構造のＣＳＰ１４である。   In the semiconductor device of the second embodiment shown in FIGS. 23 to 26, a second semiconductor chip 17, which is another semiconductor chip, is fixed on the semiconductor chip 1 via a die bonding film 2. Like the CSP 7 of the first embodiment, the CSP 14 has a resin-encapsulated type and a small chip stack structure.

すなわち、図２５及び図２６に示すように、パッケージ基板３の主面３ａのソルダレジスト膜３ｆ上に、ダイボンド用フィルム２を介して１段目（下段側）の半導体チップ１がその主面１ａを上方に向けてフェイスアップ実装されており、さらにこの上に２段目（上段側）の第２の半導体チップ１７がその主面１７ａを上方に向けてフェイスアップ実装されている。その際、第２の半導体チップ１７もその裏面１７ｂがダイボンド用フィルム２を介して半導体チップ１の主面１ａ上に固定されている。   That is, as shown in FIGS. 25 and 26, the first-stage (lower stage) semiconductor chip 1 is placed on the solder resist film 3f of the main surface 3a of the package substrate 3 via the die-bonding film 2 on the main surface 1a. The second semiconductor chip 17 at the second stage (upper stage side) is further mounted face up with the main surface 17a facing upward. At that time, the back surface 17 b of the second semiconductor chip 17 is also fixed on the main surface 1 a of the semiconductor chip 1 through the die bonding film 2.

また、ＣＳＰ１４は、実施の形態１のＣＳＰ７と同様に小型の半導体パッケージである。すなわち、半導体チップ１の大きさとパッケージ基板３の大きさがほぼ同じであり、パッケージ基板３の方が僅かに大きい程度である。例えば、半導体チップ１の端部からパッケージ基板３の端部までの距離は、ＣＳＰ７と同様に約0.２〜0.３ｍｍと非常に狭い。   The CSP 14 is a small semiconductor package similar to the CSP 7 of the first embodiment. That is, the size of the semiconductor chip 1 and the size of the package substrate 3 are substantially the same, and the package substrate 3 is slightly larger. For example, the distance from the end of the semiconductor chip 1 to the end of the package substrate 3 is as narrow as about 0.2 to 0.3 mm, as in the case of the CSP 7.

したがって、図２５及び図２６に示すように、上下段両方のチップとも逆ボンディングによってワイヤボンディングが行われて組み立てられたものである。   Therefore, as shown in FIGS. 25 and 26, both the upper and lower chips are assembled by wire bonding by reverse bonding.

なお、１段目の半導体チップ１のワイヤボンディングについては、基板側のボンディングリード３ｈへのワイヤ接続が第１ボンドとなっており、半導体チップ１のパッド１ｃへのワイヤ接続が第２ボンドとなっている。その際、実施の形態１のＣＳＰ７と同様に、それぞれのワイヤ４の一部であるループの頂点４ｂがワイヤ接続部４ａより外側に配置されている。すなわち、各ワイヤ４のループの最上位地点（ここでは４ｂ）がワイヤ接続部４ａのワイヤ引き出し方向の中心線１３より外側に配置されている。   As for the wire bonding of the first-stage semiconductor chip 1, the wire connection to the bonding lead 3h on the substrate side is the first bond, and the wire connection to the pad 1c of the semiconductor chip 1 is the second bond. ing. At that time, similarly to the CSP 7 of the first embodiment, the apex 4b of the loop which is a part of each wire 4 is arranged outside the wire connection portion 4a. That is, the highest point (here 4b) of the loop of each wire 4 is arranged outside the center line 13 in the wire drawing direction of the wire connecting portion 4a.

さらに、２段目の第２の半導体チップ１７のワイヤ接続のうち、図２６に示すように、１段目の半導体チップ１のパッド１ｃと上段（２段目）の第２の半導体チップ１７のパッド１７ｃとを接続する第２ワイヤ（他のワイヤ）１５については、パッド１ｃとパッド１７ｃの距離が短いため、ワイヤ４と同様に、それぞれの第２ワイヤ１５の一部であるループの頂点１５ｂがワイヤ接続部１５ａより外側に配置されている。つまり、各第２ワイヤ１５のループの最上位地点（ここでは１５ｂ）がワイヤ接続部１５ａのワイヤ引き出し方向の中心線１３より外側に配置されている。   Further, in the wire connection of the second-stage second semiconductor chip 17, as shown in FIG. 26, the pad 1c of the first-stage semiconductor chip 1 and the upper (second-stage) second semiconductor chip 17 are connected. As for the second wire (other wire) 15 that connects the pad 17c, the distance between the pad 1c and the pad 17c is short, and thus the vertex 15b of the loop that is a part of each second wire 15 is the same as the wire 4. Is arranged outside the wire connection portion 15a. That is, the highest point (15b in this case) of the loop of each second wire 15 is arranged outside the center line 13 in the wire drawing direction of the wire connecting portion 15a.

なお、２段目の第２の半導体チップ１７のワイヤ接続のうち、図２５に示すように、パッケージ基板３のボンディングリード３ｈと上段（２段目）の第２の半導体チップ１７のパッド１７ｃとを接続する第３ワイヤ１６については、通常の逆ボンディングが行われている。すなわち、パッケージ基板３のボンディングリード３ｈと上段の第２の半導体チップ１７のパッド１７ｃとのワイヤ接続においては、ボンディングリード３ｈとパッド１７ｃの距離が長く、ワイヤ長を長く形成することが可能なため、ワイヤループの形状の安定化を図ることができる。   Of the wire connections of the second semiconductor chip 17 at the second stage, as shown in FIG. 25, the bonding leads 3h of the package substrate 3 and the pads 17c of the second semiconductor chip 17 at the upper stage (second stage) For the third wire 16 connecting the two, ordinary reverse bonding is performed. That is, in the wire connection between the bonding lead 3h of the package substrate 3 and the pad 17c of the upper second semiconductor chip 17, the distance between the bonding lead 3h and the pad 17c is long and the wire length can be formed long. The shape of the wire loop can be stabilized.

したがって、２段目の第２の半導体チップ１７のワイヤ接続では、１段目の半導体チップ１のパッド１ｃと２段目の第２の半導体チップ１７のパッド１７ｃとを接続するワイヤボンディングのみに、第２ワイヤ１５のループの頂点１５ｂがワイヤ接続部１５ａより外側に配置されるようなワイヤ接続を行う。   Therefore, in the wire connection of the second semiconductor chip 17 in the second stage, only the wire bonding for connecting the pad 1c of the first semiconductor chip 1 and the pad 17c of the second semiconductor chip 17 in the second stage, Wire connection is performed such that the apex 15b of the loop of the second wire 15 is arranged outside the wire connection portion 15a.

本実施の形態２のＣＳＰ１４においても、各ワイヤの一部であるループの頂点４ｂ，１５ｂが、それぞれの第１ボンドのワイヤ接続部４ａ，１５ａより外側に配置されていることにより、ワイヤ４及び第２ワイヤ１５が外側に遠回りして引き回されるため、ワイヤ長を長くすることができる。   Also in the CSP 14 of the second embodiment, the vertices 4b and 15b of the loop, which are a part of each wire, are arranged outside the wire connection portions 4a and 15a of the respective first bonds, so that the wires 4 and Since the second wire 15 is routed around the outside, the wire length can be increased.

これにより、ワイヤ４及び第２ワイヤ１５の引き回しのマージンが増えてキャピラリ１８の動く速度にワイヤ送り速度が追従することが可能になり、ワイヤ４及び第２ワイヤ１５それぞれのループ形状の安定化を図ることができる。   As a result, a margin for routing the wire 4 and the second wire 15 is increased, and the wire feed speed can follow the moving speed of the capillary 18, thereby stabilizing the loop shapes of the wire 4 and the second wire 15. Can be planned.

その結果、チップ端部とワイヤ４や第２ワイヤ１５とのショートを低減してワイヤ接続不良の発生を低減することができ、ワイヤ接続不良の抑制化を図ることができる。   As a result, it is possible to reduce the short circuit between the chip end and the wire 4 or the second wire 15 to reduce the occurrence of wire connection failure, and to suppress the wire connection failure.

本実施の形態２のＣＳＰ１４のその他の構造及びその他の効果については、実施の形態１のＣＳＰ７と同様であるため、その重複説明は省略する。   The other structure and other effects of the CSP 14 according to the second embodiment are the same as those of the CSP 7 according to the first embodiment, and a duplicate description thereof is omitted.

以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

例えば、前記実施の形態１及び２では、半導体装置の一例として、ＢＧＡ型の小型の半導体パッケージ（ＣＳＰ７，１４）の場合について説明したが、前記半導体装置は、ＬＧＡ（Land Grid Array)型やＱＦＮ（Quad Flat Non-leaded Package）型のものであってもよい。   For example, in the first and second embodiments, the case of a BGA type small semiconductor package (CSP 7 or 14) is described as an example of the semiconductor device. However, the semiconductor device may be an LGA (Land Grid Array) type or QFN. (Quad Flat Non-leaded Package) type may be used.

また、半導体チップ１や第２の半導体チップ１７の固定については、ダイボンド用フィルム２に限らず、例えば、ペースト状の接着材等を用いて固定してもよい。   Further, the fixing of the semiconductor chip 1 and the second semiconductor chip 17 is not limited to the die-bonding film 2 and may be fixed using, for example, a paste-like adhesive material.

また、ボールマウントの工程については、パッケージ基板３のランド３ｄに半田を塗布した後、リフロー処理により半田バンプ８を形成する方法に限らず、例えば、予めボール形状に形成しておき、ランド３ｄに転写する方法や、マスクを介して半田を印刷する方法を用いてもよい。   Further, the ball mounting process is not limited to the method of forming solder bumps 8 by reflow processing after applying solder to the lands 3d of the package substrate 3. For example, the ball mounting process is performed in advance on the lands 3d. A method of transferring or a method of printing solder through a mask may be used.

本発明は、配線基板を有した電子装置およびその製造技術に好適である。   The present invention is suitable for an electronic device having a wiring board and a manufacturing technique thereof.

１ 半導体チップ
１ａ 主面
１ｂ 裏面
１ｃ パッド（電極）
２ ダイボンド用フィルム
３ パッケージ基板（配線基板）
３ａ 主面
３ｂ 裏面
３ｃ コア材
３ｄ ランド
３ｅ スルーホール
３ｆ ソルダレジスト膜
３ｇ 銅配線
３ｈ ボンディングリード（端子）
３ｉ 開口部
３ｊ 給電線
４ ワイヤ
４ａ ワイヤ接続部
４ｂ ループの頂点
５ 一括封止体
６ 封止体
７ ＣＳＰ（半導体装置）
８ 半田バンプ（外部端子）
９ 多数個取り基板
１０ マーキング
１１ ダイシングブレード
１２ ダイシングテープ
１３ 中心線
１４ ＣＳＰ（半導体装置）
１５ 第２ワイヤ（他のワイヤ）
１５ａ ワイヤ接続部
１５ｂ ループの頂点
１６ 第３ワイヤ
１７ 第２の半導体チップ（他の半導体チップ）
１７ａ 主面
１７ｂ 裏面
１７ｃ パッド（電極）
１８ キャピラリ
１９ 金バンプ
２０ 樹脂成形金型
２０ａ キャビティ
３０ 小型パッケージ DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Main surface 1b Back surface 1c Pad (electrode)
2 Film for die bonding 3 Package substrate (wiring substrate)
3a Main surface 3b Back surface 3c Core material 3d Land 3e Through hole 3f Solder resist film 3g Copper wiring 3h Bonding lead (terminal)
3i Opening 3j Feed line 4 Wire 4a Wire connection 4b Apex of loop 5 Collective sealing body 6 Sealing body 7 CSP (semiconductor device)
8 Solder bump (external terminal)
9 Multiple substrate 10 Marking 11 Dicing blade 12 Dicing tape 13 Center line 14 CSP (semiconductor device)
15 Second wire (other wires)
15a Wire connection part 15b Apex of loop 16 3rd wire 17 2nd semiconductor chip (other semiconductor chips)
17a Main surface 17b Back surface 17c Pad (electrode)
18 Capillary 19 Gold bump 20 Resin mold 20a Cavity 30 Small package

Claims (3)

以下の工程を含むことを特徴とする半導体装置の製造方法：
（ａ）平面形状が矩形状から成る上面、前記上面とは反対側の下面、及び前記上面の上
面辺に沿うように、前記上面に配置された複数の端子を有する配線基板を準備する工程；
（ｂ）平面形状が矩形状から成る第１主面、前記第１主面とは反対側の第１裏面、及び前記第１主面の第１主面辺に沿うように、前記第１主面に配置された複数の第１パッドを有する第１半導体チップを、前記複数の端子から成る端子列よりも前記配線基板の内側に位置し、かつ前記第１裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面に搭載する工程；
（ｃ）平面形状が矩形状から成る第２主面、前記第２主面とは反対側の第２裏面、及び前記第２主面の第２主面辺に沿うように、前記第２主面に配置された複数の第２パッドを有する第２半導体チップを、前記複数の第１パッドから成る端子列よりも前記第１半導体チップの内側に位置し、かつ前記第２裏面が前記第１半導体チップの前記第１主面と対向するように、前記第１半導体チップの前記第１主面に積層する工程；
（ｄ）前記第２半導体チップの前記複数の第２パッドと前記第１半導体チップの前記複数の第１パッドとを複数の第１ワイヤを介して、前記第２半導体チップの前記複数の第２パッドと前記配線基板の前記複数の端子とを複数の第２ワイヤを介して、それぞれ電気的に接続する工程；
（ｅ）前記第１半導体チップ、前記第２半導体チップ、前記複数の第１ワイヤ及び前記複数の第２ワイヤを樹脂で封止することで、前記第２半導体チップの前記第２主面側に位置する表面を有する封止体を形成する工程；
ここで、
前記複数の第１ワイヤのそれぞれは、前記第１ワイヤの第１部分を前記第１半導体チップの前記第１パッドと接続してから、前記第１ワイヤの前記第１部分とは異なる第２部分を前記第２半導体チップの前記第２パッドと接続することで、形成され、
前記複数の第１ワイヤのそれぞれは、前記複数の第１ワイヤのそれぞれの一部が、前記第１ワイヤの前記第１部分より前記第１半導体チップの前記第１主面における前記第１主面辺側に位置するように、形成され、
前記複数の第２ワイヤのそれぞれは、前記複数の第２ワイヤのそれぞれが、前記第２ワイヤのうちの前記配線基板の前記端子と接続される部分より前記配線基板の前記上面における前記上面辺側に配置される部分を有さないように、形成される。 A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing a wiring board having a plurality of terminals arranged on the upper surface so that the upper surface of the upper surface is a rectangular shape, the lower surface opposite to the upper surface, and the upper surface side of the upper surface;
(B) The first main surface so as to be along the first main surface having a rectangular planar shape, the first back surface opposite to the first main surface, and the first main surface side of the first main surface. A first semiconductor chip having a plurality of first pads disposed on a surface thereof is positioned inside the wiring board with respect to a terminal row composed of the plurality of terminals, and the first back surface is connected to the upper surface of the wiring board. Mounting on the upper surface of the wiring board so as to face each other;
(C) The second main surface so as to be along the second main surface having a rectangular planar shape, the second back surface opposite to the second main surface, and the second main surface side of the second main surface. A second semiconductor chip having a plurality of second pads arranged on the surface is located inside the first semiconductor chip with respect to the terminal row composed of the plurality of first pads, and the second back surface is the first semiconductor chip. Stacking the first main surface of the first semiconductor chip so as to face the first main surface of the semiconductor chip;
(D) The plurality of second pads of the second semiconductor chip through the plurality of first wires through the plurality of second pads of the second semiconductor chip and the plurality of first pads of the first semiconductor chip. Electrically connecting the pad and the plurality of terminals of the wiring board via a plurality of second wires, respectively;
(E) sealing the first semiconductor chip, the second semiconductor chip, the plurality of first wires, and the plurality of second wires with a resin so that the second main surface side of the second semiconductor chip is Forming a sealing body having a positioned surface;
here,
Each of the plurality of first wires includes a second portion different from the first portion of the first wire after connecting the first portion of the first wire to the first pad of the first semiconductor chip. Is connected to the second pad of the second semiconductor chip,
Each of the plurality of first wires includes a part of the plurality of first wires, the first main surface of the first main surface of the first semiconductor chip from the first portion of the first wire. Formed to be on the side,
Each of the plurality of second wires is such that each of the plurality of second wires is on the upper surface side of the upper surface of the wiring board from a portion of the second wire connected to the terminal of the wiring board. It is formed so that it does not have a part arrange | positioned. 請求項１記載の半導体装置の製造方法において、
前記（ｄ）工程では、超音波を併用したキャピラリを用いて行うことを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The step (d) is performed using a capillary combined with ultrasonic waves. 平面形状が矩形状から成る上面、前記上面とは反対側の下面、及び前記上面の上面辺に沿うように、前記上面に配置された複数の端子を有する配線基板と、
平面形状が矩形状から成る第１主面、前記第１主面とは反対側の第１裏面、及び前記第１主面の第１主面辺に沿うように、前記第１主面に配置された複数の第１パッドを有し、前記複数の端子から成る端子列よりも前記配線基板の内側に位置し、かつ前記第１裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面に搭載された第１半導体チップと、
平面形状が矩形状から成る第２主面、前記第２主面とは反対側の第２裏面、及び前記第２主面の第２主面辺に沿うように、前記第２主面に配置された複数の第２パッドを有し、前記複数の第１パッドから成る端子列よりも前記第１半導体チップの内側に位置し、かつ前記第２裏面が前記第１半導体チップの前記第１主面と対向するように、前記第１半導体チップの前記第１主面に積層された第２半導体チップと、
前記第２半導体チップの前記複数の第２パッドと前記第１半導体チップの前記複数の第１パッドとをそれぞれ電気的に接続する複数の第１ワイヤと、
前記第２半導体チップの前記複数の第２パッドと前記配線基板の前記複数の端子とをそれぞれ電気的に接続する複数の第２ワイヤと、
前記第２半導体チップの前記第２主面側に位置する表面を有し、前記第１半導体チップ、前記第２半導体チップ、前記複数の第１ワイヤ及び前記複数の第２ワイヤを封止する封止体と、
を含み、
前記複数の第１ワイヤのそれぞれは、前記第１半導体チップの前記複数の第１パッドのそれぞれと接続される第１ワイヤ接続部を有し、
前記複数の第１ワイヤのそれぞれの一部は、前記第１ワイヤ接続部より前記第１半導体チップの前記第１主面における前記第１主面辺側に配置されており、
前記複数の第２ワイヤのそれぞれは、前記配線基板の前記複数の端子のそれぞれと接続される第２ワイヤ接続部を有し、
前記複数の第２ワイヤのそれぞれは、前記第２ワイヤ接続部より前記配線基板の前記上面における前記上面辺側に配置される部分を有していないことを特徴とする半導体装置。 A wiring board having a plurality of terminals arranged on the upper surface so as to be along an upper surface having a rectangular planar shape, a lower surface opposite to the upper surface, and an upper surface side of the upper surface;
A first main surface having a rectangular planar shape, a first back surface opposite to the first main surface, and a first main surface side of the first main surface arranged on the first main surface. The wiring having a plurality of first pads formed, located on the inner side of the wiring board with respect to the terminal row composed of the plurality of terminals, and the first back surface facing the upper surface of the wiring board. A first semiconductor chip mounted on the upper surface of the substrate;
Arranged on the second main surface so as to be along the second main surface having a rectangular planar shape, the second back surface opposite to the second main surface, and the second main surface side of the second main surface. A plurality of second pads that are located on the inner side of the first semiconductor chip with respect to a terminal row composed of the plurality of first pads, and the second back surface is the first main chip of the first semiconductor chip. A second semiconductor chip stacked on the first main surface of the first semiconductor chip so as to face the surface;
A plurality of first wires that electrically connect the plurality of second pads of the second semiconductor chip and the plurality of first pads of the first semiconductor chip, respectively;
A plurality of second wires that respectively electrically connect the plurality of second pads of the second semiconductor chip and the plurality of terminals of the wiring board;
A seal having a surface located on the second main surface side of the second semiconductor chip and sealing the first semiconductor chip, the second semiconductor chip, the plurality of first wires, and the plurality of second wires; A stationary body,
Including
Each of the plurality of first wires has a first wire connection portion connected to each of the plurality of first pads of the first semiconductor chip,
A part of each of the plurality of first wires is arranged on the first main surface side of the first main surface of the first semiconductor chip from the first wire connection portion,
Each of the plurality of second wires has a second wire connection portion connected to each of the plurality of terminals of the wiring board,
Each of the plurality of second wires does not have a portion arranged on the upper surface side of the upper surface of the wiring board from the second wire connection portion.
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