JP4747188B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4747188B2
JP4747188B2 JP2008156464A JP2008156464A JP4747188B2 JP 4747188 B2 JP4747188 B2 JP 4747188B2 JP 2008156464 A JP2008156464 A JP 2008156464A JP 2008156464 A JP2008156464 A JP 2008156464A JP 4747188 B2 JP4747188 B2 JP 4747188B2
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JP
Japan
Prior art keywords
mold
lead frame
lead
semiconductor device
die pad
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Expired - Fee Related
Application number
JP2008156464A
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Japanese (ja)
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JP2008258652A (en
Inventor
富士夫 伊藤
博通 鈴木
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2008156464A priority Critical patent/JP4747188B2/en
Publication of JP2008258652A publication Critical patent/JP2008258652A/en
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Publication of JP4747188B2 publication Critical patent/JP4747188B2/en
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention relates to a manufacturing method of semiconductor device. As a means for promoting the increase of the number of pins in a QFN (Quad Non-leaded package), a semiconductor die mounted on a die pad is arranged at the center of a plastic package, and a plurality of leads made of the same metal as the die pad and die pad supports are arranged around the die pad so as to surround the die pad. Lead tips on one side near the semiconductor die are electrically connected to bonding pads on a main surface of the semiconductor die via gold wires, and lead tips on the other side are ended at a side surface of the plastic package. In order to reduce the length between the semiconductor die and the leads, the lead tips on the one side are extended to positions close to the die pad, and the intervals between adjoining leads on the one side are smaller than those on the other side.

Description

本発明は、半導体装置の製造技術に関し、特に、樹脂封止型半導体装置の多ピン化に適用して有効な技術に関する。   The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to the increase in the number of pins of a resin-sealed semiconductor device.

リードフレームに搭載された半導体チップをモールド樹脂からなる封止体によって封止した樹脂パッケージの一種にＱＦＮ(Quad Flat Non-leaded package)がある。   There is a QFN (Quad Flat Non-leaded package) as a kind of a resin package in which a semiconductor chip mounted on a lead frame is sealed with a sealing body made of a mold resin.

ＱＦＮは、ボンディングワイヤを介して半導体チップと電気的に接続される複数のリードのそれぞれの一端部を封止体の外周部の裏面（下面）から露出させて端子を構成し、前記端子の露出面とは反対側の面、すなわち封止体の内部の端子面にボンディングワイヤを接続して前記端子と半導体チップとを電気的に接続する構造となっている。そして、これらの端子を配線基板の電極（フットプリント）に半田付けすることによって実装される。この構造は、リードがパッケージ（封止体）の側面から横方向に延びて端子を構成するＱＦＰ(Quad Flat Package)に比べて、実装面積が小さくなるという利点を備えている。   The QFN constitutes a terminal by exposing one end portion of each of a plurality of leads electrically connected to the semiconductor chip via a bonding wire from the back surface (lower surface) of the outer peripheral portion of the sealing body. A bonding wire is connected to a surface opposite to the surface, that is, a terminal surface inside the sealing body to electrically connect the terminal and the semiconductor chip. These terminals are mounted by soldering to the electrodes (footprints) of the wiring board. This structure has an advantage that the mounting area is reduced as compared with a QFP (Quad Flat Package) in which the leads extend in the lateral direction from the side surface of the package (sealing body) to form the terminals.

上記ＱＦＮについては、例えば特開２００１−１８９４１０号公報（特許文献１）や特許第３０７２２９１号（特許文献２）などに記載がある。
特開２００１−１８９４１０号公報 特許第３０７２２９１号 About said QFN, Unexamined-Japanese-Patent No. 2001-189410 (patent document 1), patent 3072291 (patent document 2), etc. have description, for example.
JP 2001-189410 A Patent No. 3072291

しかしながら、このようなＱＦＮは、半導体チップに形成されるＬＳＩの高機能化、高性能化に伴って端子数を増加（多ピン化）しようとすると、次のような問題が生じる。   However, such QFN has the following problems when it is attempted to increase the number of terminals (increase the number of pins) as the LSI formed on the semiconductor chip has higher functionality and higher performance.

すなわち、前述したように、ＱＦＮは、封止体の裏面に露出する端子面とは反対側の面にボンディングワイヤを接続するため、端子ピッチとリードのボンディングワイヤ接続箇所のピッチとが同一となる。また、端子面積は、実装時の信頼性を確保するための所定の面積が必要であることから、あまり小さくすることができない。   That is, as described above, since the QFN connects the bonding wires to the surface opposite to the terminal surface exposed on the back surface of the sealing body, the terminal pitch and the pitch of the bonding wire connecting portion of the lead are the same. . Also, the terminal area cannot be made very small because a predetermined area is required to ensure reliability during mounting.

従って、パッケージサイズを変えずに多ピン化を図ろうとした場合、端子数をそれほど増やすことができないので、大幅な多ピン化ができない。他方、パッケージサイズを大きくして多ピン化を図ろうとすると、半導体チップとボンディングワイヤ接続箇所との距離が長くなり、ボンディングワイヤ長が長くなってしまうため、ワイヤボンディング工程や樹脂モールド工程で隣り合ったワイヤ同士がショートするなどの問題が発生し、製造歩留まりが低下してしまう。   Therefore, when trying to increase the number of pins without changing the package size, the number of terminals cannot be increased so much, so that a large number of pins cannot be achieved. On the other hand, if the package size is increased to increase the number of pins, the distance between the semiconductor chip and the bonding wire connecting portion becomes longer and the bonding wire length becomes longer. This causes problems such as short-circuiting between wires, resulting in a decrease in manufacturing yield.

さらに、製造コストを下げる目的で半導体チップをシュリンクした場合も、半導体チップとボンディングワイヤ接続箇所との距離が長くなり、ボンディングワイヤの接続ができなくなる、という問題も発生する。   Further, even when the semiconductor chip is shrunk for the purpose of reducing the manufacturing cost, there arises a problem that the distance between the semiconductor chip and the bonding wire connecting portion becomes long and the bonding wire cannot be connected.

本発明の目的は、ＱＦＮの多ピン化を達成することのできる技術を提供することにある。   An object of the present invention is to provide a technique capable of achieving a multi-pin QFN.

本発明の他の目的は、チップシュリンクに対応したＱＦＮを得ることのできる技術を提供することにある。   Another object of the present invention is to provide a technique capable of obtaining a QFN corresponding to chip shrink.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

本願の一発明である半導体装置の製造方法は、
（ａ）平面形状が四辺形からなり、第１ダイパッド部、および平面視において前記第１ダイパッド部の周囲に配置された複数の第１リードを有する第１パターンと、平面形状が四辺形からなり、第２ダイパッド部、および平面視において前記第２ダイパッド部の周囲に配置された複数の第２リードを有し、かつ前記第１パターンの隣に配置された第２パターンと、平面視において前記第１パターンと前記第２パターンとの間に配置され、かつ前記複数の第１リードおよび前記複数の第２リードと連結する連結部分と、平面視において前記第１パターンおよび前記第２パターンの外側に位置する外枠部分とを備えたリードフレームを準備する工程；
（ｂ）第１金型と、前記第１金型に形成された第１キャビティと、前記第１金型に形成された第２キャビティと、前記第１金型と対向する第２金型とを備えた金型を準備する工程；
（ｃ）前記リードフレームの前記第１および第２ダイパッド部のそれぞれの上面に半導体チップを搭載する工程；
（ｄ）前記（ｃ）工程の後、前記第１金型に形成された前記第１および第２キャビティが前記リードフレームの前記第１および第２パターンにそれぞれ対応し、かつ前記第１および第２ダイパッド部のそれぞれの前記上面に搭載された前記半導体チップが前記第１および前記第２キャビティでそれぞれ覆われるように、前記リードフレームの前記連結部分および前記外枠部分を前記第１金型と前記第２金型とで挟み込み、前記金型に形成されたゲートを介して前記第１キャビティ内に樹脂を注入し、さらに、前記第１キャビティを介して前記第２キャビティ内に前記樹脂を注入し、前記複数の第１および第２リードのそれぞれの一部が露出するように、前記第１および第２パターンを一括して封止する樹脂封止体を成形する工程；
（ｅ）前記（ｄ）工程の後、前記樹脂封止体の一部および前記リードフレームをダイサーで切断することによって、前記樹脂封止体を個片化する工程；
ここで、
前記（ｄ）工程により形成される前記樹脂封止体は、前記第１および第２ダイパッド部のそれぞれの前記上面側に位置する表面と、前記表面とは反対側の裏面を有しており、
前記（ｄ）工程では、前記第１金型に形成され、かつ平面視において前記第１キャビティと前記第２キャビティとの間に設けられ、かつ前記リードフレームを前記第１金型と前記第２金型とで挟み込んだ際、前記リードフレームの前記連結部分のうち、前記連結部分と繋がる前記複数の第１および第２リードのうちの最も端に位置するリードが繋がる第１部分よりも外側の第２部分と平面的に重なる位置に設けられた連通部分を介して、前記第１キャビティから前記第２キャビティに前記樹脂を供給しており、
さらに前記（ｄ）工程では、前記リードフレームの前記連結部分のうち、前記連結部分における前記第２部分以外を前記第１金型と前記第２金型とで挟み込んだ状態で前記第１および前記第２キャビティ内に前記樹脂を注入することで、前記複数の第１および第２リードのそれぞれの前記一部が前記樹脂封止体の前記裏面から露出するように、前記第１および第２パターンを一括して封止する前記樹脂封止体を成形するものである。 A manufacturing method of a semiconductor device which is one invention of the present application is:
(A) The planar shape is a quadrilateral, the first pattern having a first die pad portion, and a plurality of first leads arranged around the first die pad portion in plan view, and the planar shape is a quadrilateral. The second die pad section, and a second pattern disposed around the second die pad section in plan view, and disposed next to the first pattern, and in plan view A connecting portion disposed between the first pattern and the second pattern and connected to the plurality of first leads and the plurality of second leads; and the outside of the first pattern and the second pattern in plan view Providing a lead frame with an outer frame portion located at a position ;
(B) a first mold, a first cavity formed in the first mold, a second cavity formed in the first mold, and a second mold facing the first mold. Preparing a mold comprising:
( C ) mounting a semiconductor chip on each upper surface of the first and second die pad portions of the lead frame ;
( D) After the step (c), the first and second cavities formed in the first mold correspond to the first and second patterns of the lead frame, respectively, and the first and second cavities The connecting portion and the outer frame portion of the lead frame are connected to the first mold so that the semiconductor chips mounted on the upper surfaces of the two die pad portions are respectively covered with the first and second cavities. sandwiched between the second mold, the resin is injected into the first cavity through a gate formed in the mold, further, injecting the resin into the second cavity through said first cavity And molding a resin sealing body that collectively seals the first and second patterns so that a part of each of the plurality of first and second leads is exposed ;
(E) after step (d), by cutting a portion and the lead frame of the resin sealing body with a dicer, the step of singulating the resin sealing body;
here,
The resin sealing body formed by the step (d) has a surface located on the upper surface side of each of the first and second die pad portions, and a back surface opposite to the surface,
In the step (d), the lead mold is formed in the first mold and provided between the first cavity and the second cavity in a plan view, and the lead frame is formed between the first mold and the second mold. Out of the connecting portions of the lead frame, the outermost lead of the plurality of first and second leads connected to the connecting portion is connected to the outermost portion of the lead frame when the lead is positioned between the leads. The resin is supplied from the first cavity to the second cavity via a communication portion provided at a position overlapping the second portion in a plane,
Further, in the step (d), the first and the second molds are sandwiched between the first mold and the second mold except for the second part of the connection part among the connection parts of the lead frame. By injecting the resin into the second cavity, the first and second patterns are formed such that the portions of the plurality of first and second leads are exposed from the back surface of the resin sealing body. The resin sealing body that collectively seals is molded .

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。   Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

本願の一発明である半導体装置の製造方法によれば、半導体チップの周囲に配置された複数のリードのそれぞれの一端部側をダイパッド部の近傍まで引き回すことにより、リードとボンディングパッドを結線するワイヤの長さを短くすることができるので、多ピン化に伴ってリードのピッチ、すなわちワイヤの間隔が狭くなった場合でも、製造工程の途中でワイヤ同士が短絡する不良の発生を抑制することが可能となり、ＱＦＮの多ピン化を推進することができる。   According to the method of manufacturing a semiconductor device according to one aspect of the present application, a wire that connects the lead and the bonding pad by drawing one end portion of each of the plurality of leads arranged around the semiconductor chip to the vicinity of the die pad portion. The length of the wire can be shortened, so that even when the lead pitch, that is, the distance between the wires becomes narrower as the number of pins increases, the occurrence of defects in which the wires are short-circuited during the manufacturing process can be suppressed. This makes it possible to promote the increase in the number of QFN pins.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、特に必要なときを除き、同一または同様な部分の説明を原則として繰り返さない。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

（実施の形態１）
図１は、本実施の形態のＱＦＮの外観（表面側）を示す平面図、図２は、ＱＦＮの外観（裏面側）を示す平面図、図３は、ＱＦＮの内部構造（表面側）を示す平面図、図４は、ＱＦＮの内部構造（裏面側）を示す平面図、図５は、ＱＦＮの断面図である。 (Embodiment 1)
FIG. 1 is a plan view showing the appearance (front side) of the QFN of the present embodiment, FIG. 2 is a plan view showing the appearance (back side) of the QFN, and FIG. 3 shows the internal structure (front side) of the QFN. FIG. 4 is a plan view showing the internal structure (back side) of the QFN, and FIG. 5 is a cross-sectional view of the QFN.

本実施の形態のＱＦＮ１は、１個の半導体チップ２を封止体３によって封止した表面実装型のパッケージ構造を有しており、その外形寸法は、例えば縦×横＝１２ｍｍ×１２ｍｍ、厚さ＝１．０ｍｍである。   The QFN 1 of the present embodiment has a surface-mount type package structure in which one semiconductor chip 2 is sealed with a sealing body 3, and the outer dimensions thereof are, for example, length × width = 12 mm × 12 mm, thickness The length is 1.0 mm.

上記半導体チップ２は、金属製のダイパッド部４上に搭載された状態で封止体３の中央部に配置されている。この半導体チップ２の一辺のサイズは、例えば４ｍｍである。上記ダイパッド部４は、例えば一辺のサイズが４ｍｍ〜７ｍｍの範囲内にある複数種類の半導体チップ２を搭載可能とするために、その径を半導体チップ２の径よりも小さくした、いわゆる小タブ構造になっており、本実施形態では、３ｍｍの径を有している。ダイパッド部４は、これと一体に形成され、封止体３の四隅に延在する４本の吊りリード５ｂによって支持されている。   The semiconductor chip 2 is disposed at the center of the sealing body 3 in a state of being mounted on the metal die pad portion 4. The size of one side of the semiconductor chip 2 is, for example, 4 mm. The die pad portion 4 has a so-called small tab structure in which the diameter is smaller than the diameter of the semiconductor chip 2 so that a plurality of types of semiconductor chips 2 having a side size in the range of 4 mm to 7 mm can be mounted. In this embodiment, it has a diameter of 3 mm. The die pad portion 4 is formed integrally with the die pad portion 4 and is supported by four suspension leads 5 b extending at the four corners of the sealing body 3.

上記ダイパッド部４の周囲には、ダイパッド部４および吊りリード５ｂと同一の金属からなる複数本（例えば１１６本）のリード５がダイパッド部４を囲むように配置されている。これらのリード５の一端部側（半導体チップ２に近い側）５ａは、Ａｕワイヤ６を介して半導体チップ２の主面のボンディングパッド７と電気的に接続されており、それとは反対側の他端部側５ｃは、封止体３の側面で終端している。   Around the die pad portion 4, a plurality of (for example, 116) leads 5 made of the same metal as the die pad portion 4 and the suspension lead 5 b are disposed so as to surround the die pad portion 4. One end side (side closer to the semiconductor chip 2) 5a of these leads 5 is electrically connected to the bonding pad 7 on the main surface of the semiconductor chip 2 via the Au wire 6, and the other side opposite to that The end portion side 5 c is terminated at the side surface of the sealing body 3.

上記リード５のそれぞれは、半導体チップ２との距離を短くするために、一端部側５ａがダイパッド部４の近傍まで引き回され、その先端のピッチ（Ｐ３）は狭ピッチ（０．１８ｍｍ〜０．２ｍｍ）となっている。このため、隣接するリード５とのピッチは、一端部側５ａの方が他端部側５ｃよりも小さくなっている。リード５の形状をこのようにすることにより、リード５の一端部側５ａとボンディングパッド７を結線するＡｕワイヤ６の長さを短く（本実施形態では３ｍｍ以下）することができるので、多ピン化した場合でも、また多ピン化に伴ってリード５のピッチ、すなわちＡｕワイヤ６の間隔が狭くなった場合でも、ＱＦＮ１の製造工程（例えば、ワイヤボンディング工程や樹脂モールド工程）でＡｕワイヤ６同士が短絡する不良の発生を抑制することができる。 In order to shorten the distance from the semiconductor chip 2, each of the leads 5 has one end side 5 a routed to the vicinity of the die pad portion 4, and the tip pitch (P 3 ) is narrow (0.18 mm to 0.18 mm). 0.2 mm). For this reason, the pitch between the adjacent leads 5 is smaller on the one end side 5a than on the other end side 5c. By making the shape of the lead 5 in this way, the length of the Au wire 6 connecting the one end portion side 5a of the lead 5 and the bonding pad 7 can be shortened (3 mm or less in this embodiment). Even when the number of pins is increased and the pitch of the leads 5, that is, the interval between the Au wires 6 is reduced due to the increase in the number of pins, the Au wires 6 are manufactured in the QFN 1 manufacturing process (for example, a wire bonding process or a resin molding process). Can suppress the occurrence of a short circuit.

図２に示すように、ＱＦＮ１の裏面（基板実装面）には、複数個（例えば１１６個）の外部接続用端子８が設けられている。これらの端子８は、封止体３の各辺に沿って千鳥状に２列ずつ配置され、それぞれの端子８の先端部分は、封止体３の裏面から露出し、かつ外側に突出している。端子８の径（ｄ）は、０．３ｍｍであり、隣接する端子８とのピッチは、同一列の端子８とのピッチ（Ｐ１）が０．６５ｍｍ、他の列の端子とのピッチ（Ｐ２）が０．３２５ｍｍである。 As shown in FIG. 2, a plurality of (for example, 116) external connection terminals 8 are provided on the back surface (substrate mounting surface) of the QFN 1. These terminals 8 are arranged in two rows in a staggered manner along each side of the sealing body 3, and the tip portions of the terminals 8 are exposed from the back surface of the sealing body 3 and protrude outward. . The diameter (d) of the terminal 8 is 0.3 mm, and the pitch with the adjacent terminal 8 is 0.65 mm with respect to the terminal 8 in the same row (P 1 ), and the pitch with the terminal in the other row ( P 2 ) is 0.325 mm.

本実施形態の端子８は、リード５と一体に形成されており、端子８の厚さは、１２５μｍ〜１５０μｍ程度である。また、リード５の端子８以外の部分、すなわち一端部側５ａや他端部側５ｃなどの厚さは６５μｍ〜７５μｍ程度である。また、封止体３の外側に突出した端子８の先端部分には、メッキ法あるいは印刷法によって半田層９が被着されている。本実施形態のＱＦＮ１は、これらの端子８を配線基板の電極（フットプリント）に半田付けすることによって実装される。   The terminal 8 of this embodiment is formed integrally with the lead 5, and the thickness of the terminal 8 is about 125 μm to 150 μm. Further, the thickness of the portion other than the terminal 8 of the lead 5, that is, the one end side 5 a and the other end side 5 c is about 65 μm to 75 μm. A solder layer 9 is applied to the tip of the terminal 8 protruding outside the sealing body 3 by a plating method or a printing method. The QFN 1 of this embodiment is mounted by soldering these terminals 8 to the electrodes (footprints) of the wiring board.

次に、上記ＱＦＮ１の製造方法を説明する。最初に、図６に示すようなリードフレームＬＦ１を用意する。このリードフレームＬＦ１は、Ｃｕ、Ｃｕ合金またはＦｅ−Ｎｉ合金などの金属板からなり、前述したダイパッド部４、リード５、吊りリード５ｂなどのパターンが縦および横方向に繰り返し形成された構成になっている。すなわち、リードフレームＬＦ１は、複数個（例えば２４個）の半導体チップ２を搭載する多連構造になっている。 Next, a method for manufacturing the QFN 1 will be described. First, a lead frame LF 1 as shown in FIG. 6 is prepared. The lead frame LF 1 is made of a metal plate such as Cu, Cu alloy, or Fe—Ni alloy, and has a configuration in which the patterns such as the die pad portion 4, the lead 5, and the suspension lead 5 b are repeatedly formed in the vertical and horizontal directions. It has become. That is, the lead frame LF 1 has a multiple structure on which a plurality (for example, 24) of semiconductor chips 2 are mounted.

上記リードフレームＬＦ１を製造するには、図７に示すような板厚１２５μｍ〜１５０μｍ程度のＣｕ、Ｃｕ合金またはＦｅ−Ｎｉ合金などからなる金属板１０を用意し、ダイパッド部４、リード５および吊りリード５ｂを形成する箇所の片面をフォトレジスト膜１１で被覆する。また、外部接続用の端子８を形成する箇所は、両面をフォトレジスト膜１１で被覆する。そして、この状態で金属板１０を薬液によってエッチングし、片面がフォトレジスト膜１１で被覆された領域の金属板１０の板厚を半分程度（６５μｍ〜７５μｍ）まで薄くする（ハーフエッチング）。このような方法でエッチングを行うことにより、両面共にフォトレジスト膜１１で被覆されていない領域の金属板１０は完全に消失し、片面がフォトレジスト膜１１で被覆された領域に厚さ６５μｍ〜７５μｍ程度のダイパッド部４、リード５および吊りリード５ｂが形成される。また、両面がフォトレジスト膜１１で被覆された領域の金属板１０は薬液によってエッチングされないので、エッチング前と同じ厚さ（１２５μｍ〜１５０μｍ程度）を有する突起状の端子８が形成される。 In order to manufacture the lead frame LF 1 , a metal plate 10 made of Cu, Cu alloy, Fe—Ni alloy or the like having a plate thickness of about 125 μm to 150 μm as shown in FIG. One side of the portion where the suspension lead 5 b is formed is covered with the photoresist film 11. Further, both sides of the portion where the external connection terminal 8 is formed are covered with the photoresist film 11. In this state, the metal plate 10 is etched with a chemical solution, and the thickness of the metal plate 10 in the region where one side is covered with the photoresist film 11 is reduced to about half (65 μm to 75 μm) (half etching). By performing etching in such a manner, the metal plate 10 in the region not covered with the photoresist film 11 on both sides disappears completely, and a thickness of 65 μm to 75 μm is formed in the region covered on one side with the photoresist film 11. A die pad portion 4, a lead 5 and a suspension lead 5b are formed. Further, since the metal plate 10 in the region where both surfaces are covered with the photoresist film 11 is not etched by the chemical solution, the protruding terminals 8 having the same thickness (about 125 μm to 150 μm) as before the etching are formed.

次に、フォトレジスト膜１１を除去し、続いてリード５の一端部側５ａの表面にＡｇメッキを施すことによって、前記図６に示したリードフレームＬＦ１が完成する。なお、リード５の一端部側５ａにＡｇメッキを施す手段に代えて、リードフレームＬＦ１の全面にＰｄ（パラジウム）メッキを施してもよい。Ｐｄメッキは、Ａｇメッキに比べてメッキ層の膜厚が薄いので、リード５とＡｕワイヤ６の接合性を向上させることができる。また、リードフレームＬＦ１の全面にメッキを施すことにより、端子８の表面にも同時にメッキ層が形成されるので、メッキ工程を短縮することができる。 Then, removal of the photoresist 11, followed by applying a Ag plating on the surface of one end portion 5a of the lead 5, the lead frame LF 1 is completed as shown in FIG. 6. Instead of the means for applying the Ag plating at one end 5a of the lead 5 may be subjected to Pd (palladium) plating on the entire surface of the lead frame LF 1. Since Pd plating has a thinner plating layer than Ag plating, the bondability between the lead 5 and the Au wire 6 can be improved. Further, by plating the entire surface of the lead frame LF 1, a plating layer is simultaneously formed on the surface of the terminal 8, so that the plating process can be shortened.

このように、リードフレームＬＦ１の母材となる金属板１０の一部の片面をフォトレジスト膜１１で被覆してハーフエッチングを施し、リード５の板厚を金属板１０の半分程度まで薄くすることにより、一端部側５ａのピッチが極めて狭い（本実施形態では０．１８ｍｍ〜０．２ｍｍピッチ）リード５を精度よく加工することができる。また、金属板１０の一部の両面をフォトレジスト膜１１で被覆することにより、ダイパッド部４、リード５および吊りリード５ｂの形成と同時に端子８を形成することができる。 In this way, a part of one side of the metal plate 10 which is the base material of the lead frame LF 1 is covered with the photoresist film 11 and half-etched to reduce the thickness of the lead 5 to about half of the metal plate 10. Thus, the lead 5 having a very narrow pitch on the one end side 5a (0.18 mm to 0.2 mm pitch in this embodiment) can be processed with high accuracy. Further, by covering a part of both surfaces of the metal plate 10 with the photoresist film 11, the terminals 8 can be formed simultaneously with the formation of the die pad portion 4, the lead 5 and the suspension lead 5b.

次に、上記のようなリードフレームＬＦ１を使ってＱＦＮ１を製造するには、まず図８および図９に示すように、半導体チップ２の素子形成面を上に向けてダイパッド部４上に搭載し、Ａｕペーストやエポキシ樹脂系の接着剤を使って両者を接着する。 Next, in order to manufacture the QFN 1 using the lead frame LF 1 as described above, first, as shown in FIGS. 8 and 9, the semiconductor chip 2 is mounted on the die pad portion 4 with the element formation surface facing upward. Then, the two are bonded using Au paste or epoxy resin adhesive.

上記作業を行うときは、図９に示すように、リードフレームＬＦ１の裏面側に突起状の端子８が位置するので、リードフレームＬＦ１を支持する治具３０Ａの端子８と対向する箇所に溝３１を形成しておくとよい。このようにすると、リードフレームＬＦ１を安定して支持することができるので、ダイパッド部４上に半導体チップ２を搭載する際にリードフレームＬＦ１が変形したり、ダイパッド部４と半導体チップ２の位置がずれたりする不具合を防ぐことができる。 When performing the above operations, as shown in FIG. 9, since the protruding terminal 8 on the back side of the lead frame LF 1 is positioned, at a position opposed to the terminal 8 of the jig 30A for supporting the lead frame LF 1 The groove 31 is preferably formed in advance. In this way, since the lead frame LF 1 can be stably supported, when the semiconductor chip 2 is mounted on the die pad portion 4, the lead frame LF 1 is deformed, or the die pad portion 4 and the semiconductor chip 2 It is possible to prevent a problem that the position is shifted.

また、本実施形態のＱＦＮ１は、半導体チップ２を金型に装着して樹脂モールドを行う際、半導体チップ２の上面側と下面側の樹脂の流れを均一化するために、吊りリード５ｂの一部を折り曲げることによってダイパッド部４をリード５よりも高い位置に配置するタブ上げ構造としている。従って、図９に示すように、治具３０Ａのダイパッド部４と対向する箇所に突起３２を形成することにより、リードフレームＬＦ１を安定して支持することができるので、ダイパッド部４上に半導体チップ２を搭載する際にリードフレームＬＦ１が変形したり、ダイパッド部４と半導体チップ２の位置がずれたりする不具合を防ぐことができる。 Further, the QFN 1 of the present embodiment is provided with one of the suspension leads 5b in order to make the resin flow on the upper surface side and the lower surface side of the semiconductor chip 2 uniform when the semiconductor chip 2 is mounted on the mold and resin molding is performed. A tab raising structure is provided in which the die pad portion 4 is disposed at a position higher than the lead 5 by bending the portion. Therefore, as shown in FIG. 9, the lead frame LF 1 can be stably supported by forming the protrusion 32 at a location facing the die pad portion 4 of the jig 30 </ b> A. When the chip 2 is mounted, it is possible to prevent a problem that the lead frame LF 1 is deformed or the positions of the die pad portion 4 and the semiconductor chip 2 are shifted.

次に、図１０および図１１に示すように、周知のボールボンディング装置を使って半導体チップ２のボンディングパッド７とリード５の一端部側５ａとの間をＡｕワイヤ６で結線する。この場合も図１１に示すように、リードフレームＬＦ１を支持する治具３０Ｂの端子８と対応する箇所に溝３１を形成したり、ダイパッド部４と対応する箇所に突起３２を形成したりしておくことにより、リードフレームＬＦ１を安定して支持することができるので、Ａｕワイヤ６とリード５の位置ずれや、Ａｕワイヤ６とボンディングパッド７の位置ずれを防ぐことができる。 Next, as shown in FIGS. 10 and 11, the Au pad 6 is used to connect the bonding pad 7 of the semiconductor chip 2 and the one end portion side 5 a of the lead 5 using a known ball bonding apparatus. In this case also, as shown in FIG. 11, or a groove 31 at a position corresponding to the terminal 8 of the jig 30B for supporting the lead frame LF 1, or by forming a protrusion 32 at a position corresponding to the die pad 4 As a result, the lead frame LF 1 can be stably supported, so that the positional deviation between the Au wire 6 and the lead 5 and the positional deviation between the Au wire 6 and the bonding pad 7 can be prevented.

次に、上記リードフレームＬＦ１を図１２に示す金型４０に装着して半導体チップ２を樹脂封止する。図１２は、金型４０の一部（ＱＦＮ約１個分の領域）を示す断面図である。 Next, the semiconductor chip 2 is sealed with resin attached to the mold 40 representing the lead frame LF 1 in Figure 12. FIG. 12 is a cross-sectional view showing a part of the mold 40 (a region corresponding to about one QFN).

この金型４０を使って半導体チップ２を樹脂封止する際には、まず下型４０Ｂの表面に薄い樹脂シート４１を敷き、この樹脂シート４１の上にリードフレームＬＦ１を載置する。リードフレームＬＦ１は、突起状の端子８が形成された面を下に向けて載置し、端子８と樹脂シート４１とを接触させる。そしてこの状態で、樹脂シート４１とリードフレームＬＦ１を上型４０Ａと下型４０Ｂで挟み付ける。このようにすると、図に示すように、リード５の下面に位置する端子８が金型４０（上型４０Ａおよび下型４０Ｂ）の押圧力によって樹脂シート４１を押さえ付けるので、その先端部分が樹脂シート４１の中に食い込む。 The semiconductor chip 2 with the mold 40 in the resin sealing is laid a thin resin sheet 41 on the surface of the lower die 40B First, placing the lead frame LF 1 on the resin sheet 41. The lead frame LF 1 is placed with the surface on which the protruding terminals 8 are formed facing downward, and the terminals 8 and the resin sheet 41 are brought into contact with each other. In this state, it pinched the resin sheet 41 and the lead frame LF 1 in the upper die 40A and the lower die 40B. In this case, as shown in the figure, the terminal 8 located on the lower surface of the lead 5 presses the resin sheet 41 by the pressing force of the mold 40 (upper mold 40A and lower mold 40B), and the tip portion thereof is resin. Cut into the sheet 41.

この結果、図１３に示すように、上型４０Ａと下型４０Ｂの隙間（キャビティ）に溶融樹脂を注入してモールド樹脂を成型することによって封止体３を形成した後、上型４０Ａと下型４０Ｂを分離すると、樹脂シート４１の中に食い込んでいた端子８の先端部分が封止体３の裏面から外側に突出する。   As a result, as shown in FIG. 13, after forming the sealing body 3 by injecting molten resin into the gap (cavity) between the upper mold 40A and the lower mold 40B and molding the mold resin, the upper mold 40A and the lower mold 40A are formed. When the mold 40 </ b> B is separated, the tip portion of the terminal 8 that has bitten into the resin sheet 41 protrudes outward from the back surface of the sealing body 3.

なお、リードフレームＬＦ１の上面を上型４０Ａで押さえ付けると、リードフレームＬＦ１を構成する金属板のバネ力によって、リード５の先端側である一端部側５ａに上向きの力が作用する。そのため、本実施形態のリードフレームＬＦ１のように、端子８を２列に配置した場合は、リード５の一端部側５ａに近い方に端子８が形成されたリード５と、一端部側５ａから離れた方に端子８が形成されたリード５では、端子８が樹脂シート４１を押さえ付ける力に差が生じる。すなわち、一端部側５ａに近い方に形成された端子８は、一端部５ａから離れた方（＝上型４０Ａとリード５の接触部分に近い方）に形成された端子８に比べて樹脂シート４１を押さえる力が弱くなる。この結果、一端部側５ａに近い方に形成された端子８と、一端部側５ａから離れた方に形成された端子８は、封止体３の裏面から外側に突出する高さに差が生じ、これらの端子８を配線基板の電極（フットプリント）上に半田付けした際に、一部の端子８と電極との間が非接触になるオープン不良が発生する虞れがある。 Incidentally, when pressing the upper surface of the lead frame LF 1 above type 40A, by the spring force of the metal plate constituting the lead frame LF 1, one end 5a to the upward force is the tip side of the lead 5 is applied. Therefore, when the terminals 8 are arranged in two rows as in the lead frame LF 1 of the present embodiment, the lead 5 in which the terminal 8 is formed closer to the one end side 5a of the lead 5 and the one end side 5a. In the lead 5 in which the terminal 8 is formed away from the terminal, a difference occurs in the force with which the terminal 8 presses the resin sheet 41. That is, the terminal 8 formed closer to the one end side 5a is a resin sheet than the terminal 8 formed farther from the one end 5a (= the closer to the contact portion between the upper die 40A and the lead 5). The force to hold 41 is weakened. As a result, the terminal 8 formed closer to the one end side 5a and the terminal 8 formed farther from the one end side 5a have a difference in height protruding outward from the back surface of the sealing body 3. As a result, when these terminals 8 are soldered onto the electrodes (footprints) of the wiring board, there is a possibility that an open defect that causes non-contact between some of the terminals 8 and the electrodes may occur.

このような虞れがある場合は、図１４に示すように、一端部側５ａに近い方に端子８が形成されたリード５の幅（Ｗ１）を、一端部側５ａから離れた方に端子８が形成されたリード５の幅（Ｗ２）よりも広くする（Ｗ２＜Ｗ１）とよい。このようにすると、端子８が樹脂シート４１を押さえ付ける力がすべてのリード５でほぼ同じになるので、樹脂シート４１の中に食い込む端子８の量、すなわち封止体３の裏面から外側に突出する端子８の先端部分の高さは、すべてのリード５でほぼ同じになる。 When there is such a fear, as shown in FIG. 14, the width (W 1 ) of the lead 5 in which the terminal 8 is formed closer to the one end side 5a is set to be away from the one end side 5a. The width (W 2 ) of the lead 5 on which the terminal 8 is formed may be wider (W 2 <W 1 ). In this case, since the force with which the terminal 8 presses the resin sheet 41 becomes substantially the same for all the leads 5, the amount of the terminal 8 that bites into the resin sheet 41, that is, protrudes outward from the back surface of the sealing body 3. The height of the tip end portion of the terminal 8 is almost the same for all the leads 5.

また、前述したように、本実施の形態で使用するリードフレームＬＦ１は、ハーフエッチングによってパターン（ダイパッド部４、リード５、吊りリード５ｂなど）を形成するので、リード５の板厚が通常のリードフレームの半分程度まで薄くなっている。そのため、金型４０（上型４０Ａおよび下型４０Ｂ）がリードフレームＬＦ１を押圧する力は、通常のリードフレームを使用した場合に比べて弱くなるので、端子８が樹脂シート４１を押さえ付ける力が弱くなる結果、封止体３の外側に突出する高さが低くなる。 Further, as described above, the lead frame LF 1 used in the present embodiment forms a pattern (die pad portion 4, lead 5, suspension lead 5b, etc.) by half etching, so that the thickness of the lead 5 is normal. It is as thin as about half of the lead frame. Therefore, the force the mold 40 (upper die 40A and the lower mold 40B) presses the lead frame LF 1, since weaker as compared with the case of using the conventional lead frame, terminals 8 presses the resin sheet 41 forces As a result, the height protruding outside the sealing body 3 is reduced.

そこで、封止体３の外側に突出する端子８の高さを大きくしたい場合は、図１５に示すように、上型４０Ａと接触する部分（図の○印で囲んだ部分）のリードフレームＬＦ１をハーフエッチングせず、端子８と同じ厚さにしておくとよい。 Therefore, when it is desired to increase the height of the terminal 8 projecting outside the sealing body 3, as shown in FIG. 15, the lead frame LF of the portion (the portion surrounded by a circle in the figure) in contact with the upper mold 40A 1 is preferably half-etched and has the same thickness as the terminal 8.

図１６は、上記金型４０の上型４０ＡがリードフレームＬＦ１と接触する部分を斜線で示した平面図である。また、図１７は、この金型４０のゲートの位置と、キャビティに注入された樹脂の流れる方向を模式的に示した平面図である。 FIG. 16 is a plan view showing the portion where the upper die 40A of the die 40 is in contact with the lead frame LF 1 by hatching. FIG. 17 is a plan view schematically showing the position of the gate of the mold 40 and the flow direction of the resin injected into the cavity.

図１６に示すように、上記金型４０は、リードフレームＬＦ１の外枠部分、およびリード５とリード５の連結部分のみが上型４０Ａと接触し、それ以外の全ての領域は、樹脂が注入されるキャビティとして有効に利用される構造になっている。 As shown in FIG. 16, in the die 40, only the outer frame portion of the lead frame LF 1 and the connecting portion between the lead 5 and the lead 5 are in contact with the upper die 40A, and all other regions are made of resin. The structure is effectively used as a cavity to be injected.

また、図１７に示すように、上記金型４０の一辺には複数のゲートＧ１〜Ｇ１６が設けられており、例えば図の左端の縦方向に並んだ３つのキャビティＣ１〜Ｃ３には、ゲートＧ１、Ｇ２を通じて樹脂が注入され、これらに隣接する３つのキャビティＣ４〜Ｃ６には、ゲートＧ３、Ｇ４を通じて樹脂が注入される構造になっている。一方、上記ゲートＧ１〜Ｇ１６と対向する他の一辺には、ダミーキャビティＤＣ１〜ＤＣ８およびエアベント４２が設けられており、例えばゲートＧ１、Ｇ２を通じてキャビティＣ１〜Ｃ３に樹脂が注入されると、キャビティＣ１〜Ｃ３内のエアーがダミーキャビティＤＣ１に流入し、キャビティＣ３内の樹脂にボイドが生じるのを防止する構造になっている。 Further, as shown in FIG. 17, a plurality of gates G 1 to G 16 are provided on one side of the mold 40, for example, in three cavities C 1 to C 3 arranged in the vertical direction at the left end of the figure. The resin is injected through the gates G 1 and G 2 , and the resin is injected into the three cavities C 4 to C 6 adjacent to these through the gates G 3 and G 4 . On the other hand, dummy cavities DC 1 to DC 8 and an air vent 42 are provided on the other side facing the gates G 1 to G 16. For example, resin is provided in the cavities C 1 to C 3 through the gates G 1 and G 2. Is injected, air in the cavities C 1 to C 3 flows into the dummy cavity DC 1 , thereby preventing voids from occurring in the resin in the cavity C 3 .

図１８は、上記キャビティＣ１〜Ｃ１８に樹脂を注入してモールド樹脂を成型することにより封止体３を成形した後、金型４０から取り外したリードフレームＬＦ１の平面図、図１９は、図１８のＸ−Ｘ’線に沿った断面図、図２０は、リードフレームＬＦ１の裏面側の平面図である。 18 is a plan view of the lead frame LF 1 removed from the mold 40 after molding the sealing body 3 by injecting resin into the cavities C 1 to C 18 and molding the mold resin. FIG. , cross-sectional view taken along line X-X 'in FIG. 18, FIG. 20 is a plan view of the back side of the lead frame LF 1.

次に、リードフレームＬＦ１の裏面に露出した端子８の表面に半田層（９）を形成し、続いて封止体３の表面に製品名などのマークを印刷した後、図１８に示すダイシングラインＬに沿ってリードフレームＬＦ１およびモールド樹脂の一部を切断することにより、前記図１〜図５に示した本実施形態のＱＦＮ１が２４個完成する。なお、ＱＦＮ１を配線基板に実装する際、ＱＦＮ１と配線基板との隙間を大きくしたい場合、すなわちＱＦＮ１のスタンドオフ量を大きくしたい場合は、端子８の表面に形成する半田層９の膜厚を５０μｍ程度まで厚くする。このような厚い膜厚の半田層９を形成するには、例えばメタルマスクを用いて端子８の表面に半田ペーストを印刷する方法を用いる。 Then, after printing a mark such as a product name on the surface of the terminal 8 exposed on the back surface of the lead frame LF 1 to form a solder layer (9), followed by the surface of the sealing body 3, dicing shown in FIG. 18 by cutting a portion of the lead frame LF 1 and the molding resin along the line L, QFN 1 of the present embodiment shown in FIG. 1 to FIG. 5 is completed 24. When mounting the QFN 1 on the wiring board, if the gap between the QFN 1 and the wiring board is to be increased, that is, if it is desired to increase the stand-off amount of the QFN 1, the film thickness of the solder layer 9 formed on the surface of the terminal 8 is 50 μm. Thicken to the extent. In order to form such a thick solder layer 9, for example, a method of printing a solder paste on the surface of the terminal 8 using a metal mask is used.

このように、本実施の形態のＱＦＮ１は、リード５の一端部側５ａをダイパッド部４の近傍まで引き回しているので、一端部側５ａと半導体チップ２との間の距離を短くすることができ、それら接続するＡｕワイヤ６の長さも短くすることができる。また、端子８を千鳥状に配置してもリード５の一端部側５ａの長さはほぼ等しいので、一端部側５ａの先端が半導体チップ２の各辺に対してほぼ一列に並ぶ。従って、リード５の一端部側５ａと半導体チップ２とを接続するＡｕワイヤ６の長さをほぼ均等にすることができると共に、Ａｕワイヤ６のループ形状もほぼ均等にすることができる。   As described above, since the QFN 1 of the present embodiment extends the one end portion side 5a of the lead 5 to the vicinity of the die pad portion 4, the distance between the one end portion side 5a and the semiconductor chip 2 can be shortened. The lengths of the Au wires 6 to be connected can be shortened. Even if the terminals 8 are arranged in a staggered manner, the lengths of the one end portions 5 a of the leads 5 are substantially equal, so that the tips of the one end portions 5 a are arranged in a line with respect to each side of the semiconductor chip 2. Therefore, the length of the Au wire 6 that connects the one end side 5a of the lead 5 and the semiconductor chip 2 can be made substantially uniform, and the loop shape of the Au wire 6 can also be made almost uniform.

これにより、隣接するＡｕワイヤ６同士が短絡したり、特に半導体チップ２の四隅近傍でＡｕワイヤ６同士が交差したりする不具合が生じないので、ワイヤボンディングの作業性が向上する。また、隣接するＡｕワイヤ６間のピッチを狭くすることができるので、ＱＦＮ１の多ピン化を実現することができる。   As a result, there is no inconvenience that adjacent Au wires 6 are short-circuited or Au wires 6 cross each other in the vicinity of the four corners of the semiconductor chip 2, so that the workability of wire bonding is improved. In addition, since the pitch between adjacent Au wires 6 can be narrowed, it is possible to realize a multi-pin QFN1.

また、リード５の一端部側５ａをダイパッド部４の近傍まで引き回したことにより、端子８からリード５の一端部側５ａまでの距離が長くなる。これにより、封止体３の外部に露出した端子８を通じて封止体３の内部に浸入する水分が半導体チップ２に到達し難くなるので、水分によるボンディングパッド７の腐食を防止することができ、ＱＦＮ１の信頼性が向上する。   Further, since the one end side 5 a of the lead 5 is routed to the vicinity of the die pad portion 4, the distance from the terminal 8 to the one end side 5 a of the lead 5 is increased. This makes it difficult for moisture entering the inside of the sealing body 3 through the terminals 8 exposed to the outside of the sealing body 3 to reach the semiconductor chip 2, so that corrosion of the bonding pad 7 due to moisture can be prevented. The reliability of QFN1 is improved.

また、リード５の一端部側５ａをダイパッド部４の近傍まで引き回すことにより、半導体チップ２をシュリンクしてもＡｕワイヤ６の長さの増加は極めて僅か（例えば半導体チップ２を４ｍｍ角から３ｍｍ角にシュリンクしても、Ａｕワイヤ６の長さの増加は、平均０．７ｍｍ程度）であるため、半導体チップ２のシュリンクに伴うワイヤボンディングの作業性の低下を防止することができる。   Further, by extending the one end side 5a of the lead 5 to the vicinity of the die pad portion 4, even if the semiconductor chip 2 is shrunk, the length of the Au wire 6 increases very little (for example, the semiconductor chip 2 increases from 4 mm square to 3 mm square). Even when shrinking, the increase in the length of the Au wire 6 is about 0.7 mm on average), so that it is possible to prevent the workability of wire bonding from being lowered due to shrinking of the semiconductor chip 2.

（実施の形態２）
前記実施の形態１では、小タブ構造のリードフレームＬＦ１を使って製造したＱＦＮについて説明したが、例えば図２１および図２２に示すように、リード５の一端部側５ａにシート状のチップ支持体３３を貼り付けたリードフレームＬＦ２を使用して製造することも可能である。本実施形態では、上記チップ支持体３３は、絶縁フィルムからなる。 (Embodiment 2)
In the first embodiment, the QFN manufactured using the lead frame LF 1 having the small tab structure has been described. For example, as shown in FIGS. 21 and 22, a sheet-like chip support is provided on one end side 5a of the lead 5. It is also possible to manufacture using the lead frame LF 2 to which the body 33 is attached. In the present embodiment, the chip support 33 is made of an insulating film.

本実施形態で使用するリードフレームＬＦ２は、前記実施の形態１のリードフレームＬＦ１に準じた方法で製造することができる。すなわち、図２３に示すような板厚１２５μｍ〜１５０μｍ程度の金属板１０を用意し、リード５を形成する箇所の片面をフォトレジスト膜１１で被覆する。また、外部接続用の端子８を形成する箇所には、両面にフォトレジスト膜１１を形成する。そして、前記実施の形態１で説明した方法で金属板１０をハーフエッチングすることによって、厚さ６５μｍ〜７５μｍ程度のリード５と厚さ１２５μｍ〜１５０μｍ程度の端子８を同時に形成した後、リード５の一端部側５ａの表面にＡｇメッキを施し、最後に一端部側５ａの上面に絶縁フィルム３３を接着する。なお、絶縁フィルムに代えて、薄い金属板のような導電材料によってチップ支持体３３を構成してもよい。この場合は、リード５同士のショートを防ぐために、絶縁性の接着剤を使ってリード５と接着すればよい。また、金属箔の表面に絶縁性の樹脂を塗布したシートなどによってチップ支持体３３を構成することもできる。 The lead frame LF 2 used in the present embodiment can be manufactured by a method according to the lead frame LF 1 of the first embodiment. That is, a metal plate 10 having a plate thickness of about 125 μm to 150 μm as shown in FIG. 23 is prepared, and one side of a portion where the lead 5 is to be formed is covered with the photoresist film 11. Further, a photoresist film 11 is formed on both sides where the external connection terminals 8 are to be formed. Then, by half-etching the metal plate 10 by the method described in the first embodiment, the lead 5 having a thickness of about 65 μm to 75 μm and the terminal 8 having a thickness of about 125 μm to 150 μm are simultaneously formed. Ag plating is applied to the surface of the one end side 5a, and finally the insulating film 33 is bonded to the upper surface of the one end side 5a. Note that the chip support 33 may be made of a conductive material such as a thin metal plate instead of the insulating film. In this case, in order to prevent a short circuit between the leads 5, an insulating adhesive may be used to adhere to the leads 5. In addition, the chip support 33 can be configured by a sheet or the like in which an insulating resin is applied to the surface of the metal foil.

上記のようなリードフレームＬＦ２を使用する場合も、金属板１０の一部の片面をフォトレジスト膜１１でマスクしてハーフエッチングを施すことにより、リード５の板厚を金属板１０の半分程度まで薄くすることができるので、リード５の一端部側５ａのピッチが極めて狭い（例えば０．１８ｍｍ〜０．２ｍｍピッチ）リード５を精度よく加工することができる。また、金属板１０の一部の両面をフォトレジスト膜１１でマスクすることにより、突起状の端子８をリード５と同時に形成することができる。 Also in the case of using the lead frame LF 2 as described above, a part of one side of the metal plate 10 is masked with the photoresist film 11 and subjected to half etching, so that the thickness of the lead 5 is about half that of the metal plate 10. Therefore, the lead 5 having a very narrow pitch (for example, 0.18 mm to 0.2 mm pitch) on one end side 5a of the lead 5 can be processed with high accuracy. Further, by masking part of both surfaces of the metal plate 10 with the photoresist film 11, the protruding terminals 8 can be formed simultaneously with the leads 5.

上記リードフレームＬＦ２は、実施の形態１で使用したリードフレームＬＦ１とは異なり、ダイパッド部４を支持する吊りリード５ｂが不要となるので、その分、リード５の一端部側５ａの先端ピッチに余裕を持たせることができる。 Unlike the lead frame LF 1 used in the first embodiment, the lead frame LF 2 does not require the suspension lead 5b that supports the die pad portion 4, and accordingly, the tip pitch of the one end portion side 5a of the lead 5 is increased. Can be afforded.

また、チップ支持体３３をリード５で支持することにより、リード５の一端部側５ａと半導体チップ２の距離が短くなるので、Ａｕワイヤ６の長さをさらに短くすることができる。さらに、ダイパッド部４を４本の吊りリード５Ｂで支持する場合に比べてチップ支持体３３を確実に支持できるので、モールド工程で金型内に溶融樹脂を注入した際、チップ支持体３３の変位が抑制され、Ａｕワイヤ６同士の短絡不良が防止できる。   Further, by supporting the chip support 33 with the lead 5, the distance between the one end portion 5a of the lead 5 and the semiconductor chip 2 is shortened, so that the length of the Au wire 6 can be further shortened. Furthermore, since the chip support 33 can be reliably supported as compared with the case where the die pad portion 4 is supported by the four suspension leads 5B, the displacement of the chip support 33 is caused when molten resin is injected into the mold in the molding process. Is suppressed, and a short circuit failure between the Au wires 6 can be prevented.

このリードフレームＬＦ２を使ったＱＦＮ１の製造方法は、図２４に示すように、前記実施の形態１で説明した方法と概略同一である。 The manufacturing method of QFN 1 using this lead frame LF 2 is substantially the same as the method described in the first embodiment as shown in FIG.

（実施の形態３）
前記実施の形態１、２では、外部接続用の端子８をリードフレーム材料で構成したが、次のような方法で端子を形成することもできる。 (Embodiment 3)
In the first and second embodiments, the terminal 8 for external connection is made of the lead frame material, but the terminal can be formed by the following method.

まず、図２５に示すような板厚７５μｍ程度の金属板１０を用意し、ダイパッド部４、リード５および吊りリード５ｂを形成する箇所の両面をフォトレジスト膜１１で被覆する。そして、この状態で金属板１０をエッチングすることによって、ダイパッド部４、リード５および吊りリード５ｂを形成する。次に、フォトレジスト膜１１を除去し、続いてリード５の一端部側５ａの表面にＡｇメッキを施すことによって、リードフレームＬＦ３を作製する。このリードフレームＬＦ３は、外部接続用の端子８がない点を除けば、前記実施の形態１のリードフレームＬＦ１と同一の構成になっている。なお、リードフレームＬＦ３は、前記実施の形態２のリードフレームＬＦ２と同様、ダイパッド部をチップ支持体３３で構成してもよい。また、リードフレームＬＦ３のダイパッド部４、リード５および吊りリード５ｂは、金属板１０をプレスすることによって形成してもよい。 First, a metal plate 10 having a plate thickness of about 75 μm as shown in FIG. 25 is prepared, and both sides of the portion where the die pad portion 4, the lead 5 and the suspension lead 5 b are formed are covered with the photoresist film 11. And the die pad part 4, the lead 5, and the suspension lead 5b are formed by etching the metal plate 10 in this state. Next, the photoresist film 11 is removed, and then, the lead frame LF 3 is manufactured by performing Ag plating on the surface of the one end portion side 5 a of the lead 5. The lead frame LF 3 has the same configuration as the lead frame LF 1 of the first embodiment except that the external connection terminal 8 is not provided. Note that the lead frame LF 3 may have a die pad portion formed of the chip support 33 as in the lead frame LF 2 of the second embodiment. Further, the die pad portion 4, the lead 5 and the suspension lead 5 b of the lead frame LF 3 may be formed by pressing the metal plate 10.

次に、図２６に示すように、リードフレームＬＦ３の一部に実際の端子としては使用されないダミー端子１２を形成する。ダミー端子１２を形成するには、まず、リードフレームＬＦ３の裏面にスクリーン印刷用のマスク１５を重ね合わせ、後の工程で外部接続用の端子を形成する箇所にポリイミド樹脂１２ａを印刷した後、このポリイミド樹脂１２ａをベークする（図２６（ｂ）〜（ｄ））。ダミー端子１２の大きさは、後の工程で形成する実際の端子の大きさと同程度とする。なお、ここでは、ポリイミド樹脂１２ａをリード５の表面に印刷することによってダミー端子１２を形成する場合について説明したが、これに限定されるものではなく、後の工程でリード５の表面から剥離することができるものであれば、その材質や形成方法は問わない。 Next, as shown in FIG. 26, to form the dummy terminal 12 is not used as an actual terminal portion of the lead frame LF 3. In order to form the dummy terminal 12, first, a mask 15 for screen printing is overlaid on the back surface of the lead frame LF 3 , and polyimide resin 12a is printed at a location where a terminal for external connection is formed in a later step. The polyimide resin 12a is baked (FIGS. 26B to 26D). The size of the dummy terminal 12 is approximately the same as the size of an actual terminal formed in a later process. Here, the case where the dummy terminal 12 is formed by printing the polyimide resin 12a on the surface of the lead 5 has been described. However, the present invention is not limited to this, and is peeled off from the surface of the lead 5 in a later step. As long as it can be used, the material and the forming method are not limited.

次に、前記実施の形態１で説明した方法に従ってダイパッド部４上に半導体チップ２を搭載し、続いてボンディングパッド７とリード５をＡｕワイヤ６で接続する（図２６（ｅ））。   Next, the semiconductor chip 2 is mounted on the die pad portion 4 according to the method described in the first embodiment, and then the bonding pad 7 and the lead 5 are connected by the Au wire 6 (FIG. 26 (e)).

次に、図２７（ａ）に示すように、前記実施の形態１で説明した方法に従い、半導体チップ２をモールド樹脂で成形することによって封止体３を形成する。このとき、リード５の一面に形成された前記ダミー端子１２の先端部分が封止体３の裏面から外側に突出する。   Next, as shown in FIG. 27A, the sealing body 3 is formed by molding the semiconductor chip 2 with a molding resin according to the method described in the first embodiment. At this time, the tip portion of the dummy terminal 12 formed on one surface of the lead 5 protrudes outward from the back surface of the sealing body 3.

次に、図２７（ｂ）に示すように、上記ダミー端子１２をリード５の一面から剥離する。ダミー端子１２がポリイミド樹脂で構成されている場合は、ヒドラジンなどの有機溶剤でダミー端子１２を溶解することによって剥離することができる。ダミー端子１２を剥離すると、封止体３の裏面には窪み３５が形成され、リード５の一面が露出する。   Next, as shown in FIG. 27B, the dummy terminal 12 is peeled from one surface of the lead 5. When the dummy terminal 12 is made of a polyimide resin, the dummy terminal 12 can be peeled off by dissolving it with an organic solvent such as hydrazine. When the dummy terminal 12 is peeled off, a recess 35 is formed on the back surface of the sealing body 3, and one surface of the lead 5 is exposed.

次に、図２８（ａ）に示すように、封止体３の裏面にスクリーン印刷用のマスク１６を重ね合わせた後、図２８（ｂ）に示すように、窪み３５の内部に半田ペースト１３ａを供給する。   Next, as shown in FIG. 28A, after the screen printing mask 16 is overlaid on the back surface of the sealing body 3, the solder paste 13a is placed inside the recess 35 as shown in FIG. Supply.

次に、マスク１６を取り除いた後、半田ペースト１３ａを加熱炉内で溶融させる。これにより、図２９に示すように、窪み３５の内部に露出したリード５に電気的に接続され、先端部分が封止体３の裏面から外側に突出する半田バンプ１３が形成される。   Next, after removing the mask 16, the solder paste 13a is melted in a heating furnace. As a result, as shown in FIG. 29, solder bumps 13 are formed which are electrically connected to the leads 5 exposed inside the depressions 35 and whose tip portions protrude outward from the back surface of the sealing body 3.

なお、ここでは、半田ペースト１３ａをリード５の表面に印刷することによって半田バンプ１３を形成する場合について説明したが、あらかじめ球状に成形した半田ボールを窪み３５の内部に供給した後、この半田ボールをリフローすることによって半田バンプ１３を形成してもよい。   Here, the case where the solder bumps 13 are formed by printing the solder paste 13a on the surface of the lead 5 has been described. However, after solder balls formed in advance in a spherical shape are supplied into the recesses 35, the solder balls 13a are formed. The solder bumps 13 may be formed by reflowing.

なお、ダミー端子１２を除去して半田バンプ１３を形成する作業は、通常、モールド樹脂の成形が完了した直後に行い、その後、リードフレームＬＦ３を切断してＱＦＮ１を個片化するが、ＱＦＮ１を個片化した後にダミー端子１２を除去して半田バンプ１３を形成することも可能である。 Incidentally, the work of forming the solder bump 13 by removing the dummy terminal 12 is typically performed immediately after the molding of the molding resin has been completed, then, although singulating QFN1 by cutting the lead frame LF 3, QFN1 It is also possible to form the solder bumps 13 by removing the dummy terminals 12 after singulation.

上記した本実施形態の製造方法によれば、リードフレーム（ＬＦ１）をハーフエッチングして端子（８）を形成する方法とは異なり、ＱＦＮ１の用途や実装基板の種類などに適合した材料を使って端子を形成することができる。 According to the manufacturing method of the present embodiment described above, unlike the method of forming the terminal (8) by half-etching the lead frame (LF 1 ), a material suitable for the use of the QFN 1 or the type of the mounting substrate is used. Thus, a terminal can be formed.

（実施の形態４）
外部接続用の端子は、次のような方法で形成することもできる。すなわち、図３０に示すように、板厚が７５μｍ程度の薄い金属板２０を用意し、前記実施の形態３と同様の方法で金属板２０をエッチングすることによって、ダイパッド部４、リード５および同図には示さない吊りリード５ｂを有するリードフレームＬＦ４を作製した後、各リード５の中途部を、断面形状が鋸歯状となるようにプレス成形する。吊りリード５ｂの一部を上方に折り曲げるタブ上げ構造を採用する場合は、吊りリード５ｂの折り曲げとリード５の成形を同時に行えばよい。なお、ダイパッド部４、リード５および吊りリード５ｂは、前記実施の形態１で用いたような厚い金属板１０をハーフエッチングあるいはプレス成形して形成してもよい。 (Embodiment 4)
The terminal for external connection can also be formed by the following method. That is, as shown in FIG. 30, a thin metal plate 20 having a thickness of about 75 μm is prepared, and the metal plate 20 is etched by the same method as in the third embodiment. After the lead frame LF 4 having the suspension leads 5b not shown in the drawing is manufactured, the middle part of each lead 5 is press-molded so that the cross-sectional shape is a sawtooth shape. When a tab raising structure in which a part of the suspension lead 5b is bent upward is adopted, the suspension lead 5b may be bent and the lead 5 may be formed simultaneously. The die pad portion 4, the lead 5 and the suspension lead 5b may be formed by half-etching or press-molding the thick metal plate 10 used in the first embodiment.

次に、図３１に示すように、上記リードフレームＬＦ４のダイパッド部４上に半導体チップ２を搭載し、続いてボンディングパッド７とリード５の一端部側５ａをＡｕワイヤ６で結線した後、半導体チップ２をモールド樹脂で成形することによって封止体３を形成する。このようにすると、封止体３の裏面には、鋸歯状に成形されたリード５の凸部が露出する。 Next, as shown in FIG. 31, the semiconductor chip 2 is mounted on the die pad portion 4 of the lead frame LF 4 , and then the bonding pad 7 and one end portion side 5 a of the lead 5 are connected by the Au wire 6. The sealing body 3 is formed by molding the semiconductor chip 2 with a molding resin. If it does in this way, the convex part of the lead 5 shape | molded by the sawtooth shape will be exposed to the back surface of the sealing body 3. FIG.

次に、図３２に示すように、封止体３の裏面に露出したリード５の下端部をグラインダなどの工具で研磨して各リード５の中途部を切断することによって、１本のリード５を複数のリード５、５に分割する。   Next, as shown in FIG. 32, the lower end portion of the lead 5 exposed on the back surface of the sealing body 3 is polished with a tool such as a grinder, and the middle portion of each lead 5 is cut to thereby obtain one lead 5. Is divided into a plurality of leads 5 and 5.

次に、図３３に示すように、１本のリード５から分割された複数のリード５、５のそれぞれに端子３６を形成する。この端子３６の形成には、導電性ペーストの印刷、半田ボール供給法あるいはメッキ法などを使用すればよい。また、端子３６を形成する作業は、通常、モールド樹脂を成形して封止体３を形成した直後に行い、その後、リードフレームＬＦ４を切断してＱＦＮ１を個片化するが、ＱＦＮ１を個片化した後に端子３６を形成することも可能である。 Next, as shown in FIG. 33, a terminal 36 is formed on each of the plurality of leads 5, 5 divided from one lead 5. The terminal 36 may be formed by using conductive paste printing, solder ball supply method, plating method, or the like. Further, the operation for forming the terminal 36 is usually performed immediately after forming the sealing body 3 by molding the mold resin, and then the lead frame LF 4 is cut to separate the QFN 1 into individual pieces. It is also possible to form the terminal 36 after separation.

また、上記した本実施形態の端子形成方法を用いる場合は、例えば図３４に示すように、半導体チップ２から離れた位置と半導体チップ２の近傍とに交互に一端部側５ａを設けた幅の広いリード５を形成し、このリード５の各一端部側５ａにＡｕワイヤをボンディングした後、図３５に示すように、リード５の中途部を研磨、切断することによって、多数のリード５を分割形成することもできる。この方法によれば、隣接するリード５との間隔を実質的に無くすことができるので、ＱＦＮ１の端子数を大幅に増やすことができる。   Further, when the terminal forming method of the present embodiment described above is used, for example, as shown in FIG. 34, the width of the width where the one end side 5a is alternately provided in the position away from the semiconductor chip 2 and in the vicinity of the semiconductor chip 2 is provided. A wide lead 5 is formed, and an Au wire is bonded to each one end side 5a of the lead 5. Then, as shown in FIG. 35, the middle part of the lead 5 is polished and cut to divide a large number of leads 5. It can also be formed. According to this method, since the interval between the adjacent leads 5 can be substantially eliminated, the number of terminals of the QFN 1 can be greatly increased.

（実施の形態５）
図３６は、ＱＦＮの製造に用いるリードフレームＬＦ５の一部を示す平面図、図３７は、このリードフレームＬＦ５を用いて製造したＱＦＮの内部構造（表面側）を示す平面図である。 (Embodiment 5)
Figure 36 is a plan view showing a part of the lead frame LF 5 for use in the QFN fabrication, Figure 37 is a plan view showing the internal structure of a QFN manufactured using this lead frame LF 5 (surface side).

本実施の形態のリードフレームＬＦ５は、ダイパッド部４の周囲を囲む複数本のリード５の先端（一端部側５ａ）の長さを交互に変えた構成になっている。また、このリードフレームＬＦ５を使用する場合は、ダイパッド部４に搭載する半導体チップ２として、その主面の各辺に沿ってボンディングパッド７を２列ずつ千鳥状に配置したものを使用する。 The lead frame LF 5 of the present embodiment has a configuration in which the lengths of the tips (one end side 5a) of the plurality of leads 5 surrounding the die pad portion 4 are alternately changed. When this lead frame LF 5 is used, a semiconductor chip 2 mounted on the die pad portion 4 is used in which bonding pads 7 are arranged in two rows in a staggered manner along each side of the main surface.

このように、リードフレームＬＦ５のリード５の先端の長さを交互に変え、かつ半導体チップ２のボンディングパッド７を千鳥状に配置した場合は、図３８に示すように、半導体チップ２の外側に近い列のボンディングパッド７と先端の長さが長いリード５とを、ループ高さが低くかつ長さが短いＡｕワイヤ６で接続し、内側の列のボンディングパッド７と先端の長さが短いリード５とを、ループ高さが高くかつ長さが長いＡｕワイヤ６で接続する。 In this way, when the lengths of the tips of the leads 5 of the lead frame LF 5 are alternately changed and the bonding pads 7 of the semiconductor chip 2 are arranged in a staggered manner, as shown in FIG. The bonding pads 7 in a row close to the lead 5 and the lead 5 having a long tip are connected by an Au wire 6 having a short loop height and a short length, and the length of the bonding pad 7 in the inner row and the tip is short. The lead 5 is connected by an Au wire 6 having a high loop height and a long length.

これにより、半導体チップ２の多ピン化に伴ってリード５のピッチ、すなわちＡｕワイヤ６の間隔が狭くなった場合でも、互いに隣接するＡｕワイヤ６同士の干渉を防ぐことができるので、ＱＦＮの製造工程（例えば、ワイヤボンディング工程や樹脂モールド工程）でＡｕワイヤ６同士が短絡する不良の発生を有効に抑制することができる。   Thereby, even when the pitch of the leads 5, that is, the interval between the Au wires 6 becomes narrow as the number of pins of the semiconductor chip 2 is increased, interference between the adjacent Au wires 6 can be prevented. Generation | occurrence | production of the defect which Au wires 6 short-circuit in a process (for example, wire bonding process or resin mold process) can be suppressed effectively.

上記リードフレームＬＦ５は、図３９に示すように、ボンディングパッド７が一列に配置された半導体チップ２を搭載する場合にも使用することができる。また、半導体チップ２を搭載するダイパッド部４の形状は、円形に限定されるものではなく、例えば図４０に示すリードフレームＬＦ６や、図４１に示すリードフレームＬＦ７のように、ダイパッド部４の幅を吊りリード５ｂの幅よりも広くする、いわゆるクロスタブ構造などを採用することもできる。この場合は、図４０に示すように、ダイパッド部４上の複数箇所に接着剤１４を塗布して半導体チップ２を接着することにより、半導体チップ２の回転方向のずれが有効に防止されるので、ダイパッド部４と半導体チップ２の相対的な位置精度が向上する。また、実質的に吊りリード５ｂの一部としても機能するダイパッド部４の幅が広いことにより、吊りリード５ｂの剛性が向上するという効果も得られる。なお、上記のようなクロスタブ構造のダイパッド部４においても、サイズの異なる複数種類の半導体チップ２を搭載できることはいうまでもない。 As shown in FIG. 39, the lead frame LF 5 can also be used when a semiconductor chip 2 having bonding pads 7 arranged in a row is mounted. Further, the shape of the die pad portion 4 on which the semiconductor chip 2 is mounted is not limited to a circular shape. For example, the die pad portion 4 is like a lead frame LF 6 shown in FIG. 40 or a lead frame LF 7 shown in FIG. It is also possible to employ a so-called crosstab structure or the like in which the width of the wire is wider than the width of the suspension lead 5b. In this case, as shown in FIG. 40, by applying the adhesive 14 to a plurality of locations on the die pad portion 4 and bonding the semiconductor chip 2, displacement of the semiconductor chip 2 in the rotational direction can be effectively prevented. Thus, the relative positional accuracy between the die pad portion 4 and the semiconductor chip 2 is improved. In addition, since the die pad portion 4 that substantially functions as a part of the suspension lead 5b is wide, an effect that the rigidity of the suspension lead 5b is improved can be obtained. Needless to say, a plurality of types of semiconductor chips 2 having different sizes can also be mounted on the die pad portion 4 having the crosstab structure as described above.

（実施の形態６）
ＱＦＮの端子は、次のような方法で形成することもできる。まず、図４２（ａ）に示すように、例えば前記実施の形態３の図２５に示した方法で作製したリードフレームＬＦ３を用意する。次に、図４２（ｂ）〜（ｄ）に示すように、リードフレームＬＦ３の裏面にスクリーン印刷用のマスク１７を重ね合わせ、端子を形成する箇所にＣｕペースト１８ａを印刷した後、このＣｕペースト１８ａをベークすることによってＣｕ端子１８を形成する。 (Embodiment 6)
The terminal of QFN can also be formed by the following method. First, as shown in FIG. 42A, for example, a lead frame LF 3 manufactured by the method shown in FIG. 25 of the third embodiment is prepared. Next, as shown in FIGS. 42B to 42D, after the screen printing mask 17 is overlaid on the back surface of the lead frame LF 3 and the Cu paste 18a is printed at the locations where the terminals are to be formed, this Cu The Cu terminal 18 is formed by baking the paste 18a.

次に、図４２（ｅ）に示すように、前記実施の形態１で説明した方法に従ってダイパッド部４上に半導体チップ２を搭載し、続いてボンディングパッド７とリード５をＡｕワイヤ６で接続する。   Next, as shown in FIG. 42E, the semiconductor chip 2 is mounted on the die pad portion 4 according to the method described in the first embodiment, and then the bonding pad 7 and the lead 5 are connected by the Au wire 6. .

次に、図４３に示すように、前記実施の形態１で説明した方法に従い、半導体チップ２をモールド樹脂で成形することによって封止体３を形成する。これにより、リード５の一面に形成された前記Ｃｕ端子１８の先端部分が封止体３の裏面から外側に突出する。   Next, as shown in FIG. 43, according to the method described in the first embodiment, the sealing body 3 is formed by molding the semiconductor chip 2 with a molding resin. As a result, the tip of the Cu terminal 18 formed on one surface of the lead 5 protrudes outward from the back surface of the sealing body 3.

その後、必要に応じてＣｕ端子１８の表面に無電解メッキ法などを用いてＳｎやＡｕのメッキを施してもよい。   Thereafter, Sn or Au may be plated on the surface of the Cu terminal 18 as necessary using an electroless plating method or the like.

上記した本実施形態の製造方法によれば、リード５の一面にダミー端子１２を形成した後、ダミー端子１２を除去して半田バンプ１３を形成する前記実施の形態３の方法に比べて、端子形成工程を簡略化することができる。   According to the manufacturing method of the present embodiment described above, the dummy terminal 12 is formed on one surface of the lead 5, and then the dummy terminal 12 is removed to form the solder bump 13 as compared with the method of the third embodiment. The formation process can be simplified.

（実施の形態７）
図４４に示すＱＦＮ１は、リード５の一端部側（半導体チップ２に近い側）５ａを上方に折り曲げた例である。このようにすると、リード５の一端部側５ａと半導体チップ２の主面との段差が小さくなり、リード５とボンディングパッド７を接続するＡｕワイヤ６のループ高さを低くできるので、その分、封止体３の厚さを薄くすることができる。 (Embodiment 7)
The QFN 1 shown in FIG. 44 is an example in which one end portion side (side near the semiconductor chip 2) 5a of the lead 5 is bent upward. In this way, the step between the one end side 5a of the lead 5 and the main surface of the semiconductor chip 2 is reduced, and the loop height of the Au wire 6 connecting the lead 5 and the bonding pad 7 can be reduced. The thickness of the sealing body 3 can be reduced.

また、図４５に示すＱＦＮ１は、リード５の一端部側５ａを上方に折り曲げると共に、ダイパッド部４をリード５の一端部側５ａとほぼ同じ高さにし、このダイパッド部４の下面側に半導体チップ２をフェイスダウン方式で搭載した例である。このようにすると、リード５の一端部側５ａおよびダイパッド部４のそれぞれの上面と封止体３の上面との間の樹脂厚を極めて薄くできるので、封止体３の厚さが０．５ｍｍ程度の超薄型ＱＦＮを実現することができる。   Further, the QFN 1 shown in FIG. 45 bends one end portion 5a of the lead 5 upward, makes the die pad portion 4 substantially the same height as the one end portion 5a of the lead 5, and places a semiconductor chip on the lower surface side of the die pad portion 4. This is an example in which 2 is mounted in a face-down manner. In this way, the resin thickness between the upper surface of the one end portion side 5a of the lead 5 and the die pad portion 4 and the upper surface of the sealing body 3 can be made extremely thin, so that the thickness of the sealing body 3 is 0.5 mm. A super thin QFN can be realized.

リード５の一端部側５ａを上方に折り曲げる上記方式は、例えば図４６および図４７に示すように、リード５の一端部側５ａに絶縁フィルムからなるチップ支持体３３を貼り付けたリードフレームＬＦ２を使用する場合にも適用することができる。チップ支持体３３と半導体チップ２との接着は、例えばチップ支持体３３の片面に形成した接着剤１９を介して行う。この場合も、前述した理由から、封止体３の厚さを薄くすることができる。 For example, as shown in FIGS. 46 and 47, the above-described method of bending the one end side 5a of the lead 5 upward is a lead frame LF 2 in which a chip support 33 made of an insulating film is attached to the one end side 5a of the lead 5. It can also be applied when using The chip support 33 and the semiconductor chip 2 are bonded via an adhesive 19 formed on one surface of the chip support 33, for example. Also in this case, the thickness of the sealing body 3 can be reduced for the reason described above.

図４８および図４９は、例えばＣｕやＡｌのような熱伝導性の高い材料からなるヒートスプレッダ２３を使ってチップ支持体を構成した例である。ヒートスプレッダ２３をとチップ支持体を兼用することにより、放熱性の良好なＱＦＮを実現することができる。また、ヒートスプレッダ２３を使ってチップ支持体を構成する場合は、図５０に示すように、ヒートスプレッダ２３の一面を封止体３の表面に露出させることも可能であり、これにより、放熱性をさらに向上させることができる。   48 and 49 show an example in which a chip support is configured using a heat spreader 23 made of a material having high thermal conductivity such as Cu or Al. By using the heat spreader 23 also as a chip support, a QFN with good heat dissipation can be realized. Further, when the chip support is configured using the heat spreader 23, it is possible to expose one surface of the heat spreader 23 on the surface of the sealing body 3 as shown in FIG. Can be improved.

なお、本実施の形態は、リードフレームをハーフエッチングして形成した端子８を有するＱＦＮに適用したが、これに限定されるものではなく、前述した各種の方法で形成した端子を有するＱＦＮに適用できることはもちろんである。   The present embodiment is applied to the QFN having the terminals 8 formed by half-etching the lead frame, but is not limited to this, and is applied to the QFN having the terminals formed by the various methods described above. Of course you can.

（実施の形態８）
図５１は、ＱＦＮの製造に用いるリードフレームＬＦ８の一部を示す平面図、図５２は、このリードフレームＬＦ８を用いて製造したＱＦＮの外観（裏面側）を示す平面図である。 (Embodiment 8)
Figure 51 is a plan view, FIG. 52 showing a portion of the lead frame LF 8 for use in the QFN manufacturing is a plan view showing an appearance of a QFN manufactured using this lead frame LF 8 (back side).

ＱＦＮのパッケージサイズを一定にしたままで多ピン化を進めた場合、端子８のピッチが極めて狭くなるため、前記実施の形態１で使用したリードフレームＬＦ１のように、端子８の幅をリード５の幅よりも広くしようとするとリードフレームの加工が非常に困難になる。 When the number of pins is increased while the package size of the QFN is kept constant, the pitch of the terminals 8 becomes extremely narrow, so that the width of the terminals 8 is made to be the same as the lead frame LF 1 used in the first embodiment. If the width is larger than 5, the processing of the lead frame becomes very difficult.

その対策としては、本実施の形態のリードフレームＬＦ８のように、端子８の幅をリード５の幅と同じすることが望ましい。これにより、例えば端子８およびリード５の幅（ｄ）が０．１５〜０．１８ｍｍ、隣接する端子８とのピッチは、同一列の端子８とのピッチ（Ｐ１）が０．５ｍｍ、他の列の端子とのピッチ（Ｐ２）が０．２５ｍｍといった狭ピッチ超多ピンののＱＦＮを実現することができる。 As a countermeasure, it is desirable to make the width of the terminal 8 the same as the width of the lead 5 as in the lead frame LF 8 of the present embodiment. Thereby, for example, the width (d) of the terminal 8 and the lead 5 is 0.15 to 0.18 mm, the pitch with the adjacent terminal 8 is 0.5 mm with the pitch (P 1 ) with the terminal 8 in the same row, etc. A QFN of a super-multi-narrow pitch having a pitch (P 2 ) with a terminal of a row of 0.25 mm can be realized.

この場合、端子８の幅が狭くなったことによって端子８と実装基板との接触面積が小さくなり、接続信頼性が低下するので、これを補償する手段として、端子８の長さを長くすることによって、面積の低下を防ぐことが望ましい。また、リード５の幅が狭くなったことによってリード５の強度も低下するため、リード５の先端にチップ支持体３３を貼り付け、このチップ支持体３３でリード５を支持することにより、リード５の変形を防ぐようにすることが望ましい。チップ支持体３３は、図５３に示すように、リード５の中途部に設けてもよい。端子８の幅をリード５の幅と同じする本実施の形態のリードフレームＬＦ８は、図５４および図５５に示すように、チップ支持体３３を有しないものに適用できることはもちろんである。 In this case, since the contact area between the terminal 8 and the mounting substrate is reduced by reducing the width of the terminal 8 and the connection reliability is lowered, the length of the terminal 8 is increased as a means for compensating for this. Therefore, it is desirable to prevent the area from decreasing. In addition, since the strength of the lead 5 is reduced due to the reduction in the width of the lead 5, the chip support 33 is attached to the tip of the lead 5, and the lead 5 is supported by the chip support 33. It is desirable to prevent deformation. The chip support 33 may be provided in the middle of the lead 5 as shown in FIG. Of course, the lead frame LF 8 of the present embodiment in which the width of the terminal 8 is the same as the width of the lead 5 can be applied to one having no chip support 33 as shown in FIGS.

以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

例えば、前記実施の形態１で説明した金型４０を使用して一枚のリードフレームＬＦ１に搭載された多数の半導体チップ２を同時に樹脂封止する場合は、リードフレームＬＦ１とモールド樹脂との熱膨張係数差に起因してダイシング前のリードフレームＬＦ１に反りや変形が生じる場合がある。 For example, in the case where a large number of semiconductor chips 2 mounted on one lead frame LF 1 are simultaneously resin-sealed using the mold 40 described in the first embodiment, the lead frame LF 1 and the mold resin In some cases, the lead frame LF 1 before dicing is warped or deformed due to the difference in thermal expansion coefficient.

これを防止するには、例えば図５６に示すように、リードフレームＬＦ１の外枠部分にスリット２２を設けることが有効である。また、封止体３を構成するモールド樹脂に含まれるフィラーなどの量を変えることによって、封止体３の熱膨張係数をリードフレームＬＦ１の熱膨張係数に近づけることも有効である。 To prevent this, for example, as shown in FIG. 56, it is effective to provide the slit 22 in the outer frame portion of the lead frame LF 1. It is also effective to bring the thermal expansion coefficient of the sealing body 3 closer to the thermal expansion coefficient of the lead frame LF 1 by changing the amount of filler or the like contained in the mold resin constituting the sealing body 3.

また、例えば図５７に示すように、封止体３の裏面にダイパッド部４を露出させることによって、放熱性の高いＱＦＮ１を実現することができる。封止体３の裏面にダイパッド部４を露出させるには、例えば厚い板厚の金属板１０をハーフエッチングして薄い板厚のリード５および吊りリード５ｂを形成する際、ダイパッド部４をフォトレジスト膜で覆っておくことにより、厚い板厚のダイパッド部４を形成すればよい。   For example, as shown in FIG. 57, by exposing the die pad portion 4 to the back surface of the sealing body 3, it is possible to realize the QFN 1 with high heat dissipation. In order to expose the die pad portion 4 on the back surface of the sealing body 3, for example, when the thin metal plate 10 is half-etched to form the thin lead 5 and the suspension lead 5 b, the die pad portion 4 is exposed to the photoresist. By covering with a film, the thick die pad portion 4 may be formed.

また、前記実施の形態１では、厚い板厚の金属板１０をハーフエッチングして薄い板厚のダイパッド部４、リード５および吊りリード５ｂを形成したが、薄い板厚の吊りリード５ｂに比較的大きいサイズの半導体チップ２を搭載した場合は、吊りリード５ｂの剛性が不足することがある。その対策としては、例えば図５８に示すように、吊りリード５ｂの一部または全体をハーフエッチングせず、厚い板厚で形成することが有効である。また、この場合は、吊りリード５ｂの一部（または全体）が封止体３の裏面に露出するので、この露出部分を配線基板に半田付けすることによって、ＱＦＮ１と配線基板の接続信頼性やＱＦＮ１の放熱性を向上させることができる。   In the first embodiment, the thick metal plate 10 is half-etched to form the thin die pad portion 4, the lead 5 and the suspension lead 5b. When a large size semiconductor chip 2 is mounted, the rigidity of the suspension lead 5b may be insufficient. As a countermeasure, for example, as shown in FIG. 58, it is effective to form a thick plate thickness without partially etching the whole or part of the suspension lead 5b. In this case, since part (or the whole) of the suspension lead 5b is exposed on the back surface of the sealing body 3, the connection reliability between the QFN 1 and the wiring board can be obtained by soldering the exposed part to the wiring board. The heat dissipation of QFN1 can be improved.

また、前記実施の形態では、封止体３を形成する際、金型４０（上型４０Ａおよび下型４０Ｂ）の間に樹脂シート４１を挟むモールド成形方法を用いたが、図５９に示すように、樹脂シート４１を使用しないモールド成形方法で封止体３を形成してもよい。この場合は、封止体３を金型４０から取り出した際、図６０（ａ）に示すように、端子８の一部が樹脂で覆われたり、図６０（ｂ）に示すように、端子８の全体が樹脂で覆われたりすることがあるので、図６１に示すように、グラインダなどのバリ取り手段３７を使って端子８の表面の樹脂バリを除去し、その後、端子８の表面に前述した印刷法やメッキ法で金属層を形成すればよい。   Moreover, in the said embodiment, when forming the sealing body 3, the molding method which sandwiches the resin sheet 41 between the metal mold | die 40 (upper mold | type 40A and lower mold | type 40B) was used, but as shown in FIG. In addition, the sealing body 3 may be formed by a molding method that does not use the resin sheet 41. In this case, when the sealing body 3 is taken out from the mold 40, as shown in FIG. 60 (a), a part of the terminal 8 is covered with resin, or as shown in FIG. 60 (b), the terminal 6 may be covered with resin, as shown in FIG. 61, the deburring means 37 such as a grinder is used to remove the resin burr on the surface of the terminal 8, and then the surface of the terminal 8 is removed. The metal layer may be formed by the printing method or plating method described above.

本発明は、ＱＦＮのような樹脂封止型半導体装置に適用することができる。   The present invention can be applied to a resin-encapsulated semiconductor device such as QFN.

本発明の一実施の形態である半導体装置の外観（表面側）を示す平面図である。It is a top view which shows the external appearance (surface side) of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の外観（裏面側）を示す平面図である。It is a top view which shows the external appearance (back surface side) of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の内部構造（表面側）を示す平面図である。It is a top view which shows the internal structure (surface side) of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の内部構造（裏面側）を示す平面図である。It is a top view which shows the internal structure (back surface side) of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の断面図である。It is sectional drawing of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の製造に用いるリードフレームの全体平面図である。1 is an overall plan view of a lead frame used for manufacturing a semiconductor device according to an embodiment of the present invention; 図６に示すリードフレームの製造方法を示す要部断面図である。FIG. 7 is a main part sectional view showing a method for manufacturing the lead frame shown in FIG. 6. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームの要部平面図である。It is a principal part top view of the lead frame which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームの要部断面図である。It is principal part sectional drawing of the lead frame which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームの要部平面図である。It is a principal part top view of the lead frame which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームの要部断面図である。It is principal part sectional drawing of the lead frame which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームおよび金型の要部断面図である。It is principal part sectional drawing of the lead frame and metal mold | die which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームおよび金型の要部断面図である。It is principal part sectional drawing of the lead frame and metal mold | die which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームの要部平面図である。It is a principal part top view of the lead frame which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームおよび金型の要部断面図である。It is principal part sectional drawing of the lead frame and metal mold | die which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. 本発明の一実施の形態である半導体装置の製造に用いる金型の上型がリードフレームと接触する部分を示した平面図である。It is the top view which showed the part which the upper mold | type of the metal mold | die used for manufacture of the semiconductor device which is one embodiment of this invention contacts a lead frame. 本発明の一実施の形態である半導体装置の製造に用いる金型のゲートの位置と、キャビティに注入された樹脂の流れる方向を模式的に示した平面図である。It is the top view which showed typically the position of the gate of the metal mold | die used for manufacture of the semiconductor device which is one embodiment of this invention, and the flow direction of the resin inject | poured into the cavity. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームの全体平面図（表面側）である。1 is an overall plan view (front side) of a lead frame showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームの断面図である。1 is a cross-sectional view of a lead frame illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 本発明の一実施の形態である半導体装置の製造方法を示すリードフレームの全体平面図（裏面側）である。1 is an overall plan view (back side) of a lead frame showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; 本発明の他の実施の形態である半導体装置の製造に用いるリードフレームの要部平面図である。It is a principal part top view of the lead frame used for manufacture of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造に用いるリードフレームの要部断面図である。It is principal part sectional drawing of the lead frame used for manufacture of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造に用いるリードフレームの製造方法を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing method of the lead frame used for manufacture of the semiconductor device which is other embodiment of this invention. 図２１および図２２に示すリードフレームを使った半導体装置の製造方法を示す要部断面図である。FIG. 23 is an essential part cross-sectional view showing a method of manufacturing a semiconductor device using the lead frame shown in FIGS. 21 and 22. 本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. （ａ）〜（ｅ）は、本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。(A)-(e) is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. （ａ）、（ｂ）は、本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。(A), (b) is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. （ａ）、（ｂ）は、本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。(A), (b) is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。It is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示すリードフレームの要部平面図である。It is a principal part top view of the lead frame which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示すリードフレームの要部平面図である。It is a principal part top view of the lead frame which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法に用いるリードフレームの要部平面図である。It is a principal part top view of the lead frame used for the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の内部構造（表面側）を示す平面図である。It is a top view which shows the internal structure (surface side) of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示す説明図である。It is explanatory drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示すリードフレームの要部平面図である。It is a principal part top view of the lead frame which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法に用いるリードフレームの要部平面図である。It is a principal part top view of the lead frame used for the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法に用いるリードフレームの要部平面図である。It is a principal part top view of the lead frame used for the manufacturing method of the semiconductor device which is other embodiment of this invention. （ａ）〜（ｅ）は、本発明の他の実施の形態である半導体装置の製造方法を示す要部断面図である。(A)-(e) is principal part sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is other embodiment of this invention. （ａ）、（ｂ）は、本発明の他の実施の形態である半導体装置を示す断面図である。(A), (b) is sectional drawing which shows the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法に用いるリードフレームの要部平面図である。It is a principal part top view of the lead frame used for the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の外観（裏面側）を示す平面図である。It is a top view which shows the external appearance (back surface side) of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法に用いるリードフレームの要部平面図である。It is a principal part top view of the lead frame used for the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法に用いるリードフレームの要部平面図である。It is a principal part top view of the lead frame used for the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法に用いるリードフレームの要部平面図である。It is a principal part top view of the lead frame used for the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造に用いるリードフレームの要部平面図である。It is a principal part top view of the lead frame used for manufacture of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の断面図である。It is sectional drawing of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の内部構造（裏面側）を示す平面図である。It is a top view which shows the internal structure (back surface side) of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の製造方法を示す金型の要部断面図である。It is principal part sectional drawing of the metal mold | die which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. （ａ）、（ｂ）は、金型から取り出した封止体の部分拡大断面図である。(A), (b) is the elements on larger scale of the sealing body taken out from the metal mold | die. 本発明の他の実施の形態である半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which is other embodiment of this invention.

符号の説明Explanation of symbols

１ ＱＦＮ
２ 半導体チップ
３ 封止体
４ ダイパッド部
５ リード
５ａ リードの一端部側
５ｂ 吊りリード
５ｃ リードの他端部側
６ Ａｕワイヤ
７ ボンディングパッド
８ 端子
９ 半田層
１０ 金属板
１１ フォトレジスト膜
１２ ダミー端子
１２ａ ポリイミド樹脂
１３ 半田バンプ
１３ａ 半田ペースト
１４ 接着剤
１５、１６、１７ マスク
１８ａ Ｃｕペースト
１８ Ｃｕ端子
１９ 接着剤
２０ 金属板
２１ 端子
２２ スリット
２３ ヒートスプレッダ
３０Ａ、３０Ｂ 治具
３１ 溝
３２ 突起
３３ チップ支持体
３４ ダミー端子
３５ 窪み
３６ 端子
３７ バリ取り手段
４０ 金型
４０Ａ 上型
４０Ｂ 下型
４１ 樹脂シート
４２ エアベント
Ｃ１〜Ｃ２４ キャビティ
ｄ 端子の径
ＤＣ１〜ＤＣ８ ダミーキャビティ
Ｇ１〜Ｇ１６ ゲート
Ｌ ダイシングライン
ＬＦ１〜ＬＦ８ リードフレーム
Ｐ１ 端子間ピッチ（同一列）
Ｐ２ 端子間ピッチ（異なる列）
Ｐ３ リード一端部側先端ピッチ 1 QFN
2 Semiconductor chip 3 Sealing body 4 Die pad portion 5 Lead 5a Lead one end side 5b Hanging lead 5c Lead other end side 6 Au wire 7 Bonding pad 8 Terminal 9 Solder layer 10 Metal plate 11 Photoresist film 12 Dummy terminal 12a Polyimide resin 13 Solder bump 13a Solder paste 14 Adhesive 15, 16, 17 Mask 18a Cu paste 18 Cu terminal 19 Adhesive 20 Metal plate 21 Terminal 22 Slit 23 Heat spreader 30A, 30B Jig 31 Groove 32 Projection 33 Chip support 34 Dummy terminal 35 recess 36 pin 37 deburring means 40 the mold 40A upper mold 40B lower die 41 resin sheet 42 Air vent C 1 -C 24 diameter DC 1 to DC 8 dummy cavity G 1 ~G 16 gate L dicing line LF of the cavity d terminal 1 to LF 8 Node frame P 1 terminal pitch (in the same row)
P 2 terminal pitch (different rows)
P 3 lead one end tip pitch

Claims (5)

以下の工程を含むことを特徴とする半導体装置の製造方法：
（ａ）平面形状が四辺形からなり、第１ダイパッド部、および平面視において前記第１ダイパッド部の周囲に配置された複数の第１リードを有する第１パターンと、平面形状が四辺形からなり、第２ダイパッド部、および平面視において前記第２ダイパッド部の周囲に配置された複数の第２リードを有し、かつ前記第１パターンの隣に配置された第２パターンと、平面視において前記第１パターンと前記第２パターンとの間に配置され、かつ前記複数の第１リードおよび前記複数の第２リードと連結する連結部分と、平面視において前記第１パターンおよび前記第２パターンの外側に位置する外枠部分とを備えたリードフレームを準備する工程；
（ｂ）第１金型と、前記第１金型に形成された第１キャビティと、前記第１金型に形成された第２キャビティと、前記第１金型と対向する第２金型とを備えた金型を準備する工程；
（ｃ）前記リードフレームの前記第１および第２ダイパッド部のそれぞれの上面に半導体チップを搭載する工程；
（ｄ）前記（ｃ）工程の後、前記第１金型に形成された前記第１および第２キャビティが前記リードフレームの前記第１および第２パターンにそれぞれ対応し、かつ前記第１および第２ダイパッド部のそれぞれの前記上面に搭載された前記半導体チップが前記第１および前記第２キャビティでそれぞれ覆われるように、前記リードフレームの前記連結部分および前記外枠部分を前記第１金型と前記第２金型とで挟み込み、前記金型に形成されたゲートを介して前記第１キャビティ内に樹脂を注入し、さらに、前記第１キャビティを介して前記第２キャビティ内に前記樹脂を注入し、前記複数の第１および第２リードのそれぞれの一部が露出するように、前記第１および第２パターンを一括して封止する樹脂封止体を成形する工程；
（ｅ）前記（ｄ）工程の後、前記樹脂封止体の一部および前記リードフレームをダイサーで切断することによって、前記樹脂封止体を個片化する工程；
ここで、
前記（ｄ）工程により形成される前記樹脂封止体は、前記第１および第２ダイパッド部のそれぞれの前記上面側に位置する表面と、前記表面とは反対側の裏面を有しており、
前記（ｄ）工程では、前記第１金型に形成され、かつ平面視において前記第１キャビティと前記第２キャビティとの間に設けられ、かつ前記リードフレームを前記第１金型と前記第２金型とで挟み込んだ際、前記リードフレームの前記連結部分のうち、前記連結部分と繋がる前記複数の第１および第２リードのうちの最も端に位置するリードが繋がる第１部分よりも外側の第２部分と平面的に重なる位置に設けられた連通部分を介して、前記第１キャビティから前記第２キャビティに前記樹脂を供給しており、
さらに前記（ｄ）工程では、前記リードフレームの前記連結部分のうち、前記連結部分における前記第２部分以外を前記第１金型と前記第２金型とで挟み込んだ状態で前記第１および前記第２キャビティ内に前記樹脂を注入することで、前記複数の第１および第２リードのそれぞれの前記一部が前記樹脂封止体の前記裏面から露出するように、前記第１および第２パターンを一括して封止する前記樹脂封止体を成形する。 A method for manufacturing a semiconductor device comprising the following steps:
(A) The planar shape is a quadrilateral, the first pattern having a first die pad portion, and a plurality of first leads arranged around the first die pad portion in plan view, and the planar shape is a quadrilateral. The second die pad section, and a second pattern disposed around the second die pad section in plan view, and disposed next to the first pattern, and in plan view A connecting portion disposed between the first pattern and the second pattern and connected to the plurality of first leads and the plurality of second leads; and the outside of the first pattern and the second pattern in plan view Providing a lead frame with an outer frame portion located at a position ;
(B) a first mold, a first cavity formed in the first mold, a second cavity formed in the first mold, and a second mold facing the first mold. Preparing a mold comprising:
( C ) mounting a semiconductor chip on each upper surface of the first and second die pad portions of the lead frame ;
( D) After the step (c), the first and second cavities formed in the first mold correspond to the first and second patterns of the lead frame, respectively, and the first and second cavities The connecting portion and the outer frame portion of the lead frame are connected to the first mold so that the semiconductor chips mounted on the upper surfaces of the two die pad portions are respectively covered with the first and second cavities. sandwiched between the second mold, the resin is injected into the first cavity through a gate formed in the mold, further, injecting the resin into the second cavity through said first cavity And molding a resin sealing body that collectively seals the first and second patterns so that a part of each of the plurality of first and second leads is exposed ;
(E) after step (d), by cutting a portion and the lead frame of the resin sealing body with a dicer, the step of singulating the resin sealing body;
here,
The resin sealing body formed by the step (d) has a surface located on the upper surface side of each of the first and second die pad portions, and a back surface opposite to the surface,
In the step (d), the lead mold is formed in the first mold and provided between the first cavity and the second cavity in a plan view, and the lead frame is formed between the first mold and the second mold. Out of the connecting portions of the lead frame, the outermost lead of the plurality of first and second leads connected to the connecting portion is connected to the outermost portion of the lead frame when the lead is positioned between the leads. The resin is supplied from the first cavity to the second cavity via a communication portion provided at a position overlapping the second portion in a plane,
Further, in the step (d), the first and the second molds are sandwiched between the first mold and the second mold except for the second part of the connection part among the connection parts of the lead frame. By injecting the resin into the second cavity, the first and second patterns are formed such that the portions of the plurality of first and second leads are exposed from the back surface of the resin sealing body. The resin sealing body that seals all of the above is molded. 請求項１記載の半導体装置の製造方法において、
前記複数の第１および第２リードのそれぞれは、前記連結部分と同じ厚さで形成された端子部を有し、
前記（ｅ）工程では、前記端子部と前記連結部分との間を前記ダイサーで切断することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
Each of the plurality of first and second leads has a terminal portion formed with the same thickness as the connecting portion ;
In the step (e), the dicer is used to cut between the terminal portion and the connecting portion . 請求項２記載の半導体装置の製造方法において、
前記リードフレームは、前記端子部および前記連結部分以外がハーフエッチングされていることを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 2.
The method of manufacturing a semiconductor device, wherein the lead frame is half-etched except for the terminal portion and the connecting portion. 請求項１記載の半導体装置の製造方法において、
前記第１パターンのうち、前記連結部分と対向する辺側には、前記ゲートが設けられており、
前記第２パターンのうち、前記連結部分と対向する辺側には、ダミーキャビティおよびエアベントが形成されていることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
Of the first pattern, the side facing the connecting portion is the gate is provided,
Wherein among the second patterns, the side facing the connecting part, a method of manufacturing a semiconductor device characterized by dummy cavities and d Abento are formed. 請求項１記載の半導体装置の製造方法において、
前記リードフレームは、前記上面と、前記上面とは反対側の下面を有しており、
前記（ｄ）工程では、前記リードフレームの前記下面と前記第２金型との間にシートを配置した状態で、前記リードフレームの前記連結部分および前記外枠部分を前記第１金型と前記第２金型とで挟み込むことを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The lead frame has the upper surface and a lower surface opposite to the upper surface,
In the step (d), in a state where a sheet is disposed between the lower surface of the lead frame and the second mold, the connecting portion and the outer frame portion of the lead frame are connected to the first mold and the second mold. A method of manufacturing a semiconductor device, wherein the semiconductor device is sandwiched between second molds .
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