JP2007208159A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007208159A
JP2007208159A JP2006027849A JP2006027849A JP2007208159A JP 2007208159 A JP2007208159 A JP 2007208159A JP 2006027849 A JP2006027849 A JP 2006027849A JP 2006027849 A JP2006027849 A JP 2006027849A JP 2007208159 A JP2007208159 A JP 2007208159A
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JP
Japan
Prior art keywords
interposer
semiconductor device
semiconductor
semiconductor element
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006027849A
Other languages
Japanese (ja)
Inventor
Shinichi Fujiwara
Ukyo Ikeda
Shosaku Ishihara
Shiro Yamashita
Isamu Yoshida
勇 吉田
志郎 山下
宇亨 池田
昌作 石原
伸一 藤原
Original Assignee
Hitachi Ltd
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, 株式会社日立製作所 filed Critical Hitachi Ltd
Priority to JP2006027849A priority Critical patent/JP2007208159A/en
Publication of JP2007208159A publication Critical patent/JP2007208159A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

A semiconductor device having both functions of a high heat dissipation semiconductor device using a lead frame and an interposer and a multichip semiconductor device having semiconductor elements mounted on both sides of the lead frame is obtained.
A first semiconductor element and a second semiconductor element are mounted above and below a lead frame via an adhesive layer, the first semiconductor element and the second semiconductor element are electrically connected to an interposer, and an upper surface of the interposer is A molded semiconductor device, wherein a lead frame is provided with a plurality of holes, wires are used for connection between the first semiconductor device and the interposer, bumps are used for connection between the second semiconductor device and the interposer, and the first semiconductor device and the interposer The wire used for connection is connected through a hole provided in the lead frame.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a multichip semiconductor device in which semiconductor elements are mounted on both sides of a lead frame.

  In recent years, in response to the demand for higher density and smaller size of a semiconductor device, as one method, two semiconductor elements are mounted on the front and back of a lead frame, and each inner lead and the semiconductor element are connected by wire bonding. Such a structure has been proposed.

  In addition, semiconductor elements tend to increase in calorific value year by year, and the demand for improving heat dissipation has increased. Therefore, a structure as in Patent Document 2 has been proposed in response to demands for higher density, smaller size, and higher heat dissipation. According to Patent Document 2, a first semiconductor element is provided on one side of a metal plate bonded to a lead frame and connected to an inner lead by a wire. A second semiconductor element is also mounted on one of the metal plates, a wiring tape is provided on the circuit forming surface of the second semiconductor element and connected by a wire, and a bump is provided to connect the external substrate and the wiring tape. It has a structure. It is described that the structure of Patent Document 2 can achieve high density and high heat dissipation.

JP-A-8-191129 JP 2002-124623 A

  However, in the method of Patent Document 1, the heat dissipation from the mold resin, which has a lower thermal conductivity than that of metal, and the thermal conductivity transmitted to the wire, the inner lead, and the outer lead are high, but the heat dissipation semiconductor device has only a narrow path and a high heat generation. The structure was unsuitable for mounting.

  Further, in the method of Patent Document 2, heat is spread by a metal plate, but the heat radiation path from the inner lead and outer lead that are signal lines is narrow, and the circuit formation surface of the second semiconductor element is more thermally conductive than metal. There was a limit to heat dissipation due to bumps through low-rate wiring tape.

  An object of the present invention is to provide a high-heat-dissipating and high-density semiconductor device by eliminating the above-mentioned drawbacks of the prior art and directly connecting a heat-dissipation lead mounting a semiconductor element to an external substrate. .

  The semiconductor device of the present invention has a first semiconductor element and a second semiconductor element mounted on the top and bottom of a lead frame via an adhesive layer, and the first semiconductor element and the second semiconductor element are electrically connected to an interposer. A semiconductor device in which the upper surface of the interposer is molded, wherein the lead frame is provided with one or a plurality of holes, wires are used to connect the first semiconductor device and the interposer, and the second semiconductor device and the interposer are connected. The wires used for connecting the first semiconductor device and the interposer using bumps are connected through holes provided in the lead frame.

  In the present invention, a structure in which a plurality of semiconductor elements are mounted can increase the density, and heat can be radiated directly to an external substrate using a lead frame, so that high heat dissipation can be achieved.

  Embodiments of the present invention will be described below.

  FIG. 1 is a schematic sectional view of a first embodiment of the present invention. A first semiconductor element 2 is mounted on the upper surface of the lead frame 1 with a circuit forming surface facing upward via an adhesive layer (not shown), and a second semiconductor element 3 is mounted on the lower surface of the lead frame 1 on the circuit forming surface. It is mounted with an adhesive layer (not shown) facing down. The first semiconductor element 2 is electrically connected to the interposer 5 via the wires 4, and the second semiconductor element 3 is electrically connected to the interposer 5 via the bumps 6. Further, the upper surface of the interposer 5 is protected by a mold resin 7, and external connection bumps 8 are provided on the lower surface of the interposer 5 for connection to an external substrate (not shown). The lead frame 1 is bent like an outer lead of a normal semiconductor device so that the heat generated in the first semiconductor element 2 and the second semiconductor element 3 can be easily connected to the external board via an adhesive member in order to release the heat to the external board. It has a structure. Note that solder, conductive adhesive, or the like is used as the material for the bumps 6 and the external connection bumps 8.

  FIG. 2 is a schematic plan view of the first embodiment of the present invention. The mold resin 7 is not shown in order to make the internal structure easy to see, and instead the area to be sealed is represented by a dotted line. A hole 9 is provided in the lead frame 1, and the wire 4 passes through the hole 9 to connect the first semiconductor element 2 and the interposer 5. If the hole 9 is made large, the path through which heat escapes is reduced and the heat dissipation performance is lowered. Therefore, it is important to make the hole 9 the minimum size through which the wire 9 can pass.

  FIG. 3 is a schematic cross-sectional view when mounted on the external substrate of the first embodiment of the present invention. The lead frame 1 is connected to an external substrate 11 via solder 10. It goes without saying that measures are taken to further diffuse and dissipate heat within the substrate at the location of the external substrate 11 to which the lead frame 1 is connected. Further, although the present invention has been described by the method of connecting the lead frame 1 and the external substrate 11 with solder, it goes without saying that a conductive adhesive may be used.

  By configuring as described above, it is possible to increase the density by incorporating two semiconductor elements in one semiconductor device, and the heat of the semiconductor elements can be directly radiated to the substrate using a lead frame, so that heat is dissipated. It is possible to improve the performance. Furthermore, since the mold resin above and below the lead frame adheres through the hole, the adhesion between the resin above and below the lead frame is improved and the reliability can be improved.

  FIG. 4 is a schematic cross-sectional view of the second embodiment of the present invention. The interposer 5 has an opening 12 that is substantially the same size as the second semiconductor element 3, and the circuit forming surface of the second semiconductor element 3 is exposed from the opening 12, and the external connection bump 8 is formed by the interposer 5. And a circuit forming surface of the second semiconductor element 3 are connected to each other.

  By configuring as described above, the heat of the second semiconductor element can be directly released to the external substrate, so that the heat dissipation can be improved as compared with the first embodiment.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. It is a cross-sectional schematic diagram of the semiconductor device when mounted on the external substrate of the first embodiment of the present invention. It is a cross-sectional schematic diagram of the semiconductor device of the 2nd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Lead frame, 2 ... 1st semiconductor element, 3 ... 2nd semiconductor element, 4 ... Wire, 5 ... Interposer, 6 ... Single layer thin film, 9 ... Hole, 12 ... Opening part.

Claims (5)

  1. A semiconductor in which a first semiconductor element and a second semiconductor element are mounted on the top and bottom of a lead frame via an adhesive layer, the first semiconductor element and the second semiconductor element are electrically connected to an interposer, and the upper surface of the interposer is molded In the device
    A semiconductor device, wherein electrical signals of the first semiconductor element and the second semiconductor element are electrically connected to an external substrate by a connecting member provided on a lower surface of the interposer.
  2. The semiconductor device according to claim 1,
    A semiconductor device using a wire for connecting the first semiconductor device and the interposer and using a bump for connecting the second semiconductor device and the interposer.
  3. The semiconductor module according to claim 1,
    A semiconductor device, wherein the lead frame has one or a plurality of holes.
  4. The semiconductor module according to claim 2,
    A wire used for connecting the first semiconductor device and the interposer is connected through a hole provided in the lead frame.
  5. The semiconductor module according to claim 1,
    A semiconductor device characterized in that an opening having a size equivalent to that of the second semiconductor element is provided in the interposer, and a connection member electrically connected to the external substrate is provided on the lower surface of the interposer and the circuit forming surface of the second semiconductor element. .
JP2006027849A 2006-02-06 2006-02-06 Semiconductor device Pending JP2007208159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006027849A JP2007208159A (en) 2006-02-06 2006-02-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006027849A JP2007208159A (en) 2006-02-06 2006-02-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2007208159A true JP2007208159A (en) 2007-08-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006027849A Pending JP2007208159A (en) 2006-02-06 2006-02-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2007208159A (en)

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WO2009020037A1 (en) 2007-08-09 2009-02-12 Nec Lighting, Ltd. Illuminating device
JP2013535825A (en) * 2010-07-19 2013-09-12 テッセラ,インコーポレイテッド Stackable mold microelectronic package with area array unit connector
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
EP2650917A3 (en) * 2012-04-09 2016-10-12 Canon Kabushiki Kaisha Multilayered semiconductor device, printed circuit board, and method of manufacturing multilayered semiconductor device
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9917073B2 (en) 2012-07-31 2018-03-13 Invensas Corporation Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
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US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires

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US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
WO2009020037A1 (en) 2007-08-09 2009-02-12 Nec Lighting, Ltd. Illuminating device
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
CN106129041A (en) * 2010-07-19 2016-11-16 德塞拉股份有限公司 There is the stackable molding microelectronics Packaging of face array element connector
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
JP2013535825A (en) * 2010-07-19 2013-09-12 テッセラ,インコーポレイテッド Stackable mold microelectronic package with area array unit connector
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
EP2650917A3 (en) * 2012-04-09 2016-10-12 Canon Kabushiki Kaisha Multilayered semiconductor device, printed circuit board, and method of manufacturing multilayered semiconductor device
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US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
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US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
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US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
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