JP2007208159A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007208159A
JP2007208159A JP2006027849A JP2006027849A JP2007208159A JP 2007208159 A JP2007208159 A JP 2007208159A JP 2006027849 A JP2006027849 A JP 2006027849A JP 2006027849 A JP2006027849 A JP 2006027849A JP 2007208159 A JP2007208159 A JP 2007208159A
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Prior art keywords
interposer
semiconductor
semiconductor device
semiconductor element
lead frame
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JP2006027849A
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Japanese (ja)
Inventor
Shinichi Fujiwara
Ukyo Ikeda
Shosaku Ishihara
Shiro Yamashita
Isamu Yoshida
勇 吉田
志郎 山下
宇亨 池田
昌作 石原
伸一 藤原
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Hitachi Ltd
株式会社日立製作所
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Priority to JP2006027849A priority Critical patent/JP2007208159A/en
Publication of JP2007208159A publication Critical patent/JP2007208159A/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for combining both functions of a semiconductor device with high heat dissipation using a lead frame and an interposer and a multi-chip semiconductor device mounted with a semiconductor element on both sides of a lead frame.
SOLUTION: The semiconductor element is provided, wherein the first and second semiconductor elements are mounted on and under the lead frame via an adhesive layer, the first and second semiconductor elements are electrically connected to the interposer, and an upper side of the interposer is molded. A plurality of holes are formed to the lead frame, wires are used for the connection between the first semiconductor element and the interposer, bumps are used for the connection between the second semiconductor element and the interposer, and the wires used for the connection between the first semiconductor element and the interposer are connected through the holes formed to the lead frame.
COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に係り、特にリードフレームの両面に半導体素子を搭載するマルチチップ型半導体装置に関する。 The present invention relates to a semiconductor device, particularly to a multi-chip type semiconductor device for mounting a semiconductor element on both sides of the lead frame.

近年、半導体装置の高密度化、小型化への要求に対して、1つの方法として二つの半導体素子をリードフレームの表裏に搭載し各インナリードと半導体素子をワイヤボンディングにより接続する特許文献1のような構造が提案されている。 Recently, density of semiconductor device, the request for miniaturization, in Patent Document 1 each inner lead and the semiconductor element is mounted on the front and back of a single leadframe two semiconductor devices as a way to connect by wire bonding structures have been proposed, such as.

また、半導体素子は、年々発熱量が増加する傾向にあり放熱性向上の要求も高まってきた。 Further, the semiconductor device has been increased demand for there radiating improvement tends to yearly heating value increases. そこで高密度化、小型化、高放熱性化の要求に対して特許文献2のような構造が提案されている。 Therefore densification, miniaturization, the structure of Patent Document 2 has been proposed for the request of the high heat radiation of. 特許文献2によると、リードフレームに張り合わされた金属板の片面に第一の半導体素子を設けインナリードとワイヤにより接続する。 According to Patent Document 2, connected by inner lead wire is provided a first semiconductor element on one side of the metal plate glued to the lead frame. そして、金属板の一方にも第二の半導体素子を搭載し、その第二の半導体素子の回路形成面に配線テープを設けワイヤにより接続し、外部基板と配線テープの接続にバンプを設けている構造となっている。 Then, in one of the metal plate equipped with the second semiconductor element, and connected by its second semiconductor wire provided wiring tape to the circuit forming surface of the element, and a bump provided on the connection of the external substrate and the wiring tape and it has a structure. 特許文献2の構造とすることにより、高密度化、高放熱化が図れることが記載されている。 By the structure of Patent Document 2, it is described that high density, high heat dissipation can be achieved.

特開平8−191129号公報 JP-8-191129 discloses 特開2002−124623号公報 JP 2002-124623 JP

しかし、特許文献1の方法では、金属に比べて熱伝導率が低いモールド樹脂からの放熱とワイヤ、インナリード、アウタリードと伝わる熱伝導率は高いが放熱経路が狭い経路しかなく高発熱の半導体素子の搭載には不向きな構造であった。 However, in the method of Patent Document 1, the heat dissipation and the wire from the low thermal conductivity mold resin as compared with the metal, the inner leads, the thermal conductivity transmitted and outer leads is high there is only a narrow path radiation path highly exothermic semiconductor elements It was an unsuitable structure for mounting on.

また、特許文献2の方法では、金属板で熱を広げているが信号線であるインナリード、アウタリードからの放熱経路は狭く、且つ第二の半導体素子の回路形成面に金属に比べて熱伝導率の低い配線テープを介してバンプがあるために放熱性に限界があった。 Further, in the method of Patent Document 2, are spread heat in the metal plate but the inner lead is a signal line, the heat dissipation path from the outer lead is narrow, and the thermal conductivity as compared with metal circuit formation surface of the second semiconductor device there is a limit in heat dissipation properties because of the bumps through a rate lower wiring tape.

本発明の目的は、上記した従来技術の欠点を解消し、半導体素子を搭載している放熱リードを外部基板に直接接続することにより、高放熱性な高密度の半導体装置を提供することにある。 An object of the present invention is to overcome the disadvantages of the prior art described above, by connecting directly to the heat dissipation leads mounted with the semiconductor device to an external substrate is to provide a high heat radiation, high density semiconductor device .

本発明の半導体装置は、リードフレームの上下に接着層を介して第一半導体素子と第二半導体素子とを搭載し、前記第一半導体素子と第二半導体素子とをインターポーザと電気的に接続させ、インターポーザ上面をモールドした半導体装置であって、前記リードフレームには一つもしくは複数の孔を設け、前記第一半導体装置とインターポーザの接続にワイヤを用い、前記第二半導体装置とインターポーザの接続にバンプを用い、前記第一半導体装置とインターポーザの接続に用いるワイヤは、前記リードフレームに設けられた孔を通って接続されているものである。 The semiconductor device of the present invention is equipped with the first semiconductor element and the second semiconductor element through the bonding layer and below the lead frame, electrically to connect the interposer and the first semiconductor element and the second semiconductor device , a semiconductor device obtained by molding the interposer top, the provided one or more holes in the lead frame, using a wire connection of the first semiconductor device and the interposer, the connection of the second semiconductor device and the interposer using bumps, wire used for connection of the first semiconductor device and the interposer are those which are connected through a hole provided in the lead frame.

本発明では複数の半導体素子を搭載した構造にすることにより高密度化、リードフレームを用いて直接外部基板に放熱することができるので高放熱化が図ることができる。 Densification by a mounting structure of the plurality of semiconductor elements in the present invention, it is possible to high heat dissipation of that achieved because it can be radiated directly to the external substrate by using a lead frame.

以下、本発明の実施の形態を説明する。 Hereinafter, an embodiment of the present invention.

図1は本発明の第一の実施例の断面模式図である。 Figure 1 is a schematic cross-sectional view of a first embodiment of the present invention. リードフレーム1の上面には第一半導体素子2が回路形成面を上にして接着剤層(図示せず)を介して搭載され、リードフレーム1の下面には第二半導体素子3が回路形成面を下にして接着剤層(図示せず)を介して搭載されている。 The upper surface of the lead frame 1 is first semiconductor element 2 is mounted via an adhesive layer (not shown) in the top circuit forming surface, the second semiconductor element 3 is the circuit forming surface to the lower surface of the lead frame 1 It is mounted via an adhesive layer (not shown) and down. また、第一半導体素子2はワイヤ4を介してインターポーザ5と電気的に接続されており、第二半導体素子3はバンプ6を介してインターポーザ5と電気的に接続されている。 The first semiconductor element 2 is electrically connected to the interposer 5 through the wire 4, the second semiconductor element 3 is electrically connected to the interposer 5 through the bump 6. さらに、インターポーザ5の上面はモールド樹脂7で保護されており、インターポーザ5の下面には外部基板(図示せず)との接続用に外部接続用バンプ8が設けられている。 Furthermore, the upper surface of the interposer 5 is protected by the mold resin 7, on the lower surface of the interposer 5 external connection bumps 8 are provided for connection with an external substrate (not shown). リードフレーム1は、第一半導体素子2と第二半導体素子3で発生する熱を外部基板に逃がすために外部基板と接着部材を介して接続しやすいように通常の半導体装置のアウタリードのように曲折した構造になっている。 The lead frame 1 is bent as in the outer lead of the first semiconductor element 2 and the conventional semiconductor device to make it easier to connect through the external substrate and the adhesive member to release heat generated in the second semiconductor element 3 to the external substrate It has become the structure. なお、バンプ6、外部接続用バンプ8の材料にははんだや導電性接着剤などを用いる。 Incidentally, the bumps 6, the material of the external connection bumps 8 using solder or a conductive adhesive.

図2は本発明の第一の実施例の平面模式図である。 Figure 2 is a schematic plan view of a first embodiment of the present invention. モールド樹脂7は内部構造を見やすくするために図示せず、その代わり封止するエリアを点線で表している。 Molding resin 7 is not shown for the sake of clarity the internal structure, and represents an area for alternatively sealing by a dotted line. リードフレーム1には孔9が設けられており、ワイヤ4は孔9の中を通って第一半導体素子2とインターポーザ5を接続している。 The lead frame 1 has holes 9 are provided, the wire 4 is connected to the first semiconductor element 2 and the interposer 5 through the inside of the hole 9. 孔9は、大きくすると熱の逃げる経路が少なくなり放熱性が低下するためワイヤ9を通す必要最低限の大きさにすることが重要である。 Hole 9, it is important that the route is reduced heat dissipation escape of heat is the minimum size through the wire 9 to lower by increasing.

図3は本発明の第一の実施例の外部基板に搭載された時の断面模式図である。 Figure 3 is a schematic sectional view when mounted on the external substrate of the first embodiment of the present invention. リードフレーム1ははんだ10を介して外部基板11に接続されている。 Lead frame 1 is connected to the external substrate 11 through the solder 10. リードフレーム1が接続される外部基板11の箇所には、基板内でさらに熱を拡散、放熱するために対策を採ることは言うまでもない。 The portion of the external substrate 11 where the lead frame 1 is connected, further diffuse the heat in the substrate, it is of course to take measures for dissipating. また、本発明ははんだによりリードフレーム1と外部基板11とを接続する方法で説明したが、導電性接着剤を用いても良いことは言うまでもない。 Further, the present invention has been described in the method of connecting the lead frame 1 and the external substrate 11 by the solder, it goes without saying that even by using a conductive adhesive.

上記のように構成することにより、2つの半導体素子を1つの半導体装置に内蔵することにより高密度化が図れ、また半導体素子の熱はリードフレームを用いて直接基板に放熱させることができるので放熱性の向上を図ることができる。 By configuring as described above, two semiconductor devices Hakare densification by incorporated in a single semiconductor device, also the heat of the semiconductor element can be dissipated to the substrate directly by using the lead frame radiator it is possible to improve the resistance. さらに、孔を通してリードフレーム上下のモールド樹脂が密着するのでリードフレーム上下の樹脂間の密着性が向上し信頼性を向上させることができる。 Furthermore, it is possible to improve the improved adhesion between the lead frame and below the resin reliability since the lead frame and below the molding resin are in close contact through the hole.

図4は本発明の第二の実施例の断面模式図である。 Figure 4 is a cross-sectional schematic view of a second embodiment of the present invention. インターポーザ5には第二半導体素子3とほぼ同等な大きさで開口部12があり、その開口部12から第二半導体素子3の回路形成面が露出しており、外部接続用バンプ8はインターポーザ5の下面と第二半導体素子3の回路形成面上に接続されている構造になっている。 The interposer 5 has openings 12 at substantially equal size and the second semiconductor element 3, through the opening 12 and the circuit forming surface of the second semiconductor element 3 is exposed, the external connection bumps 8 interposer 5 It has a structure in which the lower surface of the connected on the circuit formation surface of the second semiconductor element 3.

上記のように構成することにより、第二半導体素子の熱を外部基板に直接逃がすことができるので第一の実施例に比べて放熱性が向上することができる。 By configuring as described above, heat dissipation can be improved as compared with the first embodiment it is possible to escape directly heat the second semiconductor element to the external board.

本発明の第一の実施例の半導体装置の断面模式図である。 It is a schematic cross-sectional view of a semiconductor device of the first embodiment of the present invention. 本発明の第一の実施例の半導体装置の平面模式図である。 It is a schematic plan view of a semiconductor device of the first embodiment of the present invention. 本発明の第一の実施例の外部基板に搭載されて時の半導体装置の断面模式図である。 It is a schematic cross-sectional view of a semiconductor device during being mounted on an external substrate of the first embodiment of the present invention. 本発明の第二の実施例の半導体装置の断面模式図である。 It is a schematic cross-sectional view of a semiconductor device of the second embodiment of the present invention.

符号の説明 DESCRIPTION OF SYMBOLS

1…リードフレーム、2…第一半導体素子、3…第二半導体素子、4…ワイヤ、5…インターポーザ、6…一層目薄膜、9…孔、12…開口部。 1 ... lead frame, 2 ... first semiconductor element, 3 ... second semiconductor element, 4 ... wire, 5 ... interposer, 6 ... first layer thin film, 9 ... hole, 12 ... opening.

Claims (5)

  1. リードフレームの上下に接着層を介して第一半導体素子と第二半導体素子とを搭載し、前記第一半導体素子と第二半導体素子とをインターポーザと電気的に接続させ、インターポーザ上面をモールドした半導体装置において、 Mounting a first semiconductor element and the second semiconductor element through the bonding layer and below the lead frame, an interposer electrically connected to the said first semiconductor element and the second semiconductor element, a semiconductor obtained by molding the interposer top in the device,
    前記第一半導体素子と第二半導体素子の電気信号をインターポーザ下面に設置された接続部材によって外部基板に電気的に接続されていることを特徴とする半導体装置。 Wherein a being electrically connected to the external substrate by the first semiconductor element and the connecting member an electrical signal which is placed on the interposer lower surface of the second semiconductor element.
  2. 請求項1記載の半導体装置において、 The semiconductor device according to claim 1,
    前記第一半導体装置とインターポーザの接続にワイヤを用い、前記第二半導体装置とインターポーザの接続にバンプを用いたことを特徴とする半導体装置。 Wherein a said using the wire to the first semiconductor device and the interposer connection using bumps to connect the second semiconductor device and the interposer.
  3. 請求項1記載の半導体モジュールにおいて、 The semiconductor module according to claim 1,
    前記リードフレームに一つもしくは複数の孔を有することを特徴とする半導体装置。 Wherein a has one or more holes in the lead frame.
  4. 請求項2記載の半導体モジュールにおいて、 The semiconductor module according to claim 2,
    前記第一半導体装置とインターポーザの接続に用いるワイヤは、前記リードフレームに設けられた孔を通って接続されていることを特徴とする半導体装置。 The wire used for the connection of the first semiconductor device and the interposer, a semiconductor device characterized by being connected through a hole provided in the lead frame.
  5. 請求項1記載の半導体モジュールにおいて、 The semiconductor module according to claim 1,
    インターポーザに第二半導体素子と同等な大きさの開口部を有し、外部基板と電気的に接続する接続部材をインターポーザ下面と第二半導体素子の回路形成面に設けたことを特徴とする半導体装置。 An opening of the second semiconductor element and the comparably sized on the interposer, a semiconductor device which is characterized by providing a connecting member for connecting the external substrate and electrically to the circuit forming surface of the interposer lower surface and the second semiconductor device .
JP2006027849A 2006-02-06 2006-02-06 Semiconductor device Pending JP2007208159A (en)

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