JP2642359B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2642359B2 JP2642359B2 JP62226307A JP22630787A JP2642359B2 JP 2642359 B2 JP2642359 B2 JP 2642359B2 JP 62226307 A JP62226307 A JP 62226307A JP 22630787 A JP22630787 A JP 22630787A JP 2642359 B2 JP2642359 B2 JP 2642359B2
- Authority
- JP
- Japan
- Prior art keywords
- tape carrier
- leads
- carrier packages
- lead
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数のテープキャリアパッケージを重ね実装
するようにした半導体装置に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device in which a plurality of tape carrier packages are stacked and mounted.
半導体素子の組込技術の一つに、テープキャリア方式
がある。この方式は、フィルムキャリアあるいはTAB（T
ape Automated Bonding）方式などとも称されている。
この方式は、長尺のスプロケットホール（パーフォレー
ションホール）付きの樹脂製テープに半導体素子を連続
的に組込んでいく方法で、当該テープキャリアは半導体
素子（チップ）の電極配置に合わせたリードパターン
が、スプロケットホールとデバイスホールを持つ樹脂フ
ィルム上に形成されたもので、例えば、接着剤付きポリ
イミドフィルムを適宜幅にスリットし、それに送り用の
スプロケットホールとチップを組込みするためのデバイ
スホールとをパンチングし、銅箔をラミネートし、ホト
レジスト技術、エッチング技術を用いて所望のリードパ
ターンを形成する工程を経て製造される。One of the techniques for incorporating semiconductor elements is a tape carrier method. This method uses a film carrier or TAB (T
ape Automated Bonding) method.
In this method, semiconductor elements are continuously incorporated into a resin tape having a long sprocket hole (perforation hole). The tape carrier has a lead pattern that matches the electrode arrangement of the semiconductor element (chip). Formed on a resin film having sprocket holes and device holes, for example, slitting a polyimide film with an adhesive to an appropriate width, and punching a sprocket hole for feeding and a device hole for incorporating a chip. Then, it is manufactured through a process of laminating a copper foil and forming a desired lead pattern using a photoresist technique and an etching technique.
なお、当該テープキャリアについて述べた文献の例と
しては、マックグローヒルブックカンパニージャパン
（Mc Graw−Hill Book Company Japan）社刊1983年コピ
ーライト「VLSI TECHNOLOGY」p558があげられる。An example of a document describing the tape carrier is 1983 "Copyright" VLSI TECHNOLOGY "p558 published by McGraw-Hill Book Company Japan.
しかるに、従来のテープキャリアにあっては、１品種
１レイアウトとなっており、同じパターンを持っている
ために同品種のテープキャリアを重ねて実装用基板に実
装することができない。However, the conventional tape carrier has one type and one layout, and since it has the same pattern, it is not possible to stack tape carriers of the same type and mount them on a mounting board.
そのため、高密度に実装しようとしたら、実装用基板
上に同品種のテープキャリアと並べて配設することが必
要となり、プリント配線基板などの実装用基板表面の配
線を複雑化させ、断線なども生じ易くなり、その信頼性
を低下させることになる。For this reason, when mounting at high density, it is necessary to arrange tape carriers of the same type side by side on the mounting board, which complicates the wiring on the surface of the mounting board such as a printed wiring board and causes disconnection. It becomes easier and its reliability is reduced.
本発明の目的は、テープキャリアパッケージを重ねて
実装し得るようにして高密度実装することができる技術
を提供することにある。An object of the present invention is to provide a technique capable of high-density mounting by allowing tape carrier packages to be mounted one on top of the other.
本発明の前記ならびにそのほかの目的と新規な特徴
は、本明細書の記述および添付図面から明らかになるで
あろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概
要を簡単に説明すれば、下記のとおりである。The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
すなわち、本発明の半導体装置は、デバイスホールを
有するフィルムテープと、前記フィルムテープに形成さ
れた前記デバイスホールに一部が突出する複数のリード
と、前記複数のリードに接合された半導体チップと、前
記複数のリードのインナー部および前記半導体チップを
封止する樹脂製の封止部とをそれぞれ備えてなる複数の
テープキャリアパッケージと、前記それぞれのテープキ
ャリアパッケージが重ねられた状態で実装される実装用
基板とからなり、前記それぞれのテープキャリアパッケ
ージの前記封止部から突出する複数のリードパターン
が、前記それぞれのテープキャリアパッケージで相違し
たパターンに形成され、前記それぞれのテープキャリア
パッケージの封止部から突出する前記複数のリードの外
方端に折り曲げ部が形成され、前記それぞれのテープキ
ャリアパッケージの封止部から突出する前記複数のリー
ドの前記折り曲げ部を重ねた状態で、前記それぞれのテ
ープキャリアパッケージが前記リードの前記折り曲げ部
により前記実装用基板に保持され、前記それぞれのテー
プキャリアパッケージに共通する信号が入出力されるリ
ードの導通を前記複数のリードを折り曲げ部によって行
うようにしたことを特徴とする。That is, the semiconductor device of the present invention is a film tape having a device hole, a plurality of leads partially projecting into the device hole formed in the film tape, a semiconductor chip joined to the plurality of leads, A plurality of tape carrier packages each including an inner portion of the plurality of leads and a resin sealing portion for sealing the semiconductor chip; and a mounting in which the respective tape carrier packages are mounted in a stacked state. A plurality of lead patterns projecting from the sealing portion of each of the tape carrier packages, are formed in different patterns in the respective tape carrier packages, and the sealing portions of the respective tape carrier packages are formed. A bent portion is formed at an outer end of the plurality of leads protruding from The respective tape carrier packages are held on the mounting substrate by the bent portions of the leads in a state where the bent portions of the plurality of leads projecting from the sealing portions of the respective tape carrier packages are overlapped. The leads for inputting and outputting signals common to the respective tape carrier packages are electrically connected to each other by bending the plurality of leads.
上記のように、リードのインナー部と半導体チップと
が樹脂により封止されて形成された各々のテープキャリ
アパッケージは、それぞれのテープキャリアパッケージ
の封止部から突出する複数のリードパターンが相違して
形成されており、重ね実装が可能となることから、半導
体チップの高密度実装が可能となり、配線も簡素化され
て装置の信頼性も向上させることができる。そして、各
々のテープキャリアパッケージはリードの折り曲げ部を
重ねた状態で実装用基板に保持されるので、複数のテー
プキャリアパッケージを一括して接合して実装用基板に
実装することができ、半導体装置を迅速に製造すること
が可能となる。As described above, each tape carrier package formed by sealing the inner portion of the lead and the semiconductor chip with the resin is different in a plurality of lead patterns projecting from the sealing portion of each tape carrier package. Since it is formed and can be mounted in a stack, high-density mounting of semiconductor chips is possible, wiring is simplified, and the reliability of the device can be improved. Further, since each tape carrier package is held on the mounting substrate with the bent portion of the lead overlapped, a plurality of tape carrier packages can be collectively joined and mounted on the mounting substrate. Can be manufactured quickly.
次に、本発明の実施例を図面に基づき説明する。第１
図は本発明の実施例を示す原理図であり、プラスチック
フィルムテープに穿設されたデバイスホール１内には当
該フィルムテープ上に形成されたリードパターン２の一
部が突出している。また、当該リードパターン２のう
ち、第１図（Ａ）における図示上右端のリード2a1が残
りのリード2bに並行に設けられているのに対し、第１図
（Ｂ）では、図示上右端のリード2a2が直角に折れ曲っ
た形となっている。このデバイスホール１内には、図示
していないが半導体素子が組込みされ、第１図（Ａ）で
は図示右端のリード2a1が当該デバイスホール１内に組
込した半導体素子（チップ）のチップセレクト信号用の
リードとなっており、また、第１図（Ｂ）では上右端の
直角に折り曲がったリード2a2が同様にチップセレクト
信号用のリードとなっている。Next, embodiments of the present invention will be described with reference to the drawings. First
FIG. 1 is a principle view showing an embodiment of the present invention. A part of a lead pattern 2 formed on a film tape protrudes into a device hole 1 formed in a plastic film tape. In the lead pattern 2, the lead 2a 1 at the upper right in FIG. 1A is provided in parallel with the remaining lead 2b, whereas the lead 2a in FIG. Lead 2a 2 is bent at a right angle. Although not shown, a semiconductor element (not shown) is incorporated in the device hole 1. In FIG. 1 (A), a lead 2a 1 at the right end in the figure is used to select a chip of the semiconductor element (chip) incorporated in the device hole 1. has a lead signal, also leads 2a 2 that bent at right angles of the upper right end in FIG. 1 (B) is likewise a lead for the chip select signal.
第１図（Ｃ）は、このように各リードパターン２の一
部の2a1,2a2を変更してこれらを変更リードとしたテー
プキャリアを重ね実装した様子を概念的に示したもの
で、リード2a1は重ね実装された上部のチップの当該チ
ップセレクト信号の入出力をつかさどり、また、リード
2a1に隣接したリード2a2は、重ね実装された下部のチッ
プの当該チップセレクト信号の入出力をつかさどるよう
になっている。FIG. 1 (C) conceptually shows a state in which a part of each lead pattern 2 is changed 2a 1 and 2a 2 and tape carriers having these changed leads are stacked and mounted. Lead 2a 1 controls the input / output of the chip select signal of the upper chip mounted on top of
Leads 2a adjacent to 2a 1 2 is adapted to govern the input and output of the chip select signal at the bottom of the chip which is superimposed implemented.
他のリード2bは、各チップに共通の入出力端子となっ
ている。第２図は、第１図（Ａ）のテープキャリアの詳
細を示したもので、また、第３図は第１図（Ｂ）のテー
プキャリアの詳細を示す。The other lead 2b is an input / output terminal common to each chip. FIG. 2 shows details of the tape carrier of FIG. 1 (A), and FIG. 3 shows details of the tape carrier of FIG. 1 (B).
これらの図に示すように、プラスチックフィルムテー
プ３の両端部には、当該テープ３の送りおよび位置合わ
せ用の複数のスプロケットホール４が適宜間隔を置いて
孔設され、また、当該テープ３の中央部には半導体素子
を組込むためのデバイスホール１が穿設され、当該デバ
イスホール１内に突出したリードパターン２の先端部
に、図示するようにチップ５をフェイスダウンボンディ
ング（ギャングボンディング）により接合する。As shown in these figures, at both ends of the plastic film tape 3, a plurality of sprocket holes 4 for feeding and positioning the tape 3 are provided at appropriate intervals, and a center of the tape 3 is provided. A device hole 1 for incorporating a semiconductor element is formed in the portion, and a chip 5 is bonded to the tip of a lead pattern 2 protruding into the device hole 1 by face-down bonding (gang bonding) as shown in the figure. .
この接合は、チップ５の電極部にバンプ６を形成し
て、熱圧着法により行われるが、リードパターン２側に
バンプ６を形成して同様に行ってもよい。当該チップ５
のボンディング（インナーリードボンディング）後に、
第４図断面図に示すように、封止樹脂をポッティングし
て樹脂封止部７を形成して封止を行なう。リードパター
ン２のうち、この樹脂封止部７から外方に突出した部分
がアウター部となり、樹脂封止部７により半導体素子
（チップ）とともに封止された部分がインナー部とな
る。This bonding is performed by forming the bumps 6 on the electrode portions of the chip 5 and performing thermocompression bonding. Alternatively, the bonding may be performed by forming the bumps 6 on the lead pattern 2 side. The chip 5
After bonding (inner lead bonding)
As shown in the sectional view of FIG. 4, a sealing resin is potted to form a resin sealing portion 7 for sealing. The portion of the lead pattern 2 that protrudes outward from the resin sealing portion 7 becomes an outer portion, and the portion sealed by the resin sealing portion 7 together with the semiconductor element (chip) becomes an inner portion.
このように封止されたテープキャリアパッケージ８
を、第５図に示すように実装用基板９上に重ね実装す
る。Tape carrier package 8 thus sealed
Are mounted on the mounting substrate 9 as shown in FIG.
第５図にて、上部テープキャリアパッケージ8aは、第
１図（Ａ）に示すリードパターン２をもつテープキャリ
アパッケージで、また、下部テープキャリアパッケージ
8bは第１図（Ｂ）に示すリードパターン２をもつテープ
キャリアパッケージである。In FIG. 5, an upper tape carrier package 8a is a tape carrier package having the lead pattern 2 shown in FIG.
8b is a tape carrier package having the lead pattern 2 shown in FIG. 1 (B).
第５図に示すように、リードのうちそれぞれのテープ
キャリアパッケージ8a,8bの封止部から突出したアウタ
ー部の外方端には折り曲げ部2c1,2c2が形成されてお
り、それぞれの折り曲げ部2c1,2c2によりそれぞれのテ
ープキャリアパッケージ8a,8bが実装用基板９に電気的
に接合されて実装される。As shown in FIG. 5, bent portions 2c 1 and 2c 2 are formed at the outer ends of the outer portions of the leads that protrude from the sealing portions of the respective tape carrier packages 8a and 8b. The tape carrier packages 8a and 8b are electrically connected to the mounting substrate 9 and mounted by the units 2c 1 and 2c 2 .
本発明に使用されるプラスチックフィルムテープは、
例えばポリイミド系樹脂フィルムを適宜幅にスリットさ
れたものにより構成される。リードパターン２は、当該
フィルムテープ上に例えば銅箔をラミネートし、ホトレ
ジスト技術やエッチング技術を用いて形成することがで
き、各テープキャリアパッケージ8a,8bに応じてその一
部のレイアウトを変更するようにする。Plastic film tape used in the present invention,
For example, it is configured by slitting a polyimide resin film to an appropriate width. The lead pattern 2 can be formed by laminating, for example, a copper foil on the film tape and using a photoresist technique or an etching technique. The layout of a part of the lead pattern 2 is changed according to each tape carrier package 8a, 8b. To
半導体素子（チップ）５は、例えばシリコン単結晶基
板から成り、周知の技術によってこのチップ内には多数
の回路素子が形成され、１つの回路機能が与えられてい
る。回路素子の具体例は、例えばMOSトランジスタから
成り、これらの回路素子によって、例えば論理回路およ
びメモリの回路機能が形成されている。バンプ６は、例
えば金（Au）バンプにより構成される。The semiconductor element (chip) 5 is made of, for example, a silicon single crystal substrate, and a number of circuit elements are formed in the chip by a well-known technique to provide one circuit function. Specific examples of the circuit elements include, for example, MOS transistors, and these circuit elements form, for example, circuit functions of a logic circuit and a memory. The bump 6 is made of, for example, a gold (Au) bump.
封止に使用されるポッティング樹脂には、例えばエポ
キシ樹脂を主体としたポッティング液が用いられる。実
装用基板９は、例えばプリント配線基板により構成され
る。As the potting resin used for sealing, for example, a potting liquid mainly containing an epoxy resin is used. The mounting substrate 9 is formed of, for example, a printed wiring board.
本発明によれば、上記実施例に示すように、各リード
パターン２の一部のリードを相互にパターンが相違した
変更リード2a1,2a2とすることにより、二個のテープキ
ャリアパッケージ8a,8bを実装用基板９上に仮に当該テ
ープキャリアパッケージ8a,8bを並設する場合に比して
実装密度を向上させることができ、また、テープキャリ
アパッケージ8a,8bを並設する場合には配線も長く、複
雑化するのに対し短く、簡略化され、断線する割合も低
減され、信頼性の向上に寄与する点大である。According to the present invention, as shown in the above embodiment, some of the leads of each lead pattern 2 are changed leads 2a 1 and 2a 2 having different patterns from each other, so that two tape carrier packages 8a, The mounting density can be improved as compared with the case where the tape carrier packages 8a and 8b are arranged side by side on the mounting substrate 9 when the tape carrier packages 8a and 8b are arranged side by side. In addition, the length is longer and more complicated, but shorter, simplified, and the rate of disconnection is reduced, contributing to improvement in reliability.
以上発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Absent.
例えば、上記実施例ではテープキャリアパッケージを
実装用基板上に二個重ね実装する例を示したが、三個以
上重ねることができ、場合により実装用基板の両面にそ
れぞれ重ね実装することもできる。For example, in the above embodiment, two tape carrier packages are mounted on the mounting substrate, but three or more tape carrier packages can be mounted on the mounting substrate, and may be mounted on both surfaces of the mounting substrate.
本願において開示される発明のうち代表的なものによ
って得られる効果を簡単に説明すれば、下記のとおりで
ある。The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.
本発明によれば、各々のパッケージは相互にリードパ
ターンが相違しており、重ね実装が可能となることか
ら、半導体チップの高密度実装が可能となり、配線も簡
素化されて装置の信頼性を向上させることができる。ま
た、重ね実装される各々のパッケージは、リードのアウ
ター部によりその折り曲げ部を重ねた状態として実装用
基板に保持されるので、複数のパッケージを一括して実
装用基板に接合することができ、半導体装置を容易かつ
迅速に製造することができる。According to the present invention, since each package has a different lead pattern from each other and can be stacked and mounted, high-density mounting of semiconductor chips is possible, wiring is simplified, and reliability of the device is improved. Can be improved. In addition, since each package to be stacked and mounted is held on the mounting substrate in a state where the bent portion is overlapped by the outer portion of the lead, a plurality of packages can be collectively joined to the mounting substrate, A semiconductor device can be manufactured easily and quickly.
第１図（Ａ）〜（Ｃ）はそれぞれ本発明の実施例を示す
原理図、 第２図は本発明の実施例を示す要部平面図、 第３図は本発明の実施例を示す要部平面図、 第４図は本発明の実施例を示す断面図、 第５図は本発明の実施例を示す断面図である。 １……デバイスホール、２……リードパターン、2a1,2a
2……変更リード、2b……共通リード、2c1,2c2……折り
曲げ部、３……プラスチックフィルムテープ、４……ス
プロケットホール、５……半導体素子（チップ）、６…
…バンプ、７……樹脂封止部、8,8a,8b……テープキャ
リアパッケージ、９……実装用基板。1 (A) to 1 (C) are each a principle view showing an embodiment of the present invention, FIG. 2 is a plan view of a main part showing an embodiment of the present invention, and FIG. 3 is a plan view showing an embodiment of the present invention. FIG. 4 is a sectional view showing an embodiment of the present invention. FIG. 5 is a sectional view showing an embodiment of the present invention. 1 ... device hole, 2 ... lead pattern, 2a 1 , 2a
2 ...... change leads, 2b ...... common lead, 2c 1, 2c 2 ...... bent portion, 3 ...... plastic film tape, 4 ...... sprocket holes, 5 ...... semiconductor element (chip), 6 ...
... Bump, 7 ... Resin sealing part, 8,8a, 8b ... Tape carrier package, 9 ... Mounting board.
フロントページの続き (72)発明者 若島 喜昭 東京都小平市上水本町1450番地 株式会 社日立製作所武蔵工場内 (56)参考文献 特開 昭63−18654（ＪＰ，Ａ) 特開 平１−293556（ＪＰ，Ａ) 特開 昭62−142394（ＪＰ，Ａ)Continuation of front page (72) Inventor Yoshiaki Wakajima 1450, Kamisumihonmachi, Kodaira-shi, Tokyo Inside Musashi Plant of Hitachi, Ltd. (56) References JP-A-63-18654 (JP, A) JP-A-1-293556 (JP, A) JP-A-62-142394 (JP, A)
Claims (4)
と、前記フィルムテープに形成された前記デバイスホー
ルに一部が突出する複数のリードと、前記複数のリード
に接合された半導体チップと、前記複数のリードのイン
ナー部および前記半導体チップを封止する樹脂製の封止
部とをそれぞれ備えてなる複数のテープキャリアパッケ
ージと、 前記それぞれのテープキャリアパッケージが重ねられた
状態で実装される実装用基板とからなり、 前記それぞれのテープキャリアパッケージの前記封止部
から突出する複数のリードパターンが、前記それぞれの
テープキャリアパッケージで相違したパターンに形成さ
れ、 前記それぞれのテープキャリアパッケージの前記封止部
から突出する前記複数のリードの外方端に折り曲げ部が
形成され、 前記それぞれのテープキャリアパッケージの前記封止部
から突出する前記複数のリードの前記折り曲げ部を重ね
た状態で、前記それぞれのテープキャリアパッケージが
前記リードの前記折り曲げ部により前記実装用基板に保
持され、 前記それぞれのテープキャリアパッケージに共通する信
号が入出力されるリードの導通を前記複数のリードを折
り曲げ部によって行うようにしたことを特徴とする半導
体装置。1. A film tape having a device hole, a plurality of leads partially projecting into the device hole formed in the film tape, a semiconductor chip joined to the plurality of leads, and the plurality of leads. A plurality of tape carrier packages each including an inner portion and a resin sealing portion for sealing the semiconductor chip; and a mounting substrate on which the respective tape carrier packages are mounted in a stacked state. A plurality of lead patterns protruding from the sealing portion of the respective tape carrier packages are formed in different patterns in the respective tape carrier packages, and protruding from the sealing portions of the respective tape carrier packages. A bent portion is formed at an outer end of the plurality of leads, The respective tape carrier packages are held on the mounting substrate by the bent portions of the leads in a state where the bent portions of the plurality of leads projecting from the sealing portion of each tape carrier package are overlapped. A semiconductor device, wherein conduction of a lead through which a signal common to the respective tape carrier packages is input / output is performed by bending the plurality of leads.
違したパターンに形成される前記複数のリードはチップ
セレクト用リードを有することを特徴とする特許請求の
範囲第１項記載の半導体装置。2. The semiconductor device according to claim 1, wherein said plurality of leads formed in different patterns between said tape carrier packages have chip select leads.
パッケージの封止部は実質同一の形状を有することを特
徴とする特許請求の範囲第１項又は第２項記載の半導体
装置。3. The semiconductor device according to claim 1, wherein the sealing portions of the stacked tape carrier packages have substantially the same shape.
パッゲージは同一種のテープキャリアパッゲージとする
ことを特徴とする特許請求の範囲第１項又は第２項記載
の半導体装置。4. The semiconductor device according to claim 1, wherein the tape carrier packages to be stacked are of the same type.
Priority Applications (13)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62226307A JP2642359B2 (en) | 1987-09-11 | 1987-09-11 | Semiconductor device |
| KR1019880007112A KR970003915B1 (en) | 1987-06-24 | 1988-06-14 | Semiconductor device and the use memory module |
| US07/209,739 US4982265A (en) | 1987-06-24 | 1988-06-22 | Semiconductor integrated circuit device and method of manufacturing the same |
| US07/796,873 US5138438A (en) | 1987-06-24 | 1991-11-25 | Lead connections means for stacked tab packaged IC chips |
| KR1019930010377A KR970003913B1 (en) | 1987-06-24 | 1993-06-09 | Surface mounting method of semiconductor integrated device |
| KR1019930010378A KR970003914B1 (en) | 1987-06-24 | 1993-06-09 | Semiconductor memory module |
| US08/323,709 US5587341A (en) | 1987-06-24 | 1994-10-18 | Process for manufacturing a stacked integrated circuit package |
| US08/763,469 US5708298A (en) | 1987-06-24 | 1996-12-10 | Semiconductor memory module having double-sided stacked memory chip layout |
| US08/984,330 US5910685A (en) | 1987-06-24 | 1997-12-03 | Semiconductor memory module having double-sided stacked memory chip layout |
| US09/292,999 US6262488B1 (en) | 1987-06-24 | 1999-04-16 | Semiconductor memory module having double-sided memory chip layout |
| US09/863,450 US6424030B2 (en) | 1987-06-24 | 2001-05-24 | Semiconductor memory module having double-sided stacked memory chip layout |
| US10/124,281 US6521993B2 (en) | 1987-06-24 | 2002-04-18 | Semiconductor memory module having double-sided stacked memory chip layout |
| US10/341,397 US6693346B2 (en) | 1987-06-24 | 2003-01-14 | Semiconductor memory module having double-sided stacked memory chip layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62226307A JP2642359B2 (en) | 1987-09-11 | 1987-09-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6471162A JPS6471162A (en) | 1989-03-16 |
| JP2642359B2 true JP2642359B2 (en) | 1997-08-20 |
Family
ID=16843154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62226307A Expired - Lifetime JP2642359B2 (en) | 1987-06-24 | 1987-09-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2642359B2 (en) |
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|---|---|---|---|---|
| JPS62142394A (en) * | 1985-12-17 | 1987-06-25 | 松下電子工業株式会社 | Semiconductor package mounting |
| JPS6318654A (en) * | 1986-07-11 | 1988-01-26 | Hitachi Micro Comput Eng Ltd | Electronic device |
-
1987
- 1987-09-11 JP JP62226307A patent/JP2642359B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6471162A (en) | 1989-03-16 |
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