JP2642359B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2642359B2
JP2642359B2 JP62226307A JP22630787A JP2642359B2 JP 2642359 B2 JP2642359 B2 JP 2642359B2 JP 62226307 A JP62226307 A JP 62226307A JP 22630787 A JP22630787 A JP 22630787A JP 2642359 B2 JP2642359 B2 JP 2642359B2
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JP
Japan
Prior art keywords
tape carrier
carrier package
plurality
leads
tape
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Expired - Lifetime
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JP62226307A
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Japanese (ja)
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JPS6471162A (en
Inventor
昌行 渡辺
利夫 管野
喜昭 若島
Original Assignee
日立デバイスエンジニアリング株式会社
株式会社日立製作所
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Priority to JP62226307A priority Critical patent/JP2642359B2/en
Priority claimed from KR88007112A external-priority patent/KR970003915B1/en
Publication of JPS6471162A publication Critical patent/JPS6471162A/en
Priority claimed from US07/796,873 external-priority patent/US5138438A/en
Priority claimed from KR93010378A external-priority patent/KR970003914B1/en
Publication of JP2642359B2 publication Critical patent/JP2642359B2/en
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Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数のテープキャリアパッケージを重ね実装するようにした半導体装置に関する。 DETAILED DESCRIPTION OF THE INVENTION The present invention [relates] relates to a semiconductor device which is adapted to overlap implement multiple tape carrier package.

〔従来の技術〕 [Prior art]

半導体素子の組込技術の一つに、テープキャリア方式がある。 One of the embedded technology of semiconductor devices, there is a tape carrier method. この方式は、フィルムキャリアあるいはTAB(T This method is a film carrier or TAB (T
ape Automated Bonding)方式などとも称されている。 ape Automated Bonding) method are also referred to as such.
この方式は、長尺のスプロケットホール(パーフォレーションホール)付きの樹脂製テープに半導体素子を連続的に組込んでいく方法で、当該テープキャリアは半導体素子(チップ)の電極配置に合わせたリードパターンが、スプロケットホールとデバイスホールを持つ樹脂フィルム上に形成されたもので、例えば、接着剤付きポリイミドフィルムを適宜幅にスリットし、それに送り用のスプロケットホールとチップを組込みするためのデバイスホールとをパンチングし、銅箔をラミネートし、ホトレジスト技術、エッチング技術を用いて所望のリードパターンを形成する工程を経て製造される。 This method is a method to continue a semiconductor device incorporating successively a resin tape with sprocket holes long (perforation holes), the tape carrier is read the pattern to match the electrode arrangement of the semiconductor element (chip) , which was formed on the resin film with sprocket holes and device holes, punching for example, slit into appropriate widths polyimide film with an adhesive, and a device hole for incorporation sprocket holes and chip for feeding thereto and, laminating a copper foil, photoresist technology, it is manufactured through a step of forming a desired lead pattern using an etching technique.

なお、当該テープキャリアについて述べた文献の例としては、マックグローヒルブックカンパニージャパン(Mc Graw−Hill Book Company Japan)社刊1983年コピーライト「VLSI TECHNOLOGY」p558があげられる。 It should be noted, as an example of literature that described for the tape carrier, McGraw Hill Book Company Japan (Mc Graw-Hill Book Company Japan) published by 1983 copyright "VLSI TECHNOLOGY" p558, and the like.

〔発明が解決しようとする課題〕 [Problems that the Invention is to Solve]

しかるに、従来のテープキャリアにあっては、1品種1レイアウトとなっており、同じパターンを持っているために同品種のテープキャリアを重ねて実装用基板に実装することができない。 However, in the conventional tape carrier, it has a 1 cultivar 1 layout, can not be mounted on the mounting substrate to overlap the tape carrier of the same varieties in order to have the same pattern.

そのため、高密度に実装しようとしたら、実装用基板上に同品種のテープキャリアと並べて配設することが必要となり、プリント配線基板などの実装用基板表面の配線を複雑化させ、断線なども生じ易くなり、その信頼性を低下させることになる。 Therefore, if we try to densely, the mounting substrate side by side with the tape carrier of the same varieties must be disposed, thereby complicating the wiring of the mounting substrate surface such as a printed wiring board, occur disconnection easily, thus lowering its reliability.

本発明の目的は、テープキャリアパッケージを重ねて実装し得るようにして高密度実装することができる技術を提供することにある。 An object of the present invention is to provide a technique capable of high-density mounting and adapted to implement overlapping the tape carrier package.

本発明の前記ならびにそのほかの目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔課題を解決するための手段〕 [Means for Solving the Problems]

本願において開示される発明のうち代表的なものの概要を簡単に説明すれば、下記のとおりである。 To briefly explain the summary of typical inventions among the inventions disclosed in this application is as follows.

すなわち、本発明の半導体装置は、デバイスホールを有するフィルムテープと、前記フィルムテープに形成された前記デバイスホールに一部が突出する複数のリードと、前記複数のリードに接合された半導体チップと、前記複数のリードのインナー部および前記半導体チップを封止する樹脂製の封止部とをそれぞれ備えてなる複数のテープキャリアパッケージと、前記それぞれのテープキャリアパッケージが重ねられた状態で実装される実装用基板とからなり、前記それぞれのテープキャリアパッケージの前記封止部から突出する複数のリードパターンが、前記それぞれのテープキャリアパッケージで相違したパターンに形成され、前記それぞれのテープキャリアパッケージの封止部から突出する前記複数のリードの外方端に折り曲げ部が形 That is, the semiconductor device of the present invention includes a film tape having a device hole, a plurality of leads partially protrude into the device hole formed in the film tape, a semiconductor chip bonded to the plurality of leads, a plurality of tape carrier package comprising comprising the plurality of leads of the inner portion and the semiconductor chip resin sealing portion for sealing the respective mounting said each of the tape carrier package is mounted in a state superimposed consists of a use substrate, a plurality of lead patterns protruding from the said sealing portion of each of the tape carrier package, the formed pattern was different in each of the tape carrier package, the sealing portions of the respective tape carrier package wherein the plurality of bent portions outward end of the lead is shaped to protrude from され、前記それぞれのテープキャリアパッケージの封止部から突出する前記複数のリードの前記折り曲げ部を重ねた状態で、前記それぞれのテープキャリアパッケージが前記リードの前記折り曲げ部により前記実装用基板に保持され、前記それぞれのテープキャリアパッケージに共通する信号が入出力されるリードの導通を前記複数のリードを折り曲げ部によって行うようにしたことを特徴とする。 Is, in a state of overlapping the bent portion of the plurality of leads projecting from the sealing portion of each of the tape carrier package, the respective tape carrier package is held in the mounting substrate by the bent portion of the lead characterized in that the signal which is common the the respective tape carrier package is to perform the bent portion of the lead of the plurality of leads conduction to be input and output.

〔作用〕 [Action]

上記のように、リードのインナー部と半導体チップとが樹脂により封止されて形成された各々のテープキャリアパッケージは、それぞれのテープキャリアパッケージの封止部から突出する複数のリードパターンが相違して形成されており、重ね実装が可能となることから、半導体チップの高密度実装が可能となり、配線も簡素化されて装置の信頼性も向上させることができる。 As described above, the tape carrier package of each the inner portion of the leads and the semiconductor chip is formed is sealed with a resin, a plurality of lead patterns protruding from the sealing portions of the respective tape carrier package differs are formed, since it becomes possible overlapping implementation enables high-density mounting of semiconductor chips, the wiring also can also be improved reliability of simplified in apparatus. そして、各々のテープキャリアパッケージはリードの折り曲げ部を重ねた状態で実装用基板に保持されるので、複数のテープキャリアパッケージを一括して接合して実装用基板に実装することができ、半導体装置を迅速に製造することが可能となる。 Since each of the tape carrier package is held on the mounting board in a state of overlapping the bent portion of the lead, can be mounted on the mounting board by bonding collectively a plurality of tape carrier packages, a semiconductor device it is possible to rapidly produce.

〔実施例〕 〔Example〕

次に、本発明の実施例を図面に基づき説明する。 It will now be described based on an embodiment of the present invention with reference to the drawings. 第1 First
図は本発明の実施例を示す原理図であり、プラスチックフィルムテープに穿設されたデバイスホール1内には当該フィルムテープ上に形成されたリードパターン2の一部が突出している。 Figure is a principle view showing an embodiment of the present invention, is in the device hole 1 drilled in the plastic film tape portion of the lead pattern 2 formed on the film tape protrudes. また、当該リードパターン2のうち、第1図(A)における図示上右端のリード2a 1が残りのリード2bに並行に設けられているのに対し、第1図(B)では、図示上右端のリード2a 2が直角に折れ曲った形となっている。 Also, among the lead pattern 2, while the illustration on the right end of the lead 2a 1 are provided in parallel to the rest of the lead 2b in FIG. 1 (A), the first view (B), shown on the right end of lead 2a 2 is in the form of bent bent at a right angle. このデバイスホール1内には、図示していないが半導体素子が組込みされ、第1図(A)では図示右端のリード2a 1が当該デバイスホール1内に組込した半導体素子(チップ)のチップセレクト信号用のリードとなっており、また、第1図(B)では上右端の直角に折り曲がったリード2a 2が同様にチップセレクト信号用のリードとなっている。 The device hole 1, not shown are a semiconductor device is embedded, the chip select of the semiconductor device lead 2a 1 of FIG. 1 (A) In the illustrated right end is embedded in the device hole 1 (chip) has a lead signal, also leads 2a 2 that bent at right angles of the upper right end in FIG. 1 (B) is likewise a lead for the chip select signal.

第1図(C)は、このように各リードパターン2の一部の2a 1 ,2a 2を変更してこれらを変更リードとしたテープキャリアを重ね実装した様子を概念的に示したもので、リード2a 1は重ね実装された上部のチップの当該チップセレクト信号の入出力をつかさどり、また、リード Figure 1 (C) is in this manner conceptually shows a state that implements overlapped tape carriers with these changes lead to change some 2a 1, 2a 2 of the lead pattern 2, lead 2a 1 is responsible for the output of the chip select signal superimposed implemented top of the chip, also lead
2a 1に隣接したリード2a 2は、重ね実装された下部のチップの当該チップセレクト信号の入出力をつかさどるようになっている。 Leads 2a adjacent to 2a 1 2 is adapted to govern the input and output of the chip select signal at the bottom of the chip which is superimposed implemented.

他のリード2bは、各チップに共通の入出力端子となっている。 Other lead 2b is a common input-output terminal to each chip. 第2図は、第1図(A)のテープキャリアの詳細を示したもので、また、第3図は第1図(B)のテープキャリアの詳細を示す。 Figure 2 is intended showing details of the tape carrier of FIG. 1 (A), also FIG. 3 shows the details of the tape carrier of FIG. 1 (B).

これらの図に示すように、プラスチックフィルムテープ3の両端部には、当該テープ3の送りおよび位置合わせ用の複数のスプロケットホール4が適宜間隔を置いて孔設され、また、当該テープ3の中央部には半導体素子を組込むためのデバイスホール1が穿設され、当該デバイスホール1内に突出したリードパターン2の先端部に、図示するようにチップ5をフェイスダウンボンディング(ギャングボンディング)により接合する。 As shown in these figures, at both ends of the plastic film tape 3 has a plurality of sprocket holes 4 for feeding and positioning of the tape 3 is Ana設 at appropriate intervals, also, the center of the tape 3 part device hole 1 for incorporating the semiconductor device is bored in the tip portion of the lead pattern 2 protruding to the device hole 1, the chip 5 as shown are bonded by face-down bonding (gang bonding) .

この接合は、チップ5の電極部にバンプ6を形成して、熱圧着法により行われるが、リードパターン2側にバンプ6を形成して同様に行ってもよい。 This junction forms a bump 6 to the electrodes of the chip 5, is performed by thermocompression bonding may be performed in the same manner to form the bumps 6 to the lead pattern 2 side. 当該チップ5 The chip 5
のボンディング(インナーリードボンディング)後に、 After the bonding (inner lead bonding),
第4図断面図に示すように、封止樹脂をポッティングして樹脂封止部7を形成して封止を行なう。 As shown in Figure 4 a cross-sectional view, performing sealing by forming a resin sealing portion 7 by potting the sealing resin. リードパターン2のうち、この樹脂封止部7から外方に突出した部分がアウター部となり、樹脂封止部7により半導体素子(チップ)とともに封止された部分がインナー部となる。 Of the lead pattern 2, the protruding portion outward from the resin sealing portion 7 is the outer portion, sealed portion with the semiconductor element (chip) is the inner part by resin sealing portion 7.

このように封止されたテープキャリアパッケージ8 Tape carrier package 8 sealed in this way
を、第5図に示すように実装用基板9上に重ね実装する。 And it is superimposed mounted on the mounting substrate 9 as shown in Figure 5.

第5図にて、上部テープキャリアパッケージ8aは、第1図(A)に示すリードパターン2をもつテープキャリアパッケージで、また、下部テープキャリアパッケージ At Figure 5, the upper tape carrier package 8a, a tape carrier package having a lead pattern 2 shown in FIG. 1 (A), The lower tape carrier package
8bは第1図(B)に示すリードパターン2をもつテープキャリアパッケージである。 8b is a tape carrier package having a lead pattern 2 shown in FIG. 1 (B).

第5図に示すように、リードのうちそれぞれのテープキャリアパッケージ8a,8bの封止部から突出したアウター部の外方端には折り曲げ部2c 1 ,2c 2が形成されており、それぞれの折り曲げ部2c 1 ,2c 2によりそれぞれのテープキャリアパッケージ8a,8bが実装用基板9に電気的に接合されて実装される。 As shown in FIG. 5, each of the tape carrier package 8a of the lead, bent portion 2c 1 is outward end of the outer portion projecting from the sealing portion of 8b, 2c 2 is formed, bending of the respective each of the tape carrier package 8a by part 2c 1, 2c 2, 8b are mounted is electrically bonded to the mounting substrate 9.

本発明に使用されるプラスチックフィルムテープは、 Plastic film tapes to be used in the present invention,
例えばポリイミド系樹脂フィルムを適宜幅にスリットされたものにより構成される。 For example constituted by those slit appropriately width polyimide resin film. リードパターン2は、当該フィルムテープ上に例えば銅箔をラミネートし、ホトレジスト技術やエッチング技術を用いて形成することができ、各テープキャリアパッケージ8a,8bに応じてその一部のレイアウトを変更するようにする。 Lead pattern 2 is laminated with, for example, copper foil on the film tape, can be formed by using a photoresist technique and etching technique, each tape carrier package 8a, so as to change a part of the layout according to 8b to.

半導体素子(チップ)5は、例えばシリコン単結晶基板から成り、周知の技術によってこのチップ内には多数の回路素子が形成され、1つの回路機能が与えられている。 A semiconductor element (chip) 5, for example, a silicon single crystal substrate, in this chip by well known techniques a large number of circuit elements are formed, one circuit function is given. 回路素子の具体例は、例えばMOSトランジスタから成り、これらの回路素子によって、例えば論理回路およびメモリの回路機能が形成されている。 Specific examples of the circuit elements, for example, a MOS transistor, these circuit elements, for example, a circuit function of the logic circuit and the memory is formed. バンプ6は、例えば金(Au)バンプにより構成される。 Bumps 6 is constituted by, for example, gold (Au) bumps.

封止に使用されるポッティング樹脂には、例えばエポキシ樹脂を主体としたポッティング液が用いられる。 The potting resin used for the sealing, for example, potting liquid mainly containing epoxy resin. 実装用基板9は、例えばプリント配線基板により構成される。 Mounting substrate 9 is composed of, for example, a printed wiring board.

本発明によれば、上記実施例に示すように、各リードパターン2の一部のリードを相互にパターンが相違した変更リード2a 1 ,2a 2とすることにより、二個のテープキャリアパッケージ8a,8bを実装用基板9上に仮に当該テープキャリアパッケージ8a,8bを並設する場合に比して実装密度を向上させることができ、また、テープキャリアパッケージ8a,8bを並設する場合には配線も長く、複雑化するのに対し短く、簡略化され、断線する割合も低減され、信頼性の向上に寄与する点大である。 According to the present invention, as shown in the above examples, by the change leads 2a 1, 2a 2 having a pattern different from a portion of the leads of the lead pattern 2 mutually, two of the tape carrier package 8a, 8b if the tape carrier package 8a on the mounting substrate 9, 8b can be improved packing density as compared with the case of juxtaposed, also, the wiring in the case of juxtaposed tape carrier package 8a, and 8b even longer, shorter whereas the complex, is simplified, the rate of breakage is also reduced, which contributes point size to improve the reliability.

以上発明者によってなされた発明を実施例にもとづき具体的に説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 Although the invention made by the inventors has been concretely described based on examples, the present invention is not limited to the above embodiments, to say that various modifications are possible without departing from the scope of the invention Absent.

例えば、上記実施例ではテープキャリアパッケージを実装用基板上に二個重ね実装する例を示したが、三個以上重ねることができ、場合により実装用基板の両面にそれぞれ重ね実装することもできる。 For example, in the above embodiment has shown an example in which stacked two on the substrate for mounting a tape carrier package mounting, can stack three or more, it can optionally be overlaid on both surfaces of the mounting substrate mounting.

〔発明の効果〕 〔Effect of the invention〕

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。 To briefly explain advantageous effects obtained by typical ones of the inventions disclosed in this application is as follows.

本発明によれば、各々のパッケージは相互にリードパターンが相違しており、重ね実装が可能となることから、半導体チップの高密度実装が可能となり、配線も簡素化されて装置の信頼性を向上させることができる。 According to the present invention, each of the packages has lead patterns different from one another, since it is possible to overlap mounting enables high-density mounting of semiconductor chips, the wiring also the reliability of the simplified by device it is possible to improve. また、重ね実装される各々のパッケージは、リードのアウター部によりその折り曲げ部を重ねた状態として実装用基板に保持されるので、複数のパッケージを一括して実装用基板に接合することができ、半導体装置を容易かつ迅速に製造することができる。 Also, each package that is overlaid implementation because it is held on the mounting substrate as a laminated state thereof bent portion by the outer portion of the lead can be bonded to the mounting substrate in a lump a plurality of packages, the semiconductor device can be easily and quickly manufactured.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

第1図(A)〜(C)はそれぞれ本発明の実施例を示す原理図、 第2図は本発明の実施例を示す要部平面図、 第3図は本発明の実施例を示す要部平面図、 第4図は本発明の実施例を示す断面図、 第5図は本発明の実施例を示す断面図である。 Figure 1 (A) ~ (C) principle diagram illustrating an embodiment of the present invention, respectively, FIG. 2 is a fragmentary plan view showing an embodiment of the present invention, FIG. 3 is a partial showing an embodiment of the present invention part plan view, Figure 4 is a cross-sectional view showing an embodiment of the present invention, FIG. 5 is a sectional view showing an embodiment of the present invention. 1……デバイスホール、2……リードパターン、2a 1 ,2a 1 ...... device hole, 2 ...... lead pattern, 2a 1, 2a
2 ……変更リード、2b……共通リード、2c 1 ,2c 2 ……折り曲げ部、3……プラスチックフィルムテープ、4……スプロケットホール、5……半導体素子(チップ)、6… 2 ...... change leads, 2b ...... common lead, 2c 1, 2c 2 ...... bent portion, 3 ...... plastic film tape, 4 ...... sprocket holes, 5 ...... semiconductor element (chip), 6 ...
…バンプ、7……樹脂封止部、8,8a,8b……テープキャリアパッケージ、9……実装用基板。 ... bumps, 7 ...... resin sealing portion, 8, 8a, 8b ...... tape carrier package, 9 ...... mounting substrate.

フロントページの続き (72)発明者 若島 喜昭 東京都小平市上水本町1450番地 株式会 社日立製作所武蔵工場内 (56)参考文献 特開 昭63−18654(JP,A) 特開 平1−293556(JP,A) 特開 昭62−142394(JP,A) Of the front page Continued (72) inventor Yoshiaki Wakashima Tokyo Kodaira Josuihon-cho, 1450 address stock company Hitachi, Musashi in the factory (56) Reference Patent Sho 63-18654 (JP, A) JP flat 1-293556 (JP, A) JP Akira 62-142394 (JP, A)

Claims (4)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】デバイスホールを有するフィルムテープと、前記フィルムテープに形成された前記デバイスホールに一部が突出する複数のリードと、前記複数のリードに接合された半導体チップと、前記複数のリードのインナー部および前記半導体チップを封止する樹脂製の封止部とをそれぞれ備えてなる複数のテープキャリアパッケージと、 前記それぞれのテープキャリアパッケージが重ねられた状態で実装される実装用基板とからなり、 前記それぞれのテープキャリアパッケージの前記封止部から突出する複数のリードパターンが、前記それぞれのテープキャリアパッケージで相違したパターンに形成され、 前記それぞれのテープキャリアパッケージの前記封止部から突出する前記複数のリードの外方端に折り曲げ部が形成され、 前記そ A film tape having a 1. A device hole, wherein a plurality of leads film portion in said device hole formed in the tape protrudes, a semiconductor chip bonded to the plurality of leads, said plurality of leads from a plurality of tape carrier package comprising respectively provided a sealing portion made of resin for sealing the inner portion and the semiconductor chip, a mounting substrate for the being implemented in each state in which the tape carrier package is superimposed becomes, a plurality of lead patterns protruding from the said sealing portion of each of the tape carrier package, the formed pattern was different in each of the tape carrier package, protruding from the said sealing portion of each of the tape carrier package the bent portion outward ends of the plurality of leads are formed, the Resona れぞれのテープキャリアパッケージの前記封止部から突出する前記複数のリードの前記折り曲げ部を重ねた状態で、前記それぞれのテープキャリアパッケージが前記リードの前記折り曲げ部により前記実装用基板に保持され、 前記それぞれのテープキャリアパッケージに共通する信号が入出力されるリードの導通を前記複数のリードを折り曲げ部によって行うようにしたことを特徴とする半導体装置。 In a state of overlapping the bent portion of the plurality of leads projecting from the sealing portion of the tape carrier package respectively, the respective tape carrier package is held in the mounting substrate by the bent portion of the lead , wherein a signal common said each of the tape carrier package is to perform the bent portion of the plurality of leads conduction leads are input.
  2. 【請求項2】前記テープキャリアパッケージ相互間で相違したパターンに形成される前記複数のリードはチップセレクト用リードを有することを特徴とする特許請求の範囲第1項記載の半導体装置。 Wherein said plurality of leads formed in different patterns between the tape carrier package mutual semiconductor device according claims first term of which is characterized by having a lead for chip select.
  3. 【請求項3】前記積層されるそれぞれのテープキャリアパッケージの封止部は実質同一の形状を有することを特徴とする特許請求の範囲第1項又は第2項記載の半導体装置。 Wherein the respective sealing portions of the tape carrier package semiconductor device in the range described paragraph 1 or 2 claims, characterized in that it has a substantially same shape to be laminated.
  4. 【請求項4】前記積層されるそれぞれのテープキャリアパッゲージは同一種のテープキャリアパッゲージとすることを特徴とする特許請求の範囲第1項又は第2項記載の半導体装置。 Wherein said each of the tape carrier package gauges stacked semiconductor device of Claims paragraph 1 or 2, wherein a is the same kind of tape carrier package gauge.
JP62226307A 1987-09-11 1987-09-11 Semiconductor device Expired - Lifetime JP2642359B2 (en)

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Application Number Priority Date Filing Date Title
JP62226307A JP2642359B2 (en) 1987-09-11 1987-09-11 Semiconductor device

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
JP62226307A JP2642359B2 (en) 1987-09-11 1987-09-11 Semiconductor device
KR88007112A KR970003915B1 (en) 1987-06-24 1988-06-14 Semiconductor device and the use memory module
US07/209,739 US4982265A (en) 1987-06-24 1988-06-22 Semiconductor integrated circuit device and method of manufacturing the same
US07/796,873 US5138438A (en) 1987-06-24 1991-11-25 Lead connections means for stacked tab packaged IC chips
KR93010378A KR970003914B1 (en) 1987-06-24 1993-06-09 Semiconductor memory module
KR93010377A KR970003913B1 (en) 1987-06-24 1993-06-09 Surface mounting method of semiconductor integrated device
US08/323,709 US5587341A (en) 1987-06-24 1994-10-18 Process for manufacturing a stacked integrated circuit package
US08/763,469 US5708298A (en) 1987-06-24 1996-12-10 Semiconductor memory module having double-sided stacked memory chip layout
US08/984,330 US5910685A (en) 1987-06-24 1997-12-03 Semiconductor memory module having double-sided stacked memory chip layout
US09/292,999 US6262488B1 (en) 1987-06-24 1999-04-16 Semiconductor memory module having double-sided memory chip layout
US09/863,450 US6424030B2 (en) 1987-06-24 2001-05-24 Semiconductor memory module having double-sided stacked memory chip layout
US10/124,281 US6521993B2 (en) 1987-06-24 2002-04-18 Semiconductor memory module having double-sided stacked memory chip layout
US10/341,397 US6693346B2 (en) 1987-06-24 2003-01-14 Semiconductor memory module having double-sided stacked memory chip layout

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JP2642359B2 true JP2642359B2 (en) 1997-08-20

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