JPS62142394A - Semiconductor package mounting - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for mounting semiconductor packages, and in particular is aimed at enabling high-density packaging.

BACKGROUND OF THE INVENTION Conventionally, in order to mount resin-sealed type packages or ceramic type pancages at high density using lead frames, the external dimensions of the package have been reduced by reducing the lead spacing. In addition, some products employ package shapes suitable for miniaturization, such as chip carriers and flat packages. That is, a high-density mounting method has been adopted in which the area occupied by the mounting board is reduced by converting one semiconductor package itself into an IJS type.

Problems to be Solved by the Invention The present invention attempts to solve the problem that in the conventional board mounting method using a resin-sealed type or ceramic type package, the area occupied by the semiconductor package on the mounted board inevitably becomes large. It is something.

Conventionally, semiconductor packages have been miniaturized to enable high-density packaging. Standard lead pitch of 10
The thickness has been narrowed from 0 mil to 50 to 20 mil, and semiconductor packages have become smaller accordingly. As the lead spacing becomes narrower, the capacitance between adjacent leads can no longer be ignored, and when mounted, there is a risk that adjacent leads may come into contact through the conductor. has its limits.

The present invention does not need to use a particularly miniaturized semiconductor package, but rather uses a conventional semiconductor package to reduce the area occupied by the semiconductor pancake on the mounting board.

Means for Solving the Problems Semiconductor back cages are mounted in two stacked layers, and each of the upper and lower semiconductor packages is stacked and mounted at a predetermined position on a mounting board.

Function The above-mentioned two-tiered configuration allows for a combination of semiconductor packages that can be stacked in two-tiered configurations without the need to further reduce the size of the semiconductor package, making it possible to double the board mounting density up to twice that of the conventional single-tiered configuration. It is possible to improve the

Embodiment The figure is a mounting cross-sectional structure diagram showing a mounting method of a two-tier structure of semiconductor packages according to an embodiment of the present invention. The figure is a surface mount example, and the semiconductor package 1 in the lower tier is a resin-sealed type. The lead is gull wing (G) in SO package.
ULL-WING) type. The upper semiconductor package 2 is a resin-sealed dual in-line package, and the leads are of a BUTT type.

The lower package may be a leadless chip carrier, a pin grid array, a flat package, etc. in addition to the package of the above embodiment. The leads of the flat package can be in two directions or in four directions, and may be in a J-shape shape. As long as the leads of the upper and lower packages do not come into contact with each other in the actual state, the shape and number of leads are not limited.

The upper package does not necessarily have to be larger than the lower package. They may have the same shape except for the lead portion. For example, the leads of the upper package may be made longer than those of the lower package so that they reach the board mounting surface.

To attach the upper and lower packages to the board, you can temporarily attach the lower package to the board, then stack the upper package and connect it to the board using vapor phase soldering, or by gluing the upper and lower packages together in advance. It is also possible to attach it to the board after adhering it with an adhesive or the like, and then connect it to the board by vapor phase soldering or the like.

Effects of the Invention As described above, when the present invention is used, the area occupied by the semiconductor package on the board can be suppressed without particularly reducing the size of the semiconductor package, and high-density packaging becomes possible. If a small package is used, even higher density packaging is possible.

[Brief explanation of drawings]

The figure is a cross-sectional structural diagram of an embodiment of the present invention. 1...Lower semiconductor package, 2...Upper semiconductor path cage, 3...No., 4...
・Surface mount board, 5... Conductor. Name of agent: Patent attorney Toshio Nakao and one other person

Claims (1)

[Claims] 1. A method for mounting a semiconductor package, comprising mounting a first semiconductor package in a lower stage and a second semiconductor package having a shape different from that of the first semiconductor package in an upper stage, in a two-tier stacked configuration.