JPH05235090A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the chip size of a semiconductor integrated circuit by a method wherein rectangular pads whose lateral side is longer than longitudinal side and other rectangular pads whose lateral side is shorter than longitudinal side are alternately arranged in parallel with each other. CONSTITUTION:Pads 1 and pads 2 are alternately arranged in parallel with each other. A lateral side X1 along an X axis and a longitudinal side Y1 along a Y of the pad 1 are set so as to satisfy a formula, X1<=Y1, and a lateral side X2 along an X axis and a longitudinal side Y2 along a Y axis of the pad 2 are set so as to satisfy a formula, X2<=Y2. The pads 1 and 2 are made to serve as fundamental parts and arrange in a few rows, so that a chip can be lessened in size. The pads 1 and 2 are connected to inner leads 6 respectively. The pads 1 in a first row are arranged so as to satisfy the above formula, X1<=Y1, and the pads 2 in a second row are arranged so as to satisfy the above formula, X2<=Y2, where the long side of a chip 10 is parallel with a Y axis.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to the arrangement and shape of the pad.

[0002]

2. Description of the Related Art Conventionally, a pad layout and a shape in a semiconductor integrated circuit have been packaged in a TCP (Tape) package.
In the case of Carrier Package), the one shown in FIG. 2 or FIG. 3 is used in order to reduce the area occupied by the pad portion in the chip.

Conventionally, the T connected to the chip 10a pad
The pitch of the CP inner leads 6 is about 90 μm
Since the size margin between the pads is insufficient to connect with the square pads 3 and 4 each having a size of about 150 μm and one side of about 100 μm, the pads 3, 3 are staggered as shown in FIG.
Often, 4 was arranged in parallel.

In some cases, as shown in FIG. 3, rectangular pads 5 are arranged in parallel to match the pitch of the inner leads 6 with the pad pitch and to secure a connection area between the inner leads 6 and the pads 5. ..

[0005]

In the conventional pad arrangement and shape, if the inner lead pitch is about 80 μm or less, it is not efficient to reduce the chip area.

An object of the present invention is to solve such problems and provide a semiconductor integrated circuit having a small chip area.

[0007]

A semiconductor integrated circuit according to the present invention has a structure in which a horizontally long rectangular pad whose one side is longer than the length of the other side and a vertically long rectangular pad whose one side is shorter than the length of the other side. Rectangular pads are arranged in parallel and alternately.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a pad layout view of an embodiment of the present invention. In this embodiment, the positional relationship between the pad 1 and the pad 2 is parallel and alternating, and the shape of the pad 1 is X ₁ ≦ Y _{1 where} the X axis is shorter than the Y axis, and the shape of the pad 2 is The Y-axis is shorter than the X-axis and X ₂ ≧ Y ₂ , and the two pads 1 and 2 are used as a base, and the basic pads are arranged in several stages, so that the chip size can be reduced. .. The pads 1 and 2 are connected to the inner lead 6.

When the pads are arranged in parallel and alternately, since the TCP inner leads 6 are arranged between the pads 1 in the first row, it is necessary to set the distance between the pads to the inner leads as a design margin or more. .. Further, since the inner leads 6 are not arranged between the pads 2 in the second row, it is not necessary to secure a margin between the pads and the inner leads. Therefore, the pad 1 in the first row is arranged vertically long with respect to the long side of the chip 10 and the pad 2 in the second row is arranged horizontally long in order to obtain the highest area efficiency in the layout of the pads.

For example, in the case of a 240-output semiconductor integrated circuit, the chip size is 15 mm × 5 mm, and the pad size of the conventional example (FIG. 2) in which 120 pads are arranged on the opposite long sides of the chip is 0.12 mm. × 0.12 mm
And the pad size of this embodiment is 0.8 mm × 0.18
mm, 0.12 mm × 0.12 mm, the X direction is shortened by 0.04 mm × 60 = 2.4 mm, and the Y direction is lengthened by 0.06 × 2 = 0.12 mm. Therefore,
Chip size is 12.6 x 5.12 = 64.512 mm
^{It is 2} , which is a reduction of nearly 14%.

[0011]

As described above, according to the present invention, the chip size is 10 to 20 compared with the conventional pad arrangement and shape.
It has an effect that it can be reduced by%.

[Brief description of drawings]

FIG. 1 is a pad layout diagram of an embodiment of the present invention.

FIG. 2 is a pad layout diagram of an example of a conventional semiconductor integrated circuit.

FIG. 3 is a pad layout view of another conventional semiconductor integrated circuit.

[Explanation of symbols]

1 to 5 pad 6 inner lead of TCP 10 chip X ₁ to ₅ length of pad ₁ to ₅ in X direction Y ₁ to ₅ length of pad ₁ to ₅ in Y direction

Claims (1)

[Claims] 1. A horizontally long rectangular pad whose one side is longer than the other side and a vertically long rectangular pad whose one side is shorter than the other side are alternately arranged in parallel. A semiconductor device characterized by the above.