JPS60147126A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60147126A
JPS60147126A JP59002051A JP205184A JPS60147126A JP S60147126 A JPS60147126 A JP S60147126A JP 59002051 A JP59002051 A JP 59002051A JP 205184 A JP205184 A JP 205184A JP S60147126 A JPS60147126 A JP S60147126A
Authority
JP
Japan
Prior art keywords
pad
wire
chip
pads
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59002051A
Other languages
Japanese (ja)
Inventor
Takao Fujizu
隆夫 藤津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59002051A priority Critical patent/JPS60147126A/en
Publication of JPS60147126A publication Critical patent/JPS60147126A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable to arrange the greatest number of pads in the same-sized chips by a method wherein the shortest distance of the wires connected to an arbitrary pad and other pad is maintained constant. CONSTITUTION:The first pad 12a is provided on the center line 15 of a chip 11, and a wire 13a is provided on the extension line. The second pad 12b is provided at the point, which is aparted as far as the prescribed distance Q from the pad 12a, on the virtual line 17 provided on the side 16 of the chip virtical to the center line 15. The lead of the lead frame which is provided opposing to the pad 12b on the circumference of the chip 11 is connected by a wire 13b. The third pad 12c is provided at the point where the line in parallel with the wire 13b and the virtual line 17 aparting as far as the equidistance Q. When pads are arranged along the circumference of chips in the same manner as above, the shortest distance between each pad and the wire bonded to the adjoining pad can be maintained constant on every position of the chips.

Description

【発明の詳細な説明】 〈発明の技術分野〉 本発明は半導体装置に係シ、特にワイヤーポンディング
に好適するように半導体チップのポンディングパッドの
配置を改良した構造に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a structure in which the arrangement of bonding pads of a semiconductor chip is improved so as to be suitable for wire bonding.

〈発明の技術的背景とその問題点〉 半導体装置、特に集積回路装置において、半導体チップ
（以後チップと略称する）のポンディングパッド（以後
パッドと略称する）をリードフレームのリード（以後リ
ードと略称する）に接続し導出するのに一般にワイヤボ
ンディング（以後ポンディングと略称する）によってい
る。従来のパッドの・配置例を第１図に示す。図面中に
示すように、チップ（１）上に配置されたパッド（２ａ
、２ｂ。<Technical background of the invention and its problems> In semiconductor devices, especially integrated circuit devices, bonding pads (hereinafter referred to as pads) of semiconductor chips (hereinafter referred to as chips) are bonded to leads of lead frames (hereinafter referred to as leads). Wire bonding (hereinafter abbreviated as bonding) is generally used to connect and lead out the wire (hereinafter referred to as bonding). An example of a conventional pad arrangement is shown in FIG. As shown in the drawing, pads (2a) placed on the chip (1)
, 2b.

２ｃ、２ｄ、・・・）はチップ（１）の辺に沿って設け
られ、−ドをポンディングすると第２図のようになる。2c, 2d, . . . ) are provided along the sides of the chip (1), and when the - cord is pounded, it becomes as shown in FIG.

この場合、任意のパッド、例えばパッド（２ａ）と他の
パッドに接続されたワイヤ、この場合はワイヤ（３ｂ）
との最短距離Ｐは次式で与えられるっＰ　＝　Ｄ　ｃｏ
ｓ　ｇＢＡｃ すなわちワイヤ間の最短距＠Ｐはパッド間距離りと、Ｉ
；ＢＡＣによシ影響を受ける。このことは、パッドの数
が多くなシパクド間距離りが小さくなるＫつれて、［Ｂ
ＡＣの大なる部分、すなわちチップのコーナーに近い部
分のワイヤ間距離が小さくなるし ことを示している。ことで、第２図のワイヤ（３／）を
ボンディングした後ワイヤ（３り）をボンディングする
場合、ワイヤ間の最短距離Ｐが所定量以下になると一第
３図に示すような不都合が生ずる。すなわちワイヤ（３
ｒ）のボンディングの際ボンデインう。またチップのコ
ーナ一部では第２図に示すように、ワイヤの長さも長く
なるため、ワイヤ間最短距離Ｐが小さくなると、ワイヤ
間の短絡がしやすくなるという問題もあった。以上の理
由からパッドを等間隔に配置する場合は、パッド数の増
大に伴ないチップコーナ一部でのパッドにおいて、ワイ
ヤ間最短距離Ｐが短くなシ、この距離でパッド間隔りの
最小間隔が規制されるため、パッド間隔の縮小つＳでき
なかった。In this case, any pad, e.g. pad (2a) and a wire connected to another pad, in this case wire (3b)
The shortest distance P is given by the following formula: P = D co
s gBAc In other words, the shortest distance between wires @P is the distance between pads and I
; Affected by BAC. This means that as the number of pads increases and the distance between pads decreases, [B
This shows that the distance between the wires in a large part of the AC, that is, in the part near the corner of the chip, becomes smaller. Therefore, when the wire (3/) in FIG. 2 is bonded and then the wire (3) is bonded, if the shortest distance P between the wires becomes less than a predetermined amount, a problem as shown in FIG. 3 occurs. That is, the wire (3
When bonding (r), perform bonding. In addition, as shown in FIG. 2, the length of the wires becomes longer at some corners of the chip, so that when the shortest distance P between the wires becomes smaller, short circuits between the wires become more likely to occur. For the above reasons, when arranging pads at equal intervals, as the number of pads increases, the shortest distance P between wires at some pads at the chip corners becomes shorter. Due to restrictions, it was not possible to reduce the pad spacing.

また、パッド間隔を等間隔にせず、パッドの位置によっ
て間隔をかえてゆき、チップコーナ一部でのパッド間隔
を広げた半導体装置は特開昭５６−１２２１４４号公報
に見られるが、パッド間隔を必要最小限にまで狭くする
には至っていない。In addition, a semiconductor device in which the pad spacing is not made equal but is varied depending on the pad position, and the pad spacing is widened at a part of the chip corner is seen in Japanese Patent Application Laid-Open No. 122144/1983. It has not yet been narrowed down to the necessary minimum.

〈発明の目的〉 本発明は高集積化しパッド数の増大しつつある半導体装
置に対し最適なパッド配置を施すことを目的とする。<Objective of the Invention> An object of the present invention is to provide optimal pad arrangement for semiconductor devices which are becoming highly integrated and the number of pads is increasing.

〈発明の概要〉 本発明はワイヤボンディングを施す半導体装置に対して
、任意のパッドと他のパッドに接続されたワイヤとの最
短距離を一定にすることを特徴とし、これによって同一
チップサイズにおいて最大数のパッドを配置することを
可能としたものである０ 〈発明の実施例〉 以下、本発明を実施例例より図面を用いながら説明する
。第４図は本発明の１つの実施例を示す図である。本実
施例はチップ住１）の中心線（１９玉に第　７１番目の
パッド（１２ａ）を、また、中心線ｕ５）の延長線上に
ワイヤ（１３ａ）を設けている。この第１番目のパッド
（１，２ａ）と隣接する第２番目のパッド（１２ｂ）の
位置は従来と同じ方法により定めている。すなわち中心
線（１９に垂直なチップの一辺αｅに並行に設けられた
仮想線αη上でパッド（１２ａ）から所定の距離Ｑだけ
離れた点に第２番目のパッド（１２ｂ）を設けた。ここ
でＱはボンディングキャビラリイのサイズより大きくな
ければならない。例えば、ボンディングキ、ヤピラリイ
が直径１２０１Ｘｎの場合、Ｑは１２０〜１３０μｍが
望ま−しい。第２番目のパッド（１２ｂ　）と、これに
対向してチップαＤの周囲に設けられたリードフレーム
のリードとはワイヤ（１３ｂ）で接続されている。通常
、このワイヤ（１３ｂ）をパッド（１２ｂ）方向に延長
すると、チップの中心α荀を通るようになっている。<Summary of the Invention> The present invention is characterized in that for a semiconductor device subjected to wire bonding, the shortest distance between any pad and a wire connected to another pad is kept constant, and thereby the maximum Embodiments of the Invention The present invention will be described below with reference to embodiments and drawings. FIG. 4 is a diagram showing one embodiment of the present invention. In this embodiment, a 71st pad (12a) is provided on the center line (19 balls) of the chip housing 1), and a wire (13a) is provided on an extension of the center line u5. The position of the second pad (12b) adjacent to the first pad (1, 2a) is determined by the same method as in the prior art. That is, the second pad (12b) was provided at a point separated by a predetermined distance Q from the pad (12a) on an imaginary line αη provided in parallel to one side αe of the chip perpendicular to the center line (19). Q must be larger than the size of the bonding cavity. For example, if the diameter of the bonding cavity is 1201Xn, Q is preferably 120 to 130 μm. It is connected to the leads of the lead frame provided around the chip αD by a wire (13b).Normally, when this wire (13b) is extended toward the pad (12b), it passes through the center α of the chip. It has become.

次に第２番目のパッド（１２ｂ）に隣接する第３番目の
パッド（１２Ｃ）の位置の定め方を述べる０まず第２番
目のパッド（Ｌ２ｂ　）と対向するリードフレームのリ
ードとを接続するワイヤ（１３ｂ）の、第２番目のパッ
ド（１２ｂ）と最短距離にあるチップのコーナー０側に
、等距離Ｑだけ離してワイヤ（１３ｂ）Ｋ平行な線を引
く（図示しない）。この平行線と前述した仮想線αηと
交わる点に第３番目のパッド（１２ｃ）を設けた。以下
第３番目のパッド（１２Ｃ）に隣接する第４番目のパッ
ド（１２ｄ）の位置も、パッド（１２ｃ）と対向するリ
ードフレームのリードを結ぶワイヤ（１３Ｃ）を基鵡に
して同様にめることができた。以下第４番目のパッド（
１２ｄ　）に隣接するパッド（１２ｅ）の位置も同様で
ある。この様にパッドをチップの周辺に沿って配設）る
と、各パッドは隣接するパッドにボンディングされてい
るワイヤとの最短距離を、チップのどの位置にあっても
一定に保つことができた。尚、本実施例で説明したＱの
値は半導体チップ（１１１の全体に暇って厳密に） 一定であ〆必要はなく、さきに述べたボンディングキャ
ピラリイが直径１２０μｍの例では、Ｑの値はほぼ１２
０〜１３０μｍの範囲内にあれば本発明は実施できる。Next, we will discuss how to determine the position of the third pad (12C) adjacent to the second pad (12b)0 First, we will discuss the wire that connects the second pad (L2b) and the lead of the opposing lead frame. On the corner 0 side of the chip that is the shortest distance from the second pad (12b) in (13b), draw a line parallel to the wire (13b) K at an equal distance Q (not shown). A third pad (12c) was provided at the point where this parallel line intersects with the aforementioned virtual line αη. Below, the position of the fourth pad (12d) adjacent to the third pad (12C) is similarly set using the wire (13C) that connects the lead of the lead frame facing the pad (12c). I was able to do that. Below is the fourth pad (
The same applies to the position of the pad (12e) adjacent to pad (12d). By arranging the pads in this way (along the periphery of the chip), the shortest distance between each pad and the wire bonded to the adjacent pad could be kept constant no matter where it was located on the chip. . Note that the value of Q explained in this example is constant for the entire semiconductor chip (111) and does not need to be fixed, and in the example where the bonding capillary is 120 μm in diameter, the value of Q is almost 12
The present invention can be carried out within the range of 0 to 130 μm.

〈発明の効果〉 本発明によるパッド配置を有する半導体装置の半導体チ
ップでは、パッドとワイヤの最短距離が設計者の必要と
する一定量にすることができるので、ワイヤボンディン
グの際、ボンディングキャビラリイがボンディング済み
のワイヤと接触することがなくなった。また同じ理由に
より、ワイヤ間の短絡という事も少くなった。<Effects of the Invention> In the semiconductor chip of the semiconductor device having the pad arrangement according to the present invention, the shortest distance between the pad and the wire can be set to a certain amount required by the designer. No more contact with bonded wires. Also, for the same reason, short circuits between wires have become less common.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のポンディングパッドの配置を説明する図
、第２図は従来のワイヤ接続状態を説明するだめの図、
第３図は従来の配置の欠点を説明するための断面図、第
４図は本発明に係るポンディングパッドの配置とその配
線図である。 １１・・・半導体チップ、 １２８〜１２ｅ・・・ポンディングパッド、１３８〜１
３ｅ・・・ワイヤ、 １６・・・半導体チップの辺、 １７・・・仮想線、 １８・・・半導体チップのコーナー。 代理人　弁理士　則　近　憲　佑 （ほか１名） 第１１！１Figure 1 is a diagram explaining the arrangement of conventional bonding pads, Figure 2 is a diagram explaining the conventional wire connection state,
FIG. 3 is a sectional view for explaining the drawbacks of the conventional arrangement, and FIG. 4 is a diagram showing the arrangement of the bonding pads and its wiring diagram according to the present invention. 11...Semiconductor chip, 128-12e...Ponding pad, 138-1
3e...Wire, 16...Semiconductor chip side, 17...Virtual line, 18...Semiconductor chip corner. Agent Patent Attorney Noriyuki Chika (and 1 other person) No. 11!1

Claims (1)

【特許請求の範囲】[Claims] 半導体チップと、この半導体チップの周辺に沿って配設
された複数のポンディングパッドと、このポンディング
パッドに夫々対向して前記半導体チップの周囲に設けら
れたリードフレームの複数のリードと、これらのリード
と前記ボンデ、イングバッドとを接続するワイヤとを具
備し、任意のポンディングパッドに接続されたワイヤと
、前記任意のポンディングパッドと最近−接する半導体
チップのコーナーの側に隣接するポンディングパッドと
の距離が前記半導体チップの全体に亘ってほぼ一定であ
ることを特徴とする半導体装置。A semiconductor chip, a plurality of bonding pads arranged along the periphery of the semiconductor chip, a plurality of leads of a lead frame provided around the semiconductor chip facing each of the bonding pads, and these and a wire connecting the lead and the bonding pad, the wire connected to any bonding pad, and the bonding pad adjacent to the corner of the semiconductor chip closest to the bonding pad. A semiconductor device characterized in that a distance from a pad to a pad is substantially constant over the entire semiconductor chip.
JP59002051A 1984-01-11 1984-01-11 Semiconductor device Pending JPS60147126A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59002051A JPS60147126A (en) 1984-01-11 1984-01-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59002051A JPS60147126A (en) 1984-01-11 1984-01-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60147126A true JPS60147126A (en) 1985-08-03

Family

ID=11518533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59002051A Pending JPS60147126A (en) 1984-01-11 1984-01-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60147126A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323548B1 (en) 1997-09-29 2001-11-27 Rohm Co., Ltd Semiconductor integrated circuit device
JP2008166621A (en) * 2006-12-29 2008-07-17 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323548B1 (en) 1997-09-29 2001-11-27 Rohm Co., Ltd Semiconductor integrated circuit device
JP2008166621A (en) * 2006-12-29 2008-07-17 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof

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